CN103026630B - 具有可调谐带宽的跟踪与保持架构 - Google Patents

具有可调谐带宽的跟踪与保持架构 Download PDF

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Publication number
CN103026630B
CN103026630B CN201180036519.XA CN201180036519A CN103026630B CN 103026630 B CN103026630 B CN 103026630B CN 201180036519 A CN201180036519 A CN 201180036519A CN 103026630 B CN103026630 B CN 103026630B
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coupled
transistor
circuit
adc
electrode
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CN103026630A (zh
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罗伯特·F·佩恩
马尔科·科西
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Texas Instruments Inc
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
CN201180036519.XA 2010-08-17 2011-08-17 具有可调谐带宽的跟踪与保持架构 Active CN103026630B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/857,674 2010-08-17
US12/857,674 US8248282B2 (en) 2010-08-17 2010-08-17 Track and hold architecture with tunable bandwidth
PCT/US2011/048037 WO2012024371A2 (en) 2010-08-17 2011-08-17 Track and hold architecture with tunable bandwidth

Publications (2)

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CN103026630A CN103026630A (zh) 2013-04-03
CN103026630B true CN103026630B (zh) 2016-10-12

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US (2) US8248282B2 (enExample)
JP (1) JP5940537B2 (enExample)
CN (1) CN103026630B (enExample)
WO (1) WO2012024371A2 (enExample)

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TWI849512B (zh) * 2016-09-12 2024-07-21 美商美國亞德諾半導體公司 自舉式切換電路
CN107294534B (zh) * 2017-05-15 2020-10-23 中山大学 用于窄带信号采样的双通道tiadc频响失配实时校正方法
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CN107359877B (zh) * 2017-06-28 2020-07-10 中国工程物理研究院电子工程研究所 超宽带信号的时间交织采样adc全数字盲补偿方法
US11387890B2 (en) * 2017-09-26 2022-07-12 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for DC offset degradation
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US11601121B2 (en) * 2020-06-26 2023-03-07 Intel Corporation Bootstrapped switch circuit, a track-and-hold circuit, an analog-to-digital converter, a method for operating a track-and-hold circuit, a base station and a mobile device
WO2022113269A1 (ja) * 2020-11-27 2022-06-02 日本電信電話株式会社 タイムインターリーブ型ａｄｃ
CN114157298B (zh) * 2021-11-12 2022-11-01 华中科技大学 一种ti-adc带宽不匹配的校准方法和系统
JP2023136003A (ja) * 2022-03-16 2023-09-29 キオクシア株式会社 半導体集積回路、受信装置、及び受信方法
WO2023202782A1 (en) * 2022-04-22 2023-10-26 Telefonaktiebolaget Lm Ericsson (Publ) A sample-and-hold (s/h) transfer function with constant group delay
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Also Published As

Publication number Publication date
US9013339B2 (en) 2015-04-21
US20130015990A1 (en) 2013-01-17
WO2012024371A3 (en) 2012-04-12
JP2013535943A (ja) 2013-09-12
WO2012024371A2 (en) 2012-02-23
US20120044004A1 (en) 2012-02-23
JP5940537B2 (ja) 2016-06-29
US8248282B2 (en) 2012-08-21
CN103026630A (zh) 2013-04-03

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