CN103003938B - 形成包括具有与另一芯片前后接合的薄的间置芯片的多芯片层叠结构的方法 - Google Patents

形成包括具有与另一芯片前后接合的薄的间置芯片的多芯片层叠结构的方法 Download PDF

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Publication number
CN103003938B
CN103003938B CN201180015676.2A CN201180015676A CN103003938B CN 103003938 B CN103003938 B CN 103003938B CN 201180015676 A CN201180015676 A CN 201180015676A CN 103003938 B CN103003938 B CN 103003938B
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China
Prior art keywords
array
semiconductor
substrate
solder
semiconductor chip
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Expired - Fee Related
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CN201180015676.2A
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English (en)
Chinese (zh)
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CN103003938A (zh
Inventor
M·G·法鲁克
K·S·皮特拉卡
R·P·沃兰
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201180015676.2A 2010-03-25 2011-03-03 形成包括具有与另一芯片前后接合的薄的间置芯片的多芯片层叠结构的方法 Expired - Fee Related CN103003938B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/731,487 2010-03-25
US12/731,487 US8114707B2 (en) 2010-03-25 2010-03-25 Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip
PCT/US2011/026957 WO2011119308A2 (en) 2010-03-25 2011-03-03 Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip

Publications (2)

Publication Number Publication Date
CN103003938A CN103003938A (zh) 2013-03-27
CN103003938B true CN103003938B (zh) 2016-01-13

Family

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Family Applications (1)

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CN201180015676.2A Expired - Fee Related CN103003938B (zh) 2010-03-25 2011-03-03 形成包括具有与另一芯片前后接合的薄的间置芯片的多芯片层叠结构的方法

Country Status (5)

Country Link
US (1) US8114707B2 (https=)
JP (1) JP5505918B2 (https=)
CN (1) CN103003938B (https=)
GB (1) GB2492026B (https=)
WO (1) WO2011119308A2 (https=)

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US9093396B2 (en) * 2011-10-31 2015-07-28 Masahiro Lee Silicon interposer systems
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KR102008014B1 (ko) 2012-10-15 2019-08-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR101366461B1 (ko) * 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101473093B1 (ko) * 2013-03-22 2014-12-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR102041502B1 (ko) 2013-04-01 2019-11-07 삼성전자 주식회사 관통 전극 및 접착 층을 갖는 반도체 패키지
CN103545297A (zh) * 2013-10-25 2014-01-29 矽力杰半导体技术(杭州)有限公司 多芯片叠合封装结构及其制作方法
US9059333B1 (en) 2013-12-04 2015-06-16 International Business Machines Corporation Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
JP2016058596A (ja) * 2014-09-11 2016-04-21 ソニー株式会社 電子デバイス、部品実装基板及び電子機器
US9496188B2 (en) 2015-03-30 2016-11-15 International Business Machines Corporation Soldering three dimensional integrated circuits
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10797039B2 (en) * 2016-12-07 2020-10-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
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JP2019220621A (ja) * 2018-06-21 2019-12-26 キオクシア株式会社 半導体装置及びその製造方法
US11088114B2 (en) 2019-11-01 2021-08-10 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
US10998271B1 (en) * 2019-11-01 2021-05-04 Micron Technology, Inc. High density pillar interconnect conversion with stack to substrate connection
CN111293046B (zh) * 2020-02-20 2022-05-03 西安微电子技术研究所 一种芯片与tsv硅基板的倒扣焊接方法
US11532582B2 (en) * 2020-08-25 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device package and method of manufacture
US20230093258A1 (en) * 2021-09-23 2023-03-23 Intel Corporation Glass patch integration into an electronic device package
CN114446806A (zh) * 2021-12-28 2022-05-06 深圳市紫光同创电子有限公司 裸片到裸片的互连电路中半导体组件、集成电路封装方法
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Also Published As

Publication number Publication date
CN103003938A (zh) 2013-03-27
US20110237026A1 (en) 2011-09-29
WO2011119308A3 (en) 2011-12-29
GB2492026A (en) 2012-12-19
JP2013524486A (ja) 2013-06-17
WO2011119308A2 (en) 2011-09-29
JP5505918B2 (ja) 2014-05-28
US8114707B2 (en) 2012-02-14
GB201218457D0 (en) 2012-11-28
GB2492026B (en) 2013-09-04

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Effective date of registration: 20171113

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Patentee before: Core USA second LLC

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