CN102893387B - 基于石墨烯沟道的器件及其制造方法 - Google Patents

基于石墨烯沟道的器件及其制造方法 Download PDF

Info

Publication number
CN102893387B
CN102893387B CN201180024337.0A CN201180024337A CN102893387B CN 102893387 B CN102893387 B CN 102893387B CN 201180024337 A CN201180024337 A CN 201180024337A CN 102893387 B CN102893387 B CN 102893387B
Authority
CN
China
Prior art keywords
graphene
contact
wafer
channel
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180024337.0A
Other languages
English (en)
Other versions
CN102893387A (zh
Inventor
K·陈
Y-M·林
P·阿沃里斯
D·B·法默
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN102893387A publication Critical patent/CN102893387A/zh
Application granted granted Critical
Publication of CN102893387B publication Critical patent/CN102893387B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Carbon And Carbon Compounds (AREA)

Abstract

提供基于石墨烯沟道的器件及其制造技术。在一方面，一种半导体器件包括：第一晶片，其具有形成于第一衬底上的至少一个石墨烯沟道、包围所述石墨烯沟道的第一氧化物层、以及接到所述石墨烯沟道并延伸穿过所述第一氧化物层的源极接触和漏极接触；以及第二晶片，其具有形成于第二衬底中的CMOS器件层、包围所述CMOS器件层的第二氧化物层、以及接到所述CMOS器件层并延伸穿过所述第二氧化物层的多个接触，所述晶片通过所述氧化物层之间的氧化物与氧化物接合而被接合在一起。接到所述CMOS器件层的所述多个接触中的一个或多个接触与所述源极接触和漏极接触相接触。接到所述CMOS器件层的所述多个接触中的一个或多个另外的接触为用于所述石墨烯沟道的栅极接触。

Description

基于石墨烯沟道的器件及其制造方法
技术领域
本发明涉及基于石墨烯（graphene）的器件，更具体而言涉及基于石墨烯沟道的器件及其制造技术。
背景技术
石墨烯为单层石墨。石墨烯具有非凡的电子特性。例如，石墨烯中的电子载流子呈现对高性能射频（rf）电路而言有吸引力的非常高的迁移率。利用涉及石墨烯的器件和复杂电路的一个主要挑战在于，石墨烯的生长条件与当前互补金属氧化物半导体（CMOS）技术的工艺限制不兼容。例如，从碳化硅（SiC）衬底外延生长的石墨烯层需要至少1200摄氏度（℃）的反应温度，该反应温度大大超出了CMOS工艺的约350℃到约400℃的温度上限。在较低温度下获得石墨烯片的一种方式是通过机械剥脱（mechanical exfoliation）体石墨并转移到合适的衬底而实现的。然而，在后续工艺期间，从任一方法获得的石墨烯可能通过氧化而被破坏，且石墨烯的特性也可能改变。
由于其高载流子迁移率，石墨烯在rf电路应用中是作为有源部件的有吸引力的材料。对rf电路而言，晶体管的性能主要决定于截止频率，即，晶体管的电流增益变成一致的频率。为了改善晶体管的截止频率，需要最小化与晶体管的互连和接触相关联的剩余电阻以及寄生电容。
一般而言，场效晶体管（FET）包含源极、漏极以及连接源极与漏极的沟道。通过电介质与沟道分隔的栅极调节通过沟道的电子流。典型地向源极、漏极和栅极提供金属接触（电极）。对于常规的基于石墨烯的FET，通常采用两种类型的栅极结构。在第一种类型中，栅极接触与源极金属接触/漏极金属接触重叠（overlap），以确保良好的栅极控制。在第二种类型中，栅极与源极金属接触/漏极金属接触负重叠（underlap），以避免栅极与源极/漏极接触之间的寄生电容。在第一种设计中，由于接触重叠，所以器件性能有显著的寄生电容。在第二种设计中，栅极与源极/漏极接触之间的非栅极化（ungated）区域造成剩余串联电阻。任一种设计都不能针对高性能操作同时解决寄生电容和剩余串联电阻的问题。
因此，需要一种有效地结合现有CMOS技术与石墨烯的新制造方案，以允许成功地利用石墨烯作为实际器件/或电路中的有源或无源元件，例如基于石墨烯的晶体管器件设计使得寄生电容和剩余串联电阻二者最小化。
发明内容
本发明提供基于石墨烯沟道的器件及其制造技术。在本发明的一个方面中，提供一种半导体器件。所述半导体器件包括：第一晶片，其具有形成于第一衬底上的至少一个石墨烯沟道、包围所述石墨烯沟道的第一氧化物层、以及接到所述石墨烯沟道并延伸穿过所述第一氧化物层的源极接触和漏极接触；以及第二晶片，其具有形成于第二衬底中的互补金属氧化物半导体（CMOS）器件层、包围所述CMOS器件层的第二氧化物层、以及接到所述CMOS器件层并延伸穿过所述第二氧化物层的多个接触，所述第一晶片和所述第二晶片通过所述第一氧化物层与所述第二氧化物层之间的氧化物与氧化物接合而被接合在一起。接到所述CMOS器件层的所述多个接触中的一个或多个接触与接到所述石墨烯沟道的所述源极接触和漏极接触相接触。接到所述CMOS器件层的所述多个接触中的一个或多个另外的接触为用于所述石墨烯沟道的栅极接触。
在本发明的另一方面中，提供一种制造半导体器件的方法。该方法包括以下步骤。形成第一晶片，所述第一晶片具有形成于第一衬底上的至少一个石墨烯沟道、包围所述石墨烯沟道的第一氧化物层、以及接到所述石墨烯沟道并延伸穿过所述第一氧化物层的源极接触和漏极接触。形成第二晶片，所述第二晶片具有形成于第二衬底中的CMOS器件层、包围所述CMOS器件层的第二氧化物层、以及接到所述CMOS器件层并延伸穿过所述第二氧化物层的多个接触。通过所述第一氧化物层与所述第二氧化物层之间的氧化物与氧化物接合将所述第一晶片和所述第二晶片接合在一起，使得接到所述CMOS器件层的所述多个接触中的一个或多个接触与接到所述石墨烯沟道的所述源极接触和漏极接触相接触，且接到所述CMOS器件层的所述多个接触中的一个或多个另外的接触为用于所述石墨烯沟道的栅极接触。
在本发明的又一方面中，提供一种晶体管器件。所述晶体管器件包括：衬底；形成于所述衬底上的源极接触和漏极接触；形成于所述衬底上的石墨烯沟道，其连接所述源极接触和漏极接触；以及位于所述石墨烯沟道上方的栅极接触，其通过电介质而与所述石墨烯沟道分隔，其中所述栅极接触处于与所述源极接触和漏极接触非重叠的位置，使得所述石墨烯沟道的位于所述栅极接触与所述源极接触和漏极接触之间的部分暴露，且其中所述石墨烯沟道的暴露部分被掺杂有n型或p型掺杂剂。
在本发明的再一方面中，提供一种制造晶体管器件的方法。所述方法包括以下步骤。提供衬底。在所述衬底上形成源极接触和漏极接触。在所述衬底上形成石墨烯沟道，所述石墨烯沟道连接所述源极接触和漏极接触。在所述石墨烯沟道上方形成栅极接触，所述栅极接触通过电介质而与所述石墨烯沟道分隔，其中所述栅极接触处于与所述源极接触和漏极接触非重叠的位置，使得所述石墨烯沟道的位于所述栅极接触与所述源极接触和漏极接触之间的部分暴露。用n型或p型掺杂剂掺杂所述石墨烯沟道的暴露部分。
将参考以下详细说明和附图获得对本发明以及本发明的其它特征和优点的更完整的了解。
附图说明
图1为截面图，示例出根据本发明实施例已在衬底上沉积或生长石墨烯层；
图2为三维（3D）图，示例出根据本发明实施例在衬底上的石墨烯层的自顶向下视图；
图3为3D图，示例出根据本发明实施例已在石墨烯/衬底上方形成掩模；
图4为3D图，示例出根据本发明实施例已在掩模周围蚀刻石墨烯层以构图并由此限定沟槽；
图5为截面图，示例出根据本发明实施例已在构图的石墨烯层和衬底之上沉积氧化物层；
图6为截面图，示例出根据本发明实施例已在氧化物层之上形成蚀刻掩模；
图7为截面图，示例出根据本发明实施例已将沟槽蚀刻到氧化物层中而暴露下面的（underlying）石墨烯部分；
图8为截面图，示例出根据本发明实施例已在氧化物层之上沉积金属而填充沟槽；
图9为截面图，示例出根据本发明实施例已由所沉积的金属形成源极区金属接触和漏极区金属接触；
图10为截面图，示例出根据本发明实施例使用晶片至晶片接合（wafer-to-wafer bonding）技术来集成图9的石墨烯晶片与互补金属氧化物半导体（CMOS）器件晶片；
图11为截面图，示例出根据本发明实施例已利用晶片接合工艺以面对面方式将石墨烯晶片与CMOS器件晶片接合在一起；
图12为截面图，示例出根据本发明实施例已从石墨烯晶片去除衬底；
图13为截面图，示例出根据本发明实施例已从CMOS器件晶片去除衬底；
图14为截面图，示例出根据本发明实施例已将另外的金属层加到图12的结构；
图15为截面图，示例出根据本发明实施例已将另外的金属层加到图13中示出的结构；
图16为截面图，提供了根据本发明实施例可如何将CMOS器件晶片部件配置为与石墨烯晶片集成的实例；
图17为截面图，示例出根据本发明实施例已在衬底上沉积或生长石墨烯层；
图18为3D图，示例出根据本发明实施例已在衬底上沉积或生长的石墨烯层的自顶向下视图；
图19为截面图，示例出根据本发明实施例在石墨烯层/衬底之上构图抗蚀剂掩模；
图20为3D图，示例出根据本发明实施例在石墨烯层/衬底之上构图抗蚀剂掩模的自顶向下视图；
图21为截面图，示例出根据本发明实施例已在构图的抗蚀剂掩模周围沉积源极接触金属/漏极接触金属；
图22为3D图，示例出根据本发明实施例已在构图的抗蚀剂掩模周围沉积源极接触金属/漏极接触金属的自顶向下视图；
图23为截面图，示例出根据本发明实施例在石墨烯层上构图掩模以限定有源沟道区域；
图24为3D图，示例出根据本发明实施例在石墨烯层上构图掩模的自顶向下视图；
图25为截面图，示例出根据本发明实施例已蚀刻掉石墨烯层的未受掩模保护的部分而由此限定石墨烯沟道；
图26为3D图，示例出根据本发明实施例已蚀刻掉石墨烯层的未受掩模保护的部分而由此限定石墨烯沟道的自顶向下视图；
图27为截面图，示例出根据本发明实施例已在石墨烯沟道、源极金属接触与漏极金属接触以及衬底之上毯覆式沉积（blanket deposit）栅极电介质；
图28为3D图，示例出根据本发明实施例已在石墨烯沟道、源极金属接触与漏极金属接触以及衬底之上毯覆式沉积栅极电介质的自顶向下视图；
图29为截面图，示例出根据本发明实施例在石墨烯沟道之上构图栅极金属接触并通过栅极电介质而使栅极金属接触与石墨烯沟道分隔；
图30为3D图，示例出根据本发明实施例在石墨烯沟道之上构图栅极金属接触并通过栅极电介质而使栅极金属接触与石墨烯沟道分隔的自顶向下视图；
图31为截面图，示例出根据本发明实施例已蚀刻掉栅极电介质的未被栅极金属接触覆盖的部分；
图32为3D图，示例出根据本发明实施例已蚀刻掉栅极电介质的未被栅极金属接触覆盖的部分的自顶向下视图；
图33为截面图，示例出根据本发明实施例已在衬底和石墨烯沟道的暴露部分、源极金属接触与漏极金属接触以及栅极金属接触之上毯覆式沉积掺杂剂；
图34为3D图，示例出根据本发明实施例已在衬底和石墨烯沟道的暴露部分、源极金属接触与漏极金属接触以及栅极金属接触之上毯覆式沉积掺杂剂的自顶向下视图；
图35为截面图，示例出根据本发明实施例已在衬底和石墨烯沟道的暴露部分、源极金属接触与漏极金属接触以及栅极金属接触之上形成保护帽盖层；以及
图36为3D图，示例出根据本发明实施例已在衬底和石墨烯沟道的暴露部分、源极金属接触与漏极金属接触以及栅极金属接触之上形成保护帽盖层的自顶向下视图。
具体实施方式
本文中提供基于石墨烯沟道的器件及其制造技术。本技术解决上述的与制造期间互补金属氧化物半导体（CMOS）/石墨烯处理温度不兼容相关的问题（参见例如下面描述的图1-16）以及完成的器件中的寄生电容和剩余电阻的问题（参见例如下面描述的图17-36）。
图1-16为示例出制造具有基于石墨烯的电路和CMOS电路二者的半导体器件的示例性方法。如下面详细描述的，本技术利用新颖的三维（3D）集成方法，其涉及分别地制造石墨烯和CMOS电路且然后使用晶片接合工艺集成石墨烯和CMOS电路。通过在工艺中分别地制造石墨烯与CMOS电路且然后稍后将两者集成，可避免与石墨烯形成温度超过CMOS制造工艺极限相关的问题。
图1为截面图，示例出已在衬底104上沉积或生长一个或多个石墨烯层102（例如，从单层到高达10层的石墨烯）。当沉积（例如使用机械剥脱）石墨烯层102时，衬底104可为绝缘晶片或具有绝缘覆盖层的晶片，例如覆盖有二氧化硅（SiO2）的硅（Si）晶片。当例如通过硅升华利用外延生长石墨烯层102时，衬底104可为碳化硅（SiC）晶片。本领域技术人员熟知在衬底上沉积石墨烯层的例如涉及剥除的技术和/或在衬底上生长石墨烯层的例如涉及SiC外延的技术，因此本文中不对其进行进一步的说明。图2为3D图，示例出在衬底104上（沉积或生长）的石墨烯层102的另一透视图，即，自顶向下视图。
石墨烯将配置为用作器件的一个或多个晶体管的有源沟道（本文中也称为“石墨烯沟道晶体管”或简称为“石墨烯晶体管”）。由此，该方法的下一步骤为用沟道布局（layout）来构图石墨烯层。图3为3D图，示例出已在石墨烯/衬底之上形成掩模302。该掩模将被用于蚀刻掉石墨烯层的不想要的区域。根据示例性实施例，掩模302由聚甲基丙烯酸甲酯（PMMA）制成。形成例如PMMA蚀刻掩模的技术为本领域技术人员所熟知，本文中不进一步说明。接着，使用蚀刻（在掩模302的周围）来构图石墨烯，由此限定沟道。图4为3D图，示例出构图的石墨烯层102。根据示例性实施例，通过氧等离子体蚀刻石墨烯。如图4所示，在蚀刻后，去除掩模302。对于由PMMA形成的示例性掩模，可在诸如丙酮的溶剂中去除掩模。
然后将氧化物层沉积为包围构图的石墨烯层。即，图5为截面图，示例出已在构图的石墨烯层102/衬底104之上沉积氧化物层502。根据示例性实施例，利用原子层沉积（ALD）和/或低温化学气相沉积（CVD），在构图的石墨烯/衬底之上沉积氧化物层502。此氧化物将用于两个目的。第一，其将用作石墨烯晶体管中的沟道的栅极电介质，参见下面。第二，稍后该氧化物层将用于在后续处理期间保护石墨烯不受破坏。此外，该氧化物层稍后将在晶片接合步骤期间的工艺中用于与相应的CMOS器件晶片形成氧化物对氧化物的接合。可能需要对石墨烯表面的官能化（functionalization）处理以产生均匀的氧化物覆盖。例如，可以在ALD氧化物沉积之前使石墨烯表面与二氧化氮（NO2）反应，来官能化石墨烯表面。作为另一实例，可以在ALD工艺前在石墨烯表面上沉积薄铝（Al）层（例如约1纳米（nm）到约2nm厚），并使其自然氧化。
然后在氧化物层上方形成掩模，该掩模用于限定石墨烯沟道的源极接触与漏极接触。即，图6为示例出已在氧化物层502上方形成蚀刻掩模602的截面图。该掩模可为电子束（e束）抗蚀剂掩模材料（例如PMMA）或金属硬掩模。形成抗蚀剂掩模或金属硬掩模的技术为本领域技术人员所熟知，因此本文中不进行进一步说明。
然后使用蚀刻暴露出石墨烯层的用于金属接触形成的区域。即，图7为截面图，示例出沟槽702已被蚀刻到氧化物层502中，暴露出下方的部分石墨烯层102。根据示例性实施例，使用湿法蚀刻来形成沟槽702。然后，去除在蚀刻期间用作掩模的掩模602。对于由PMMA形成的示例性掩模，可在诸如丙酮的溶剂中去除掩模。
随后，在氧化物层502上沉积金属以填充沟槽702。参见例如图8。根据图8中示例性示出的示例性实施例，该金属由两层构成，即第一金属层802与第二金属层804。第一金属层（下金属层）由能与石墨烯良好接触的金属（例如钯（Pd）和钛（Ti））构成，而第二金属层（上金属层）由允许在后续的晶片接合步骤（见下面）中粘附的铜（Cu）构成。因此，如图8所示，该金属与石墨烯层的先前暴露的部分接触。仅举例而言，可利用电子束蒸发和溅镀将第一金属层沉积到约1nm至约100nm的厚度，且可利用电化学将第二金属层沉积到约5nm至约100微米（μm）的厚度。
图9为截面图，示例出已由所沉积的金属形成源极区金属接触与漏极区金属接触。如图9所示，利用例如化学机械抛光（CMP）对金属化的衬底进行抛光，以去除多余的金属并将氧化物层减薄到所需厚度，例如约5nm至约1μm。如上面所强调的，石墨烯被构图以限定电路的沟道。因此，形成接到石墨烯沟道（如上所述限定的）的源极接触与漏极接触。为了简单清楚地说明，图9所示的结构，即，在衬底（晶片）上形成有石墨烯沟道以及金属源极与漏极接触的结构在以下说明中一般称为“石墨烯晶片”。如上面所强调的，石墨烯晶片包括基于石墨烯的电路，例如，一个或多个石墨烯晶体管。
图10为截面图，示例出用于使石墨烯晶片与CMOS器件晶片1002集成的晶片至晶片接合方案。如图10所示，CMOS器件晶片1002被倒装（flip），以允许与石墨烯晶片面对面接合。应注意，替代地，可以使石墨烯晶片倒装，以允许与CMOS器件晶片面对面接合（未示出）。
根据示例性实施例，CMOS器件晶片1002包括在衬底1006中形成的布线和其它CMOS结构和/或器件（在此也合称为“CMOS器件层”），其由框1004示意性表示。在一个实例中，CMOS器件层可包括CMOS晶体管或/和用于数字信号处理和/或数字-模拟信号转换和/或模拟-数字信号转换的电路。在此实例中，数字信号在CMOS器件层中被处理，而模拟射频（rf）信号由石墨烯晶片中的石墨烯晶体管处理。
根据示例性实施例，衬底1006可为体硅或绝缘体上硅（SOI）晶片。SOI晶片通常由通过掩埋氧化物（BOX）而与衬底分隔的硅（SOI）层构成。对于本领域技术人员而言显而易见的是，当使用SOI晶片时，可在SOI层中形成CMOS布线、结构和/或器件。可能的CMOS布线、结构和/或器件可包括但不限于金属线、过孔、存储器和/或逻辑晶体管，例如场效应晶体管（FET）。在体硅或SOI晶片上的CMOS布线、结构和/或器件及其制造技术对于本领域技术人员而言是显而易见的。然而，一般而言，晶体管包含源极、漏极以及连接源极与漏极的沟道。通过电介质（栅极电介质）与沟道分隔的栅极调节通过沟道的电子流。在本教导中，在CMOS器件晶片上设置接到石墨烯器件的栅极的金属接触。这样，氧化物层（即，已存在于石墨烯晶片上的氧化物层502）可有效地用作栅极接触与石墨烯沟道之间的栅极电介质，如上面所强调的。示例出CMOS器件晶片的部件如何可被配置为与石墨烯晶片的晶体管集成的实例被示于下述图16中。
如图10所示，源极金属接触S、漏极金属接触D以及栅极金属接触G分别与CMOS器件层接触（即，这些接触连接到CMOS器件层中的各CMOS布线、结构和/或器件）。在下述图16中提供了可如何将源极接触、漏极接触以及栅极接触连接到CMOS器件层中的这些部件的一个实例。在CMOS器件晶片中，可以以与上面关于石墨烯晶片中的源极金属接触和漏极金属接触描述的相同的方式，在包围CMOS器件层的氧化物层（例如氧化物层1008）中形成接到石墨烯晶片中的各种器件的源极金属接触、漏极金属接触以及栅极金属接触。然而，在该例子中，不需要Pd/Ti层，因为其目的是为了要提升对石墨烯片的粘着性（参见上面）。
图11为截面图，示例出已利用晶片接合工艺以面对面方式将石墨烯晶片与CMOS器件晶片接合在一起。在图11所示的示例性实施例中，通过石墨烯晶片的氧化物层502与CMOS器件晶片的氧化物层1008之间的氧化物对氧化物接合以及通过两个晶片的对应源极与漏极金属接触之间的铜对铜接合，将晶片接合在一起。典型地，接合温度低于400摄氏度（℃）。因此，在该工艺期间不会损坏器件。
3D集成已成为填补石墨烯电子的封装与集成电路（IC）技术空白的非常有前景的候选者。层叠CMOS现有技术水平的器件层的能力已得到证实。3D集成技术甚至在没有按比例缩放的情况下也可提供提高系统性能的新途径保证。在石墨烯中超高迁移率载流子情况下，还预期在确定整体电路性能时，互连的寄生电阻与电容将变为更加重要。在这方面，3D集成为基于石墨烯的电路提供了极大的优势。该保证归因于3D集成的一些特性特征，包括：（a）减小的总布线长度以及由此缩短的互连延迟时间；（b）显著增加的芯片间互连数目；以及（c）允许集成不同的材料、工艺技术和功能的能力。在这些优势中，来自3D的（c）项提供了解决上述热预算问题的良好途径。
因此，本发明的制造石墨烯电路的技术的优点包括：1）石墨烯可以通过各种不同方法来制备，这些方法包括上述两种方法；2）可在标准洁净室设施中预先制造复杂的电路而没有来自碳材料的潜在污染；3）晶片接合工艺中的对准确保了石墨烯沟道总是被加入在电路的所需位置处；4）由于石墨烯沟道是在另一衬底上单独地制造，因此仍可保持现有CMOS器件的要求，例如温度、湿法蚀刻环境、处理时的气体氛围等；以及5）可显著缩短在石墨烯电路情况下由互连所主宰的电路延迟时间。
现在可执行对接合的晶片的进一步处理。例如，可从石墨烯晶片去除衬底（如图12所示，已去除衬底1004的大部分而仅留下其小部分），或从CMOS器件晶片去除衬底（如图13所示，已去除衬底1006的大部分而仅留下其小部分）。由于现在在接合后存在来自两个晶片的两个衬底，选择去除哪个衬底取决于电路设计（即，允许制造另外的结构层，参见下面）。可选择来自硅晶片的硅的停止厚度（stopping thickness），而对SOI晶片而言掩埋氧化物层为停止层。根据示例性实施例，利用CMP或其它类似的抛光和/或研磨工艺来去除所希望的衬底。
如上面所强调的，去除衬底以允许在接合的衬底上制造另外的器件和/或金属层。在图14和15中示出了这些另外的层的实例。即，图14为截面图，示例出另外的金属层1402已被加到图12所示的结构（其中已从石墨烯晶片去除衬底）。根据示例性实施例，金属层1402是以与上面描述的相同的方式通过沉积氧化物层1404且然后在氧化物层1404中形成金属（例如铜）接触1406而形成的。在图14所示的示例性配置中，接触1406不与石墨烯沟道接触。
图15为截面图，示例出另外的金属层1502已被加到图13所示的结构（其中已从CMOS器件晶片去除衬底）。根据示例性实施例，金属层1502是以与上面描述的相同的方式通过沉积氧化物层1504且然后在氧化物层1504中形成金属（例如铜）接触1506而形成的。
图16为截面图，提供了可如何配置CMOS器件晶片1002的部件以与石墨烯晶片的晶体管集成的一个实例。图16所示的特定设计是本领域技术人员可预想的CMOS器件晶片1002的许多可能配置中的一种配置，仅仅旨在示例可如何实现晶片之间的连接。如图16所示，CMOS器件晶片1002可包含SOI层1602，在SOI层1602中形成分别构成CMOS晶体管（例如，金属氧化物半导体场效应晶体管（MOSFET））的源极区与漏极区的掺杂的硅区域1604和1606。向CMOS晶体管分别提供源极金属接触S’、漏极金属接触D’以及栅极金属接触G’。这些接触形成在绝缘体层1608中，且与氧化物层1008中的源极接触、漏极接触和栅极接触连接。参见例如使用金属线1610来形成该连接的情况。在绝缘体层中形成接触且然后在周围的氧化物层中形成其它金属接触的技术对于本领域普通技术人员而言是显而易见的，因此在此不再进一步描述。CMOS器件晶片与石墨烯晶片的配对可如例如上述图10及11所示地完成。如上所述，源极金属接触S’、漏极金属接触D’以及栅极金属接触G’分别用于完成石墨烯晶片中的一个或多个石墨烯晶体管。因此，在一些实施例中，石墨烯晶片会含有一个或多个晶体管，而CMOS器件晶片也会含有一个或多个晶体管（本文中也称为“CMOS”晶体管）。可使用与图16所示例的相同的技术使石墨烯晶体管与CMOS晶体管彼此邻接（interface）。
如上面所强调的，寄生电容和剩余电阻是影响常规的基于石墨烯的晶体管设计的重要因素。有利地，本发明技术提供使寄生电容和剩余电阻二者都最小化的途径，这是设计不能实现的。
图17-36为示例出制造用于射频应用的基于石墨烯的晶体管器件的示例性方法的图。如下面所详述的，本发明方法采用自对准的掺杂/栅极化（gating），以使寄生电容与剩余串联电阻二者都最小化。
如上所述，制造过程始于在衬底上形成（即，沉积或生长）石墨烯层。即，图17为截面图，示例出已在衬底1704上沉积或生长一个或多个石墨烯层1702（例如，从单层到高达10层的石墨烯）。石墨烯层1702可通过机械剥脱而沉积在衬底1704上或外延生长在SiC上（例如，通过硅升华外延）。如上面所强调的，这两种石墨烯形成工艺都为本领域技术人员所熟知，因此在此不再详述。当沉积石墨烯层1702时，衬底1704可为绝缘晶片或具有绝缘覆盖层的晶片，例如覆盖有SiO2的Si晶片。当生长石墨烯层1702时，衬底1704可为SiC晶片。图18为3D图，示例出已在衬底1704上沉积或生长石墨烯层1702的另一透视图，即，自顶向下视图。
接着，在石墨烯层/衬底之上对抗蚀剂掩模进行构图，以限定源极接触区域与漏极接触区域。图19为截面图，示例出在石墨烯层1702/衬底1704之上构图的抗蚀剂掩模1902。抗蚀剂掩模可为软掩模，例如光学或e束光刻抗蚀剂（PMMA、氢倍半硅氧烷（HSQ）、或S1818TM，其从Rohm andHaas Electronic Materials LLC,Marlborough,MA可得），或可为硬掩模，例如通过兼容沉积方法沉积的氧化物、氮化物或金属。形成软掩模或硬掩模的技术为本领域技术人员所熟知，因此在此不再详述。图20为3D图，示例出在石墨烯层1702/衬底1704之上构图的抗蚀剂掩模1902的另一透视图，即，自顶向下视图。从图20所示的透视图可知，将形成源极接触区域和漏极接触区域（如下面进一步详述的）。
然后，沉积接触金属。图21为截面图，示例出已在构图的抗蚀剂掩模1902周围沉积的源极接触金属/漏极接触金属2102。如图21所示，一旦沉积了接触金属，就去除抗蚀剂掩模1902。选择性金属接触形成遵循本领域技术人员所熟知的标准剥除工艺。首先通过e束蒸发、热蒸发、或溅射而在抗蚀剂掩模1902/衬底1704上毯覆式沉积金属。可以使用诸如Pd、Ti、金（Au）、Al、钨（W）的金属作为接触金属。在毯覆式金属沉积后，在适当溶剂中去除抗蚀剂掩模1902，且通过这样做，同时去除在抗蚀剂掩模上的金属。根据示例性实施例，抗蚀剂掩模1902由PMMA形成，且可利用丙酮作为溶剂而在剥除工艺中被去除。图22为3D图，示例出已沉积在构图的抗蚀剂掩模1902周围的源极接触金属/漏极接触金属2102的另一透视图，即，自顶向下视图。
然后在石墨烯层上对保护性硬掩模或软掩模进行构图，以限定器件的有源沟道区域。即，图23为截面图，示例出在石墨烯层1702上构图的掩模2302。同样地，形成软或硬掩模的技术为本领域技术人员所熟知，因此在此不再详述。图24为3D图，示例出在石墨烯层1702上构图的掩模2302的另一透视图，即，自顶向下视图。
然后去除未受保护的石墨烯。即，图25为截面图，示例出已通过干法蚀刻技术（例如，O2等离子体）蚀刻掉石墨烯层1702的未受掩模2302保护的部分，由此限定器件的沟道2502。如图25所示，掩模2302也已在适当的溶剂中被去除。根据示例性实施例，蚀刻掩模2302由PMMA形成，且可在丙酮中被去除。图26为3D图，示例出已蚀刻掉石墨烯片1702的未受掩模2302保护的部分的另一透视图，即，自顶向下视图。
在去除保护掩模而暴露出石墨烯沟道之后，在器件表面上沉积栅极电介质。图27为截面图，示例出已在器件上方，即，在石墨烯沟道2502、源极金属接触与漏极金属接触2102以及衬底1704上方毯覆式沉积栅极电介质2702（例如，氧化物）（参见图28）。根据示例性实施例，使用ALD、CVD、等离子体溅射或e束沉积而沉积栅极电介质2702。根据所用的沉积技术以及所沉积的电介质的厚度，石墨烯沟道的表面可能需要官能化，以确保适当的电介质覆盖。例如，在ALD氧化物沉积之前，可通过使石墨烯与NO2反应而对石墨烯进行官能化。作为另一例子，在ALD工艺之前，在石墨烯表面上沉积约1nm至约2nm厚的薄Al层并使其自然氧化。图28为3D图，示例出已在石墨烯沟道2502、源极金属接触与漏极金属接触2102以及衬底1704之上毯覆式沉积栅极电介质2702的另一透视图，即，自顶向下视图。
在电介质沉积之后，在石墨烯沟道的顶上对栅极金属接触进行构图。即，图29为截面图，示例出在石墨烯沟道2502之上构图的且通过栅极电介质2702而与石墨烯沟道2502分隔的栅极金属接触2902。在对栅极金属接触2902构图时，使用标准光刻工艺。从图29和图30（在下面说明）可注意到，栅极金属接触2902被定位为不会延伸在源极金属接触与漏极金属接触2102之上（不与源极金属接触和漏极金属接触2102重叠）。该配置在本文中也称为负重叠栅极配置（underlapping gate configuration），即，栅极金属接触与源极金属接触和漏极金属接触负重叠。图30为3D图，示例出在石墨烯沟道2502之上构图的且通过栅极电介质2702而与石墨烯沟道2502分隔的栅极金属接触2902的另一透视图，即，自顶向下视图。
然后蚀刻掉电介质的未被栅极金属接触覆盖的部分。即，图31为截面图，示例出已蚀刻掉栅极电介质2702的未被栅极金属接触2902覆盖的部分。这使得石墨烯沟道的位于栅极金属接触2902两侧的部分3102暴露。根据示例性实施例，电介质由氧化铝（Al2O3）形成，且利用磷酸而被蚀刻掉（应去除所有的电介质以暴露出石墨烯沟道的位于栅极金属接触2902两侧的部分3102）。图32为3D图，示例出已蚀刻掉栅极电介质2702的未被栅极金属接触2902覆盖的部分的另一透视图，即，自顶向下视图。
然后执行化学掺杂，以掺杂石墨烯沟道的暴露部分（即部分3102）。图33为截面图，示例出已对器件表面施加掺杂剂3302，即，已在源极金属接触与漏极金属接触2102、栅极金属接触2902、石墨烯沟道的暴露部分3102以及衬底1704之上毯覆式沉积掺杂剂3302（参见下述图34）。掺杂剂3302为n型（例如聚乙烯亚胺（PEI））或p型（例如重氮盐）分子掺杂剂。石墨烯沟道的暴露到掺杂剂的部分（即，部分3102）由栅极电极的位置限定，产生自对准的掺杂/栅极化结构。如图33所示，在该工艺中，栅极金属接触被用作去除电介质的蚀刻掩模以及限定掺杂区的掺杂掩模。图34为3D图，示例出已在源极金属接触与漏极金属接触2102、栅极金属接触2902、石墨烯沟道的暴露部分3102以及衬底1704之上毯覆式沉积掺杂剂3302的另一透视图，即，自顶向下视图。
利用本技术，通过类似于负重叠结构的自对准栅极而使寄生电容最小化，并且通过在未栅极化的区域中的化学掺杂而使剩余串联电阻最小化。对p型（或n型）器件而言，使用p型（或n型）掺杂剂，以确保主要传输支路的载流子迁移率不因掺杂剂而劣化。利用本设计，预期会改善石墨烯rf器件的性能。具体而言，本技术采用新的化学掺杂方案来控制器件特性，而没有引入影响器件性能的另外的电容，如下所述。控制石墨烯特性的其中一个主要挑战在于，不能用稳定且不劣化石墨烯载流子迁移率的掺杂剂来改变石墨烯的化学势。例如，当暴露到钾时，石墨烯呈现n型行为，但该掺杂方法也引入抑制电子传导的散射中心，由此破坏由石墨烯提供的所需电子特性。再者，钾为化学不稳定的，且可容易地在材料中扩散和迁移，造成不利的非均质。解决此问题的一个可能方案为使用静电掺杂，其中费米能级由电栅极化控制。然而，该电掺杂方法不容易按比例缩放（scalable），且可能引入寄生电容。因此，化学掺杂为优选的，但是仍需要适当的掺杂剂。已知两种分子掺杂剂（聚乙烯亚胺（PEI）和重氮盐）在石墨烯中分别提供n型掺杂和p型掺杂。这两种分子掺杂剂也选择性地保持石墨烯中的电子或空穴载流子迁移率，且在此被用于制造高性能石墨烯rf器件。
接着，作为可选的步骤，可将器件封装在保护帽盖层中。即，图35为截面图，示例出已在器件之上，即，在源极金属接触与漏极金属接触2102、栅极金属接触2902、石墨烯沟道的暴露部分3102以及衬底1704之上形成保护帽盖层3502。根据示例性实施例，保护帽盖层由氧化物或氮化物材料形成，且利用e束蒸发、ALD或CVD来沉积。保护帽盖层3502的目的在于使石墨烯沟道与会影响其电子特性的环境隔离。图36为3D图，示例出已在源极金属接触与漏极金属接触2102、栅极金属接触2902、石墨烯沟道的暴露部分3102以及衬底1704之上形成保护帽盖层3502的另一透视图，即，自顶向下视图。
由此，利用本发明的器件设计，寄生的电阻和电容被同时最小化，允许器件性能的整体增强。该制造石墨烯rf器件的新方法的优点在于：1）通过自对准的栅极化/掺杂使寄生的电阻和电容最小化，这增强了器件的高频功能性；2）使用自对准技术来构图掺杂轮廓，这降低了制造工艺的复杂性并确保对器件变化的最佳控制；以及3）通过使用不会劣化所需载流子支路的掺杂剂，保持了石墨烯的高载流子迁移率。根据所使用的掺杂剂，保持了电子或空穴迁移率。例如，PEI保持电子迁移率，而重氮盐保持空穴迁移率。
尽管本文已描述了本发明的示例性实施例，但应理解，本发明并不限于这些精确的实施例，并且只要不脱离本发明的范围，本领域技术人员可做出各种其它改变和修改。

Claims (22)

1.一种半导体器件，包括：
第一晶片，其具有形成于第一衬底上的至少一个石墨烯沟道、包围所述石墨烯沟道的第一氧化物层、以及接到所述石墨烯沟道并延伸穿过所述第一氧化物层的源极接触和漏极接触；以及
第二晶片，其具有形成于第二衬底中的互补金属氧化物半导体(CMOS)器件层、包围所述CMOS器件层的第二氧化物层、以及接到所述CMOS器件层并延伸穿过所述第二氧化物层的多个接触，所述第一晶片和所述第二晶片通过所述第一氧化物层与所述第二氧化物层之间的氧化物与氧化物接合而被接合在一起，
其中接到所述CMOS器件层的所述多个接触中的一个或多个接触与接到所述石墨烯沟道的所述源极接触和漏极接触相接触，且其中接到所述CMOS器件层的所述多个接触中的一个或多个另外的接触为用于所述石墨烯沟道的栅极接触。
2.根据权利要求1的器件，其中所述CMOS器件层包括一个或多个CMOS布线、结构和器件。
3.根据权利要求1的器件，其中所述第一衬底包括绝缘晶片、具有绝缘覆盖层的晶片或碳化硅晶片。
4.根据权利要求1的器件，其中所述第二衬底包括绝缘体上硅晶片或体硅晶片。
5.根据权利要求1的器件，其中接到所述石墨烯沟道的所述源极接触和漏极接触以及接到所述CMOS器件层的所述多个接触各自包含铜，且其中所述第一晶片和所述第二晶片进一步通过接到所述石墨烯沟道的所述源极接触和漏极接触与接到所述CMOS器件层的所述多个接触中的一个或多个接触之间的铜与铜接合而被接合在一起。
6.根据权利要求1的器件，其中所述第一晶片和所述第二晶片以面对面取向而被接合在一起。
7.一种制造半导体器件的方法，包括以下步骤：
形成第一晶片，所述第一晶片具有形成于第一衬底上的至少一个石墨烯沟道、包围所述石墨烯沟道的第一氧化物层、以及接到所述石墨烯沟道并延伸穿过所述第一氧化物层的源极接触和漏极接触；
形成第二晶片，所述第二晶片具有形成于第二衬底中的CMOS器件层、包围所述CMOS器件层的第二氧化物层、以及接到所述CMOS器件层并延伸穿过所述第二氧化物层的多个接触；以及
通过所述第一氧化物层与所述第二氧化物层之间的氧化物与氧化物接合将所述第一晶片和所述第二晶片接合在一起，使得接到所述CMOS器件层的所述多个接触中的一个或多个接触与接到所述石墨烯沟道的所述源极接触和漏极接触相接触，且接到所述CMOS器件层的所述多个接触中的一个或多个另外的接触为用于所述石墨烯沟道的栅极接触。
8.根据权利要求7的方法，还包括以下步骤：
使所述第一晶片或所述第二晶片中的一者倒装，以允许与所述第一晶片或所述第二晶片中的另一者面对面接合。
9.一种晶体管器件，包括：
衬底；
形成于所述衬底上的源极接触和漏极接触；
形成于所述衬底上的石墨烯沟道，其连接所述源极接触和漏极接触；以及
位于所述石墨烯沟道上方的栅极接触，其通过电介质而与所述石墨烯沟道分隔，其中所述栅极接触处于与所述源极接触和漏极接触非重叠的位置，使得所述石墨烯沟道的位于所述栅极接触与所述源极接触和漏极接触之间的部分暴露，且其中所述石墨烯沟道的暴露部分被掺杂有n型或p型掺杂剂，其中所述栅极接触被用作掺杂掩模，从而产生自对准的掺杂/栅极化结构。
10.根据权利要求9的器件，还包括：
帽盖层，其位于所述源极接触和漏极接触、所述栅极接触、以及所述石墨烯沟道的所述暴露部分上方。
11.根据权利要求9的器件，其中所述衬底包括绝缘晶片、具有绝缘覆盖层的晶片或碳化硅晶片。
12.根据权利要求9的器件，其中所述石墨烯沟道的所述暴露部分被掺杂有包含聚乙烯亚胺的n型掺杂剂。
13.根据权利要求9的器件，其中所述石墨烯沟道的所述暴露部分被掺杂有包含重氮盐的p型掺杂剂。
14.根据权利要求10的器件，其中所述帽盖层包含氧化物或氮化物材料。
15.一种制造晶体管器件的方法，包括：
提供衬底；
在所述衬底上形成源极接触和漏极接触；
在所述衬底上形成石墨烯沟道，所述石墨烯沟道连接所述源极接触和漏极接触；
在所述石墨烯沟道上方形成栅极接触，所述栅极接触通过电介质而与所述石墨烯沟道分隔，其中所述栅极接触处于与所述源极接触和漏极接触非重叠的位置，使得所述石墨烯沟道的位于所述栅极接触与所述源极接触和漏极接触之间的部分暴露；以及
用n型或p型掺杂剂掺杂所述石墨烯沟道的暴露部分，其中所述栅极接触被用作掺杂掩模，从而产生自对准的掺杂/栅极化结构。
16.根据权利要求15的方法，还包括以下步骤：
在所述衬底上形成一个或多个石墨烯层。
17.根据权利要求16的方法，其中所述衬底包括具有绝缘覆盖层的晶片，且其中所述形成石墨烯层的步骤进一步包括以下步骤：
利用剥脱法在所述绝缘覆盖层的表面上沉积所述石墨烯层。
18.根据权利要求16的方法，其中所述衬底包括碳化硅晶片，且其中所述形成石墨烯层的步骤进一步包括以下步骤：
通过硅升华利用外延而在所述碳化硅晶片上生长所述石墨烯层。
19.根据权利要求16的方法，其中所述在所述衬底上形成源极接触和漏极接触的步骤进一步包括以下步骤：
对位于所述石墨烯层和所述衬底上方的抗蚀剂掩模进行构图，以限定源极接触区域和漏极接触区域；
在所述抗蚀剂掩模周围且在所述源极接触和漏极接触区域中沉积金属，以形成所述源极接触和漏极接触；以及
去除所述抗蚀剂掩模。
20.根据权利要求16的方法，其中所述在所述衬底上形成石墨烯沟道的步骤进一步包括以下步骤：
对位于所述多个石墨烯层上的掩模进行构图，以限定有源沟道区域；
去除所述石墨烯层的未受所述掩模保护的部分；以及
去除所述掩模。
21.根据权利要求15的方法，还包括以下步骤：
在所述石墨烯沟道、所述源极接触和漏极接触以及所述衬底上方沉积所述电介质。
22.根据权利要求15的方法，还包括以下步骤：
在所述源极接触和漏极接触、所述栅极接触、所述石墨烯沟道的所述暴露部分以及所述衬底上方形成帽盖层。
CN201180024337.0A 2010-05-20 2011-04-26 基于石墨烯沟道的器件及其制造方法 Active CN102893387B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/783,676 2010-05-20
US12/783,676 US8445320B2 (en) 2010-05-20 2010-05-20 Graphene channel-based devices and methods for fabrication thereof
PCT/EP2011/056581 WO2011144423A1 (en) 2010-05-20 2011-04-26 Graphene channel-based devices and methods for fabrication thereof

Publications (2)

Publication Number Publication Date
CN102893387A CN102893387A (zh) 2013-01-23
CN102893387B true CN102893387B (zh) 2015-02-25

Family

ID=44243209

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180024337.0A Active CN102893387B (zh) 2010-05-20 2011-04-26 基于石墨烯沟道的器件及其制造方法

Country Status (9)

Country Link
US (4) US8445320B2 (zh)
JP (1) JP5719430B2 (zh)
KR (1) KR101419631B1 (zh)
CN (1) CN102893387B (zh)
DE (1) DE112011100907B4 (zh)
GB (2) GB2493238B (zh)
SG (1) SG184823A1 (zh)
TW (1) TWI497644B (zh)
WO (1) WO2011144423A1 (zh)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8796668B2 (en) * 2009-11-09 2014-08-05 International Business Machines Corporation Metal-free integrated circuits comprising graphene and carbon nanotubes
KR20110098441A (ko) * 2010-02-26 2011-09-01 삼성전자주식회사 그라핀 전자 소자 및 제조방법
EP2655246B1 (en) * 2010-12-23 2014-10-22 Clean Energy Labs, LLC Methods for making graphene windows
US8748871B2 (en) 2011-01-19 2014-06-10 International Business Machines Corporation Graphene devices and semiconductor field effect transistors in 3D hybrid integrated circuits
US8409957B2 (en) 2011-01-19 2013-04-02 International Business Machines Corporation Graphene devices and silicon field effect transistors in 3D hybrid integrated circuits
US8716863B2 (en) * 2011-07-13 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for high performance interconnect
US8772910B2 (en) 2011-11-29 2014-07-08 International Business Machines Corporation Doping carbon nanotubes and graphene for improving electronic mobility
US8895417B2 (en) * 2011-11-29 2014-11-25 International Business Machines Corporation Reducing contact resistance for field-effect transistor devices
US8633055B2 (en) 2011-12-13 2014-01-21 International Business Machines Corporation Graphene field effect transistor
KR101946005B1 (ko) * 2012-01-26 2019-02-08 삼성전자주식회사 그래핀 소자 및 그 제조방법
US8680511B2 (en) 2012-02-09 2014-03-25 International Business Machines Corporation Bilayer gate dielectric with low equivalent oxide thickness for graphene devices
US9368581B2 (en) 2012-02-20 2016-06-14 Micron Technology, Inc. Integrated circuitry components, switches, and memory cells
US8809153B2 (en) 2012-05-10 2014-08-19 International Business Machines Corporation Graphene transistors with self-aligned gates
US20140113416A1 (en) * 2012-06-28 2014-04-24 International Business Machines Corporation Dielectric for carbon-based nano-devices
US8816787B2 (en) 2012-07-18 2014-08-26 International Business Machines Corporation High frequency oscillator circuit and method to operate same
US9276524B2 (en) * 2012-07-18 2016-03-01 International Business Machines Corporation High frequency oscillator circuit
KR101919426B1 (ko) * 2013-01-08 2018-11-19 삼성전자주식회사 그래핀 전자 소자 및 그 제조 방법
US9490201B2 (en) * 2013-03-13 2016-11-08 Intel Corporation Methods of forming under device interconnect structures
KR20140118285A (ko) * 2013-03-28 2014-10-08 인텔렉추얼디스커버리 주식회사 환원된 그래핀 산화물을 이용한 변형 감지 소자 및 그 제조 방법
US8889475B1 (en) 2013-05-30 2014-11-18 International Business Machines Corporation Self-aligned bottom-gated graphene devices
KR101424603B1 (ko) 2013-09-10 2014-08-04 한국과학기술연구원 박막 트랜지스터의 제조 방법
KR102116978B1 (ko) * 2013-10-07 2020-05-29 삼성전자 주식회사 그래핀 소자 및 그 제조 방법
CN103840003B (zh) * 2014-02-21 2016-06-29 西安电子科技大学 以三氧化二铝为栅介质的双栅石墨烯晶体管及其制备方法
KR20150121590A (ko) * 2014-04-21 2015-10-29 이윤택 그래핀의 제조방법 및 그래핀 원자층이 식각되는 그래핀 제조방법 및 웨이퍼결합방법을 구비하는 그래핀 굽힘 트랜지스터, 및 그래핀 굽힘 트랜지스터
US9859394B2 (en) 2014-12-18 2018-01-02 Agilome, Inc. Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids
US10020300B2 (en) 2014-12-18 2018-07-10 Agilome, Inc. Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids
US9618474B2 (en) 2014-12-18 2017-04-11 Edico Genome, Inc. Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids
US9857328B2 (en) 2014-12-18 2018-01-02 Agilome, Inc. Chemically-sensitive field effect transistors, systems and methods for manufacturing and using the same
US10006910B2 (en) 2014-12-18 2018-06-26 Agilome, Inc. Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same
WO2016100049A1 (en) 2014-12-18 2016-06-23 Edico Genome Corporation Chemically-sensitive field effect transistor
CN104538453B (zh) * 2014-12-29 2018-10-19 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法和显示器件
EP3054486B1 (en) 2015-02-04 2021-07-07 Nokia Technologies Oy A field-effect apparatus, associated apparatus and methods
EP3076436A1 (en) * 2015-03-30 2016-10-05 Nokia Technologies OY A method and apparatus for providing a transistor
KR102409390B1 (ko) * 2015-10-07 2022-06-15 삼성전자주식회사 그래핀 소자 및 그 동작 방법
US9882008B2 (en) 2015-11-05 2018-01-30 Texas Instruments Incorporated Graphene FET with graphitic interface layer at contacts
US9881896B2 (en) 2015-12-17 2018-01-30 International Business Machines Corporation Advanced chip to wafer stacking
EP3206235B1 (en) * 2016-02-12 2021-04-28 Nokia Technologies Oy Method of forming an apparatus comprising a two dimensional material
EP3206232A1 (en) * 2016-02-12 2017-08-16 Centre National de la Recherche Scientifique - CNRS - Method for obtaining a graphene-based fet, in particular a memory fet, equipped with an embedded dielectric element made by fluorination
JP6714390B2 (ja) * 2016-02-26 2020-06-24 住友電気工業株式会社 電子装置およびその製造方法
WO2017201081A1 (en) 2016-05-16 2017-11-23 Agilome, Inc. Graphene fet devices, systems, and methods of using the same for sequencing nucleic acids
US10032750B2 (en) * 2016-06-29 2018-07-24 International Business Machines Corporation Integrated DC-DC power converters through face-to-face bonding
JP6675945B2 (ja) * 2016-07-19 2020-04-08 住友電気工業株式会社 グラフェントランジスタおよびその製造方法
US10170702B2 (en) * 2017-01-12 2019-01-01 International Business Machines Corporation Intermetallic contact for carbon nanotube FETs
US10121743B2 (en) * 2017-03-29 2018-11-06 Qualcomm Incorporated Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)
JP7484674B2 (ja) 2020-11-18 2024-05-16 住友電気工業株式会社 トランジスタ
CN116569319A (zh) * 2020-12-10 2023-08-08 加利福尼亚大学董事会 Cmos兼容性石墨烯结构、互连体和制造方法
EP4391028A1 (en) 2022-12-23 2024-06-26 Graphenea Semiconductor S.L.U. Graphene device and method of fabricating a graphene device
GB2627306A (en) 2023-02-20 2024-08-21 Paragraf Ltd A method for the manufacture of a graphene-containing laminate
CN115985888B (zh) * 2023-02-23 2024-07-05 天津大学 一种由电容耦合互联得到的集成垂直器件及其制备方法
GB2628126A (en) 2023-03-14 2024-09-18 Paragraf Ltd Methods for the provision of a coated graphene layer structure on a silicon-containing wafer

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6197663B1 (en) * 1999-12-07 2001-03-06 Lucent Technologies Inc. Process for fabricating integrated circuit devices having thin film transistors
EP1636829B1 (en) * 2003-06-12 2016-11-23 Georgia Tech Research Corporation Patterned thin film graphite devices
WO2005019104A2 (en) 2003-08-18 2005-03-03 President And Fellows Of Harvard College Controlled nanotube fabrication and uses
US6821826B1 (en) * 2003-09-30 2004-11-23 International Business Machines Corporation Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers
JP2005285822A (ja) 2004-03-26 2005-10-13 Fujitsu Ltd 半導体装置および半導体センサ
US7180107B2 (en) * 2004-05-25 2007-02-20 International Business Machines Corporation Method of fabricating a tunneling nanotube field effect transistor
JP2005342937A (ja) 2004-06-01 2005-12-15 National Printing Bureau 印刷機用ローラ及びその製造方法
JP3963393B2 (ja) * 2005-03-01 2007-08-22 インターナショナル・ビジネス・マシーンズ・コーポレーション カーボンナノチューブ電界効果トランジスタ及びこれの製造方法
US7547917B2 (en) * 2005-04-06 2009-06-16 International Business Machines Corporation Inverted multilayer semiconductor device assembly
WO2007002297A2 (en) 2005-06-24 2007-01-04 Crafts Douglas E Temporary planar electrical contact device and method using vertically-compressible nanotube contact structures
US20060292823A1 (en) * 2005-06-28 2006-12-28 Shriram Ramanathan Method and apparatus for bonding wafers
US7619257B2 (en) * 2006-02-16 2009-11-17 Alcatel-Lucent Usa Inc. Devices including graphene layers epitaxially grown on single crystal substrates
JP5167479B2 (ja) 2006-06-13 2013-03-21 国立大学法人北海道大学 グラフェン集積回路の製造方法
JP4669957B2 (ja) 2007-03-02 2011-04-13 日本電気株式会社 グラフェンを用いる半導体装置及びその製造方法
KR20100051595A (ko) 2007-05-25 2010-05-17 알에프 나노 코포레이션 시스템-온-칩 애플리케이션용 집적형 나노튜브 및 ｃｍｏｓ 소자 및 제작 방법
FR2916902B1 (fr) * 2007-05-31 2009-07-17 Commissariat Energie Atomique Transistor a effet de champ a nanotubes de carbone
KR101443215B1 (ko) 2007-06-13 2014-09-24 삼성전자주식회사 앰비폴라 물질을 이용한 전계효과 트랜지스터 및 논리회로
US7732859B2 (en) 2007-07-16 2010-06-08 International Business Machines Corporation Graphene-based transistor
US8659009B2 (en) 2007-11-02 2014-02-25 The Trustees Of Columbia University In The City Of New York Locally gated graphene nanostructures and methods of making and using
JP2009182173A (ja) * 2008-01-31 2009-08-13 Fujitsu Ltd グラフェントランジスタ及び電子機器
JP2009277803A (ja) * 2008-05-13 2009-11-26 Fujitsu Ltd 半導体装置、半導体装置の製造方法およびトランジスタ
US7897428B2 (en) 2008-06-03 2011-03-01 International Business Machines Corporation Three-dimensional integrated circuits and techniques for fabrication thereof
US8716805B2 (en) * 2008-06-10 2014-05-06 Toshiba America Research, Inc. CMOS integrated circuits with bonded layers containing functional electronic devices
US7952088B2 (en) 2008-07-11 2011-05-31 International Business Machines Corporation Semiconducting device having graphene channel
US8298914B2 (en) * 2008-08-19 2012-10-30 International Business Machines Corporation 3D integrated circuit device fabrication using interface wafer as permanent carrier
US7858990B2 (en) 2008-08-29 2010-12-28 Advanced Micro Devices, Inc. Device and process of forming device with pre-patterned trench and graphene-based device structure formed therein
US7858989B2 (en) * 2008-08-29 2010-12-28 Globalfoundries Inc. Device and process of forming device with device structure formed in trench and graphene layer formed thereover
US8198707B2 (en) * 2009-01-22 2012-06-12 Board Of Regents, The University Of Texas System Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene
KR101156620B1 (ko) * 2009-04-08 2012-06-14 한국전자통신연구원 그라핀 채널층을 가지는 전계 효과 트랜지스터
US8895352B2 (en) * 2009-06-02 2014-11-25 International Business Machines Corporation Method to improve nucleation of materials on graphene and carbon nanotubes
US8106383B2 (en) * 2009-11-13 2012-01-31 International Business Machines Corporation Self-aligned graphene transistor
US8278643B2 (en) * 2010-02-02 2012-10-02 Searete Llc Doped graphene electronic materials
KR101813176B1 (ko) * 2011-04-07 2017-12-29 삼성전자주식회사 그래핀 전자 소자 및 제조방법
US8772910B2 (en) * 2011-11-29 2014-07-08 International Business Machines Corporation Doping carbon nanotubes and graphene for improving electronic mobility
KR101919424B1 (ko) * 2012-07-23 2018-11-19 삼성전자주식회사 트랜지스터 및 그 제조방법

Also Published As

Publication number Publication date
GB2493238A (en) 2013-01-30
US20110284818A1 (en) 2011-11-24
CN102893387A (zh) 2013-01-23
US8445320B2 (en) 2013-05-21
KR20130018735A (ko) 2013-02-25
JP5719430B2 (ja) 2015-05-20
DE112011100907B4 (de) 2017-11-23
SG184823A1 (en) 2012-11-29
US20130302940A1 (en) 2013-11-14
GB2493238B (en) 2014-04-16
US8900918B2 (en) 2014-12-02
GB201402301D0 (en) 2014-03-26
GB201208558D0 (en) 2012-06-27
US8698165B2 (en) 2014-04-15
DE112011100907T5 (de) 2013-01-03
US20130234114A1 (en) 2013-09-12
US20130240839A1 (en) 2013-09-19
WO2011144423A1 (en) 2011-11-24
TW201207994A (en) 2012-02-16
GB2507686B (en) 2014-07-16
US8878193B2 (en) 2014-11-04
KR101419631B1 (ko) 2014-07-15
TWI497644B (zh) 2015-08-21
GB2507686A (en) 2014-05-07
JP2013531878A (ja) 2013-08-08

Similar Documents

Publication Publication Date Title
CN102893387B (zh) 基于石墨烯沟道的器件及其制造方法
US8466054B2 (en) Thermal conduction paths for semiconductor structures
KR101758852B1 (ko) 후면 방열 기능을 갖는 반도체-온-절연체
JP5048230B2 (ja) 半導体装置およびその製造方法
TWI280661B (en) CMOS fabricated on different crystallographic orientation substrates
JP2013522873A (ja) グラフェン・ベースの三次元集積回路デバイス
US20220130762A1 (en) Semiconductor structure and manufacture method thereof
CN107342258B (zh) 多个背栅极晶体管
US10083880B2 (en) Hybrid ETSOI structure to minimize noise coupling from TSV
US20150325495A1 (en) Electronic device and method for manufacturing the same, and substrate structure and method for manufacturing the same
US11545556B2 (en) Semiconductor device with air gap between gate-all-around transistors and method for forming the same
JP2017523614A (ja) 自己整合裏面特徴部を有する半導体デバイス
TWI692039B (zh) 半導體裝置的製作方法
CN102725850B (zh) 具有减小的寄生电容的体接触晶体管
US11894304B2 (en) Semiconductor device with air gap below landing pad and method for forming the same
US20240274485A1 (en) Heat dissipation in semiconductor devices

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171106

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171106

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right