CN102655081B - 一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法 - Google Patents

一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法 Download PDF

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CN102655081B
CN102655081B CN201210109582.8A CN201210109582A CN102655081B CN 102655081 B CN102655081 B CN 102655081B CN 201210109582 A CN201210109582 A CN 201210109582A CN 102655081 B CN102655081 B CN 102655081B
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郑春生
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    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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Abstract

本发明提供一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法，先在具有栅极结构的硅衬底上淀积形成第一侧墙层，后直接进行浅结离子注入工序。再在，在第一侧墙层上涂覆一层光刻胶并进行光刻胶图案化，暴露出N阱区或P阱区上方的栅极结构，对整个器件进行离子轻掺杂。去除多余的光刻胶和第一侧墙层，在硅衬底表面和栅极上淀积第二侧墙层，并在第二侧墙层上涂覆一层光刻胶。对光刻胶层进行图案化，暴露出另一侧栅极，对整个器件进行离子掺杂。去除多余的光刻胶和第二侧墙层，在硅衬底表面和栅极上依次淀积第三侧墙层和氮化硅层，去除多余第三侧墙层和氮化硅层形成侧墙。

Description

一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法
技术领域
本发明涉及一种CMOS半导体器件集成工艺，尤其涉及一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法。
背景技术
中国专利CN101593686A披露了一种制备金属栅极的集成工艺，采用无定形碳作为可牺牲栅极材料，形成Gate-last工艺所需的基体结构。具体工艺流程包括：在基底上形成栅介质层；在所述栅介质层上形成图形化的非晶碳层；形成环绕所述图形化的非晶碳层的侧墙；形成覆盖所述图形化的非晶碳层及侧墙的层间介质层；平坦化所述层间介质层并暴露所述图形化的非晶碳层；采用氧气灰化工艺去除所述图形化的非晶碳层，在所述层间介质层内形成沟槽；形成填充所述沟槽且覆盖所述层间介质层的金属层。
上述专利提供的流程非常简单，因此需要对其中的很多过程进行细化，比如：栅极成型前的叠层结构；牺牲栅极成型的前处理；牺牲栅极的后处理；常规侧墙结构的形成工艺；离子注入工艺时基体的准备；SPT工艺的处理；CESL处理；CMP工艺前处理等等。
发明内容
本发明针对中国专利CN101593686A提供制备金属栅极的集成工艺中存在问题，进一步细化其中的过程。
为了实现上述目的，本发明提供一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法，包括以下步骤：
步骤1，在具有栅极结构的硅衬底上淀积形成第一侧墙层，后直接进行浅结离子注入工序，所述硅衬底的N-阱区和P-阱区上分别设有栅极，所述栅极为无定形碳材料。
步骤2，在第一侧墙层上涂覆一层光刻胶，并进行光刻胶图案化，暴露出N阱区或P-阱区上方的栅极结构，对整个器件进行离子轻掺杂，所述离子与暴露出的阱区相反。
步骤3，去除多余的光刻胶和第一侧墙层，在硅衬底表面和栅极上淀积第二侧墙层，并在第二侧墙层上涂覆一层光刻胶。
步骤4，对光刻胶层进行图案化，暴露出另一侧栅极，对整个器件进行离子掺杂，所述离子与暴露出的阱区相反。
步骤5，去除多余的光刻胶和第二侧墙层，在硅衬底表面和栅极上依次淀积第三侧墙层和氮化硅层，去除多余第三侧墙层和氮化硅层形成侧墙。
在本发明提供的一个优选实施例中，所述栅极和硅衬底之间还设有栅氧化物层。
在本发明提供的一个优选实施例中，所述第一侧墙选用氧化物、氮氧化硅、或氮化硅材料。
在本发明提供的一个优选实施例中，所述第一侧墙层采用湿法刻蚀去除。
在本发明提供的一个优选实施例中，所述光刻胶和第二侧墙层采用湿法刻蚀去除。
本发明提供的制备方法详细、具体化了中国专利CN101593686A中的浅结（LDD）和侧墙工艺。
附图说明
图1是通过本发明制备得到具有浅结和侧墙的无定形碳牺牲栅极结构。
图2是本发明中淀积第一侧墙层后的器件结构示意图。
图3是本发明中第一次涂覆光刻胶后的器件结构示意图。
图4是本发明中进行P型离子轻掺杂时候的器件结构示意图。
图5是本发明中去除光刻胶和第一侧墙层后的结构示意图。
图6是本发明中淀积第二侧墙层后的器件结构示意图。
图7是本发明中第二次涂覆光刻胶后的器件结构示意图。
图8是本发明中进行N型离子轻掺杂时候的器件结构示意图。
图9是本发明中去除光刻胶和第二侧墙层后的结构示意图。
图10是本发明中淀积第三侧墙层和氮化硅层后的结构示意图。
具体实施方式
本发明提供一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法，先在具有栅极结构的硅衬底上淀积形成第一侧墙层，后直接进行浅结离子注入工序。再在第一侧墙层上涂覆一层光刻胶并进行光刻胶图案化，暴露出N阱区或P-阱区上方的栅极结构，对整个器件进行离子轻掺杂。去除多余的光刻胶和第一侧墙层，在硅衬底表面和栅极上淀积第二侧墙层，并在第二侧墙层上涂覆一层光刻胶。对光刻胶层进行图案化，暴露出另一侧栅极，对整个器件进行离子掺杂。去除多余的光刻胶和第二侧墙层形成完整的浅结，在硅衬底表面和栅极上依次淀积第三侧墙层和氮化硅层，去除多余第三侧墙层和氮化硅层形成侧墙。
以下通过实施例对本发明提供的一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法做进一步详细的说明，以便更好理解本发明创造的内容，但实施例的内容并不限制本发明创造的保护范围。
选用带两个或两个以上的有栅极结构的硅衬底1，栅极5为无定形碳材料，栅极5和硅衬底1之间设有栅氧化物层51，栅极1分别设在硅衬底1的N-阱区2和P-阱区3内。
如图2所示，先在硅衬底1和栅极5上淀积形成第一侧墙层61，后直接进行浅结离子注入工序。因为需要保留栅极顶部的侧墙，所以省去常规的刻蚀侧墙的步骤，进而直接进行浅结离子注入工序。第一侧墙61选用氧化物、氮氧化硅、或氮化硅中一种材料。
如图3和4所示，在第一侧墙层61上涂覆一层光刻胶71，并对该光刻胶71进行图案化处理，暴露出N阱区2上方的栅极结构，对整个器件进行P型离子轻掺杂。轻掺杂离子的种类和暴露出栅极下方的阱区有关，如暴露出是P阱区3上的栅极结构，则需要用N型离子轻掺杂。
如图5、6、7和8所示，采用湿法刻蚀去除多余的光刻胶71和第一侧墙层61。在硅衬底1表面和栅极5上淀积第二侧墙层62，在第二侧墙层62上涂覆一层光刻胶72。对光刻胶72进行图案化处理，暴露出P阱区3上方的栅极结构，对整个器件进行N型离子轻掺杂。
如图9和10所示，采用湿法刻蚀去除多余的光刻胶72和第二侧墙层62形成完整的浅结9（包括NLDD和PLDD）。再次，在硅衬底1表面和栅极5上依次淀积第三侧墙层63和氮化硅层8，去除多余第三侧墙层63和氮化硅层8形成侧墙，即形成图1所示的具有浅结和侧墙的无定形碳牺牲栅极结构，图中9为STI。
本发明中，在浅结光刻胶图形化处理之前，将无定形碳外露部分密封起来，使得灰化处理进行去除光刻胶的时候不会损失无定形碳栅极。采用两道侧墙牺牲层（第一侧墙61和第二侧墙62），分别参与浅结的形成。
以上对本发明的具体实施例进行了详细描述，但其只是作为范例，本发明并不限制于以上描述的具体实施例。对于本领域技术人员而言，任何对本发明进行的等同修改和替代也都在本发明的范畴之中。因此，在不脱离本发明的精神和范围下所作的均等变换和修改，都应涵盖在本发明的范围内。

Claims (4)

1.一种无定形碳牺牲栅极结构的浅结和侧墙的制备方法，其特征在于，包括以下步骤：
步骤1，在具有栅极结构的硅衬底上淀积形成第一侧墙层，所述第一侧墙层覆盖在所述硅衬底、所述栅极侧壁和所述栅极上表面，之后直接进行浅结离子注入工序，所述硅衬底的N-阱区和P-阱区上分别设有栅极，所述栅极为无定形碳材料；
步骤2，在第一侧墙层上涂覆一层光刻胶，并进行光刻胶图案化，暴露出N阱区或P-阱区上方的栅极结构，对整个器件进行离子轻掺杂，所述离子与暴露出的阱区相反；
步骤3，去除多余的光刻胶和第一侧墙层，在硅衬底表面和栅极上淀积第二侧墙层，所述第二侧墙层覆盖在所述硅衬底、所述栅极侧壁和所述栅极上表面，并在第二侧墙层上涂覆一层光刻胶；
步骤4，对光刻胶层进行图案化，暴露出另一侧栅极，对整个器件进行离子掺杂，所述离子与暴露出的阱区相反；
步骤5，去除多余的光刻胶和第二侧墙层，在硅衬底表面和栅极上依次淀积第三侧墙层和氮化硅层，去除多余第三侧墙层和氮化硅层形成侧墙；
其中，所述第一侧墙选用氧化物、氮氧化硅、或氮化硅材料，且所述第一侧墙、所述第二侧墙将所述栅极密封起来，使得灰化处理所述光刻胶时不会损失所述栅极。
2.根据权利要求1所述的制备方法，其特征在于，所述栅极和硅衬底之间还设有栅氧化物层。
3.根据权利要求1所述的制备方法，其特征在于，所述第一侧墙层采用湿法刻蚀去除。
4.根据权利要求1所述的制备方法，其特征在于，所述光刻胶和第二侧墙层采用湿法刻蚀去除。
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