CN102646670B - 半导体器件及其制作方法 - Google Patents
半导体器件及其制作方法 Download PDFInfo
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- CN102646670B CN102646670B CN201210120485.9A CN201210120485A CN102646670B CN 102646670 B CN102646670 B CN 102646670B CN 201210120485 A CN201210120485 A CN 201210120485A CN 102646670 B CN102646670 B CN 102646670B
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- 238000002955 isolation Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 description 10
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- 238000010586 diagram Methods 0.000 description 5
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- 238000002360 preparation method Methods 0.000 description 4
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- 229910052802 copper Inorganic materials 0.000 description 2
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- 230000001360 synchronised effect Effects 0.000 description 2
- 229910052714 tellurium Inorganic materials 0.000 description 2
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 1
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Abstract
本发明公开了一种半导体器件及其制作方法,该半导体器件包括:引线框架;第一垂直型晶体管芯片,包括具有第一源极电极、第一漏极电极和第一栅极电极的第一垂直型晶体管,其中第一垂直型晶体管芯片附着至引线框架,第一源极电极电耦接至引线框架;第二垂直型晶体管芯片,包括具有第二源极电极、第二漏极电极和第二栅极电极的第二垂直型晶体管,其中第二垂直型晶体管芯片堆叠在第一垂直型晶体管芯片上,第二源极电极电耦接至第一垂直型晶体管的第一漏极电极。
Description
技术领域
本发明涉及一种半导体器件,尤其涉及一种包括垂直型功率晶体管的半导体器件及其制作方法。
背景技术
垂直型功率晶体管,例如垂直型的金属氧化物半导体场效应晶体管(MOSFET)、垂直型结型场效晶体管(JFET)或者场效应晶体管(FET),被广泛使用在功率管理应用中。在一些功率管理应用中,例如在半桥驱动器,同步降压变换器、同步升压变换器中,均包括串联连接的垂直型功率晶体管。
图1是根据现有技术的开关功率变换器100的原理图。开关功率变换器100包括低侧功率晶体管101、高侧功率晶体管102和控制器103。高侧功率晶体管102的漏极电极102D耦接至输入端子以接收供电电源VIN。高侧功率晶体管102的栅极电极102G和低侧功率晶体管101的栅极电极101G均接收来自控制器103的栅极控制信号。高侧功率晶体管102的源极电极102S与低侧功率晶体管101的漏极电极101D彼此连接在一起形成开关节点SW,在该节点SW输出开关信号。低侧功率晶体管101的源极电极101S连接至地GND。
在一些大功率应用场合中,高侧功率晶体管102和低侧功率晶体管101可以采用例如垂直型MOSFET这样的垂直型功率晶体管。垂直型功率晶体管通常包括位于功率晶体管芯片底面的漏极电极、位于功率晶体管芯片顶面的源极电极和栅极电极。通常,高侧功率晶体管102、低侧功率晶体管101以及控制器103被制作在不同的半导体芯片上,这些半导体芯片被放置在引线框架104的同一表面上。图2是图1所示开关功率变换器100的传统封装结构200的示意图。如图2所示,高侧功率晶体管102的漏极电极102D和低侧功率晶体管101的漏极电极101D被贴装在引线框架104的不同的、彼此隔离的部分。
对于大功率器件,引线框架可用作散热器。为了便于将器件集成在印制电路板(PCB)上,通常将散热器连接至地。图1所示的开关功率变换器100具有如图2所示的封装结构,其中高侧功率晶体管102的漏极电极102D与低侧功率晶体管101的漏极电极101D均附着至引线框架104上,分别耦接至恒定的高电压VIN和在高电压和低电压之间变换的开关节点SW。通常,具有恒定高电压的裸露的引线框架不是我们所期望的,因为这会增加PCB板上的高压散热面积。而裸露的引线框架在高压与低压之间切换,更不是我们想要的,因为这会引起电磁干扰(EMI)。而且,由于多个芯片并排放置,图2所示传统封装结构的封装尺寸较大。此外,不同的半导体芯片之间通过引线键合来连接,会因此引入寄生电感和寄生电容。再者,多个露出的引线框架部分彼此靠近,使得共装(co-packaged)产品至PCB的附着工艺复杂化。
发明内容
针对现有技术中的一个或多个问题,本发明的一个目的是提供一种多芯片封装结构的半导体器件及其制作方法。
为实现上述目的,本发明提供一种半导体器件,包括:引线框架;第一垂直型晶体管芯片,包括具有第一源极电极、第一漏极电极和第一栅极电极的第一垂直型晶体管,其中第一垂直型晶体管芯片附着至引线框架,第一源极电极电耦接至引线框架;第二垂直型晶体管芯片,包括具有第二源极电极、第二漏极电极和第二栅极电极的第二垂直型晶体管,其中第二垂直型晶体管芯片堆叠在第一垂直型晶体管芯片上,第二源极电极电耦接至第一垂直型晶体管的第一漏极电极。
根据本发明还提供一种半导体器件的制作方法,该半导体器件包括第一垂直型晶体管芯片和第二垂直型晶体管芯片,该制作方法包括:制作具有第一源极电极、第一漏极电极和第一栅极电极的第一垂直型晶体管;制作具有第二源极电极、第二漏极电极和第二栅极电极的第二垂直型晶体管;将第一垂直型晶体管芯片贴装于引线框架上并将第一源极电极电耦接至引线框架;以及将第二垂直型晶体管芯片堆叠于第一垂直型晶体管芯片上并将第二源极电极耦接至第一垂直型晶体管芯片的第一漏极电极。
根据本发明实施例的半导体器件及其制作方法,将第一垂直型晶体管和第二垂直型晶体管堆叠放置,减小了半导体器件封装的尺寸,同时第一和第二垂直型晶体管间的互连电感和电阻也随之减少。
附图说明
结合以下附图阅读本发明实施例的详细描述可以更好地理解本发明。应理解,附图的特征不是按比例绘制的,而是示意性的。
图1是根据现有技术的开关功率变换器100的原理图;
图2是图1所示开关功率变换器100的传统封装结构200的示意图;
图3是根据本发明一实施例的多芯片半导体器件300的剖视图;
图4是根据本发明一实施例的具有顶侧漏极电极和栅极电极的垂直型晶体管400的剖视图;
图5是根据本发明一实施例的多芯片半导体器件500的剖视图;
图6是根据本发明一实施例的图5所示的多芯片半导体器件500的俯视图;
图7是根据本发明一实施例的集成有第一芯片和第二芯片的半导体器件的制作方法700的流程图。
具体实施方式
下面参照附图描述与本发明有关的半导体器件、封装以及制作方法的各个实施例。为了更好地理解本发明,在下面的描述中给出了一些具体的细节,例如示例电路以及这些示例电路中元器件的示例值。本领域的技术人员应理解,缺少一个或多个具体细节,或者增加其他的方法、元件或者材料等,本发明同样可以实施图3~图7中所描述的实施例。此外,为了清楚地阐述本发明,在本发明的描述中省去了一些公知的结构、材料或步骤的详细描述以及示意图。
本发明的实施例涉及一种半导体器件,该半导体器件包括堆叠设置的的第一垂直型晶体管和第二垂直型晶体管。在一个实施例中,第一和第二垂直型晶体管均具有位于底面的源极电极以及位于顶面的漏极电极和栅极电极。第二垂直型晶体管堆叠在第一垂直型晶体管之上,第二垂直型晶体管的源极直接接触第一垂直型晶体管的漏极。
在另一个实施例中,第一垂直型晶体管具有位于底面的漏极电极与位于顶面的源极电极和栅极电极。第一垂直型晶体管倒装在引线框架上,该引线框架包括彼此电隔离的第一平板和第二平板。第一垂直型晶体管的源极电极和栅极电极分别耦接至引线框架的第一平板和第二平板。第一垂直型晶体管还包括位于底面的接触板。第二垂直型晶体管具有位于第二垂直型晶体管芯片底面的漏极电极与位于顶面的源极电极和栅极电极。第二垂直型晶体管倒装于第一垂直型晶体管上,第二垂直型晶体管的源极电极和栅极电极分别耦接至第一垂直型晶体管的漏极电极和接触板。第一垂直型晶体管的接触板水平向外延伸出第二垂直型晶体管芯片的外缘。
通过堆叠第一和第二垂直型晶体管芯片,与传统的封装相比,可以减小半导体器件封装的尺寸,第一和第二垂直型晶体管间的互连电感和电阻也可随之减少。在进一步的实施例中,控制芯片(未画出)与第一和第二垂直型晶体管封装在一起,与传统的封装相比,改善了热性能,使得封装更小更便宜。
在整个说明书和权利要求书中,对“左”、“右”、“内”、“外”、“前”、 “后”、“向上”、“向下”、“顶部”、“在顶部”、“在底部”、“在正下方”、“在上方”、“在下方”以及其它类似方位词语的使用都只是为了说明的目的,并不是为了表达其相对位置的不可变。本领域普通技术人员应当理解,本发明的实施例中提供的方位词语在不同的适用场合下是可以变化的,例如,文中所描述的方向仅仅是示意性的,并不仅限于此方向,其他方向也是可能的。此外,本文所称“耦接”的是指以电或者非电的形式直接或间接连接。
为描述方便,本发明以制作于硅半导体衬底上或位于硅半导体衬底中的N沟道垂直型器件为例来进行说明。本领域的技术人员应当理解,具有相反掺杂类型的P沟道垂直型器件同样满足本发明的精神和保护范围。在本发明的实施例中,常选用多晶硅来填充沟槽。这些实施例并不限制导电材料(例如金属、半导体、金属-半导体和或他们的组合)的选择,只要所选的材料与器件制作工艺过程中的其它方面兼容即可。因此,本文所称“填充聚乙烯的”和“填充多晶硅的”可包括除多晶硅之外的其他材料或者其他材料的组合。
图3是根据本发明一实施例的多芯片半导体器件300的剖视图。多芯片半导体器件300包括位于封装305中的第一垂直型晶体管芯片301和第二垂直型晶体管芯片303。此外,封装305还包括引线框架307,该引线框架307包括多个引脚309A~309E。在一个实施例中,第一垂直型晶体管芯片301包括第一垂直型晶体管,该第一垂直型晶体管具有第一源极电极301S、第一漏极电极301D以及第一栅极电极301G。第二垂直型晶体管芯片303包括第二垂直型晶体管,该第二垂直型晶体管具有第二源极电极303S、第二漏极电极303D以及第二栅极电极303G。第一源极电极301S位于第一垂直型晶体管芯片301的下表面301B,第一漏极电极301D和第一栅极电极301G均位于第一垂直型晶体管芯片301的上表面301T。第二源极电极303S位于第二垂直型晶体管芯片303的下表面303B,第二漏极电极303D和第二栅极电极303G均位于第二垂直型晶体管芯片303的上表面303T。在一个实施例中,第一垂直型晶体管芯片301和/或第二垂直型晶体管芯片303具有其他合适的结构。
在一个实施例中,第一源极电极301S和第二源极电极303S被处理以适于倒装封装。第一垂直型晶体管芯片301的第一源极电极301S包括允许第一源极电极301S通过倒装凸块311附着并电耦接至引线框架307的连接点。引线框架307包括引脚309A,引脚309A可用作某种功能,例如接地引脚GND。这样,引线框架307露出并作为散热器,被直接附着至PCB的接地。
第二垂直型晶体管芯片303的第二源极电极303S具有接触点,该接触点允许第二源极电极303S通过倒装凸块313被附着并电耦接至第一垂直型晶体管芯片301的第一漏极电极301D。这样,第一垂直型晶体管芯片301与第二垂直型晶体管芯片303可以直接连接,以减少传统的多芯片封装中键合线引入的寄生电感和电阻。在一个实施例中,倒装凸块311和313包括铜柱凸块或者焊料凸块。在其它实施例中,倒装凸块311和313可包括金凸块和/或其他合适的互连结构。在一个实施例中,第一漏极电极301D延伸超过第二垂直型晶体管芯片303的外缘,使得第一漏极电极301D可以连接至引脚309B。相似地,第一栅极电极301G延伸超过第二垂直型晶体管芯片303的外缘,使得第一栅极电极301G可以连接至引脚309C或者共装控制电路(co-packaged control circuit),例如与图1所示控制器相似的电路。此外,第二栅极电极303G耦接至引脚309D,第二漏极电极303D耦接至引脚309E。在其它实施例中,第一漏极电极301D和/或第一栅极电极301G具有其他合适的结构。
在一个实施例中,第一漏极电极301D和引脚309B的连接,第一栅极电极301G和引脚309C的连接,以及第一漏极电极303D和引脚309E的连接均通过键合线来实现。在其它实施例中,至少一个上述的连接可以通过其他合适的耦接件来实现。
在一个实施例中,引脚309B可以用作开关引脚SW,引脚309C用作控制信号接收引脚G1,引脚309D用作另一个控制信号接收引脚G2,引脚309E用作输入引脚VIN。在其它实施例中,上述引脚可具有其他合适的功能和/或结构。
在一个实施例中,半导体器件300还包括共装控制电路(未画出),该控制电路耦接至第一垂直型晶体管芯片301和第二垂直型晶体管芯片303以提供控制信号。在一个实施例中,第一垂直型晶体管芯片301的第一栅极电极301G不耦接至引脚309C,而是耦接至共装控制电路。在另一个实施例中,第一栅极电极301G经过键合线耦接至共装控制电路以接收栅极控制信号。相似地,第二垂直型晶体管芯片303的第二栅极电极303G也耦接至共装控制电路。
图4是根据本发明一实施例的具有顶侧漏极和栅极的垂直型晶体管400的剖视图。图3所示的第一垂直型晶体管芯片301和/或第二垂直型晶体管芯片303具有与垂直型晶体管400基本相似的结构和功能。如图4所示,垂直型晶体管400包括底侧衬底,在其底侧衬底上形成有漏极或阴极,例如垂直型晶体管400包括垂直型沟槽MOSFET、VDMOS、垂直型JFET、和/或其他合适的器件。图4中,垂直型晶体管400表示为沟槽栅MOSFET仅仅是为了说明的目的,垂直型晶体管400还可包括平面栅MOSFET、VDMOS、垂直型JFET和/或其他合适的器件。
在图4所示的实施例中,垂直型晶体管400包括重掺杂的N+衬底402,在衬底402上形成垂直型晶体管400的漏极。N-外延层404位于N+衬底402的下表面S1。在N-外延层404中制作有P型体区406、N+源极区408、栅极沟槽410和栅极接触沟槽412。绝缘材料414和416分别被制作在栅极沟槽410和栅极接触沟槽412的侧壁和底部。在一个实施例中,绝缘材料414和416包括相同的材料(例如栅氧化物)并在同一步骤制作。在其它实施例中,绝缘材料414和416包括不同的材料,和/或被制作于不同的工艺步骤。
栅极418制作于栅极沟槽410中,栅极接触420制作于栅极接触沟槽412中。在一个实施例中,栅极418和栅极接触420包括相同的材料(例如重掺杂的多晶硅)并在同一步骤制作。在其它实施例中,栅极418和栅极接触420可包括不同的材料,和/或被制作于不同的工艺步骤。
在一个实施例中,栅极沟槽410和栅极接触沟槽412通过栅极沟槽410或者栅极接触沟槽412的横截面部分连接起来。介电层422制作于N-外延层404的下表面S2,用于将体区406、源极408以及栅极418与源极电极424A以及栅极电极424B分离开来。介电层422可包括碲掺杂玻璃(TEOS,Tellurium doped glass)、磷硅玻璃(PSG,Phosphosilicate glass)、硼磷硅玻璃(BPSG,Borophosphosilicate glass)或者旋压玻璃(SOG,Spin-on glass)。源极接触开口426允许源极电极424A与N+源极区408以及P型体区406之间的电接触。同样,栅极接触开口428允许栅极电极424B与栅极418之间的电接触。
垂直型晶体管400进一步包括用于将栅极接触420连接至顶侧栅极电极432的沟槽430,其中顶侧栅极电极432位于N+衬底402的上表面S3上。栅极接触434包括导电材料(例如钨,重掺杂的多晶硅),延伸通过沟槽430,提供顶侧栅极电极432与栅极接触420之间的电接触。沟槽绝缘层436包括绝缘材料(例如氧化物),制作于沟槽430的侧壁,将栅极接触434与N+衬底402和N-外延层404电隔离。介电层438制作于N+衬底402的第二表面S3。在介电层438的表面制作金属化层,图案化并蚀刻该金属化层以在垂直型晶体管400的顶面上形成分隔的漏极电极440和栅极电极432。
具有顶侧漏极电极和栅极电极的垂直型晶体管具有多种可变类型。在一个实施例中,不制作图4中所示的低侧栅极电极424B,垂直型晶体管400的底侧表面可整个用于制作源极电极424A。在另一个实施例中,沟槽430被充分蚀刻,穿通介电层438、N+衬底402、N-外延层404和介电层422以接触底侧栅极电极424B。
图5是根据本发明一实施例的多芯片半导体器件500的剖视图。多芯片半导体器件500包括位于封装505中的第一垂直型晶体管芯片501和第二垂直型晶体管芯片503。封装505还包括引线框架507,引线框架507包括多个引脚509A~509E。
在一个实施例中,第一垂直型晶体管芯片501包括具有第一漏极电极501D、第一源极电极501S和第一栅极电极501G的第一垂直型晶体管。第一漏极电极501D位于第一垂直型晶体管芯片501的上表面501T。第一源极电极501S和第一栅极电极501G位于第一垂直型晶体管芯片501的底面501B。第一垂直型晶体管芯片501还包括位于上表面501T上的接触板501C。接触板501C与第一栅极电极501D电隔离,也与第一垂直型晶体管501的衬底电隔离。
此外,第二垂直型晶体管芯片503包括具有第二漏极电极503D、第二源极电极503S和第二栅极电极503G的第二垂直型晶体管。第二漏极电极503D位于第二垂直型晶体管芯片503的上表面503T,第二源极电极503S和第二栅极电极503G位于第二垂直型晶体管芯片503的下表面503B。第二垂直型晶体管芯片503可包括垂直型MOSFET、VDMOS、JFET和/或其他合适的器件。
在一个实施例中,第一垂直型晶体管芯片501和/或第二垂直型晶体管芯片503包括:衬底,具有上表面和与上表面相对的下表面;外延层,位于衬底的上表面,具有上表面,该上表面与衬底的上表面相对;源极区和栅极,位于外延层中,靠近外延层的上表面;源极电极,位于外延层的上表面,耦接至源极区并与栅极隔离;漏极电极,位于衬底的下表面,耦接至用作漏极的衬底;栅极电极,靠近外延层的上表面,与源极区隔离。
在一个实施例中,引线框架507被图案化以包括接收第一源极电极501S的第一平板507A和接收第一栅极电极501G的第二平板507B。第一平板507A和第二平板507B彼此电隔离。在其它实施例中,引线框架507还包括芯片焊盘,其他平板,和/或其他合适的元件和/或结构。
在一个实施例中,第一垂直型晶体管芯片501被倒装,经底面501B耦接至引线框架507。第一源极电极501S和第一栅极电极501G被处理以适于倒装封装。例如,第一垂直型晶体管芯片501的第一源极电极501S具有允许第一源极电极501S通过倒装凸块511被附着并电耦接至第一平板507A的接触点。相似地,第一栅极电极501G具有允许第一栅极电极501G通过倒装凸块513被附着并电耦接至第二平板507B的接触点。
在一个实施例中,第一平板507A被连接至引脚509A以实现到PCB的连接。引脚509A可能用作,例如接地引脚GND。这样,露出的并用作散热器的引线框架507的第一平板507A被接地。。在一个实施例中,第二平板507B电耦接至引脚509B,引脚509B可用作栅极控制信号接收引脚G1。在其它实施例中,第一和/或第二平板507A和507B可具有其他合适的功能和/或结构。
如图5所示,第二垂直型晶体管芯片503堆叠于第一垂直型晶体管芯片501上,第二源极电极503S耦接至第一漏极电极501D。第二垂直型晶体管芯片晶体管芯片503的第二源极电极503S和第二栅极电极503G被处理以适于倒装封装。在一个实施例中, 第二源极电极503S具有允许第二源极电极503S通过倒装凸块515附着并电耦接至第一垂直型晶体管芯片的第一漏极电极501D的接触点。第一垂直型晶体管芯片501和第二垂直型晶体管芯片503之间的直接连接可以减少在传统的多芯片并排封装中键合线引入的寄生电阻和电感。在一个实施例中,第二栅极电极503G具有允许第二栅极电极503G通过倒装凸块517附着并电耦接至接触板501C的接触点,其中接触板501C位于第一垂直型晶体管芯片501的上表面501T之上。在其它实施例中,第二栅极电极503G可具有其他合适的结构。在一个实施例中,倒装凸块511,513,515和517可包括铜柱凸块或者焊料凸块。在其它实施例中,倒装凸块511,513,515和517中的至少一个可以包括其他合适的互连结构。
在一个实施例中,第一漏极电极501D的一部分和第一垂直型晶体管芯片501的接触板501C的一部分延伸超过第二垂直型晶体管芯片503的外缘,这样第一漏极电极501D可以连接至引脚509C,接触板501C和第二栅极电极503G可以连接至引脚509D。在一个实施例中,第一漏极电极501D经键合线519连接至引脚509C。接触板501C经键合线521连接至引脚509D,从而将第二栅极电极503G耦接至引脚509D。第二垂直型晶体管芯片503的第二漏极电极503D经键合线523耦接至引脚509E。在其它实施例中,可以使用其他合适的互连元件。在一个实施例中,引脚509C用作开关引脚SW,引脚509D用作栅极控制信号接收引脚G2,引脚509E用作电源接收引脚VIN。在其它实施例中,上述引脚509C、509D和509E可以具有其他功能。
在一个实施例中,半导体器500进一步包括共装控制电路(未画出),共装控制电路耦接至第一垂直型晶体管芯片501和第二垂直型晶体管芯片503以提供控制信号。在一个实施例中,第一垂直型晶体管芯片501的第一栅极电极501G经键合线耦接至共装控制电路以接收栅极控制信号。在另一个实施例中,第二垂直型晶体管503的第二栅极电极503G经键合线耦接至共装控制电路以接收栅极控制信号。
图6是根据本发明一实施例的图5所示多芯片半导体器件500的俯视图。如图6所示,可以沿图6所示的虚线AA’截得图5所示的半导体器件500的剖视图。第一垂直型晶体管芯片501贴装于引线框架507上,其中第一源极电极501S经倒装凸块511电耦接至第一接触板507A,第一栅极电极501G经倒装凸块513电耦接至第二接触板507B。第二垂直型晶体管芯片503堆叠于第一垂直型晶体管芯片501上。第二垂直型晶体管芯片503的第二源极电极503S经倒装凸块515电耦接至第一垂直型晶体管芯片501的第一漏极电极501D。第二垂直型晶体管芯片503的第二栅极电极503G经倒装凸块517电耦接至第一垂直型晶体管芯片501的接触板501C。第一垂直型晶体管芯片501的第一漏极电极501D经键合线519耦接至引脚509C,引脚509C用作开关引脚SW。
第二垂直型晶体管芯片503的第二漏极电极503D经键合线521耦接至引脚509E,该引脚509E用作电源引脚VIN。第一垂直型晶体管芯片501的接触板501C经键合线523耦接至引脚509D,引脚509D用作将栅极控制信号耦接至第二垂直型晶体管芯片503的第二栅极电极503G的栅极控制信号接收引脚G2。引线框架的第一接触板507A连接至引脚509A,引脚509A用作接地引脚GND以使得第一垂直型晶体管501的第一源极电极501S耦接至地。引线框架的第二接触板507B连接至引脚509B,引脚509B用作用作将栅极控制信号耦接至第一垂直型晶体管芯片501的第一栅极电极501G的栅极控制信号接收引脚G1。
图7是根据本发明一实施例的集成有第一芯片和第二芯片的半导体器件的制作方法700的流程图。该制作方法700包括步骤701到步骤704。
步骤701:在第一垂直型晶体管芯片上制作第一垂直型晶体管,在第二垂直型晶体管芯片上制作第二垂直型晶体管,其中第一垂直型晶体管具有第一源极电极、第一漏极电极和第一栅极电极,第二垂直型晶体管具有第二源极电极、第二漏极电极和第二栅极电极。
步骤702:提供具有引线框架的封装,该引线框架包括多个引脚。
步骤703:将第一垂直型晶体管贴装于引线框架上,使第一源极电极电耦接至引线框架。
步骤704:将第二垂直型晶体管芯片堆叠于第一垂直型晶体管芯片上,使第二源极电极耦接至第一垂直型晶体管芯片的第一漏极电极。
在一个实施例中,该制作方法700还包括步骤705,将第一源极、栅极和漏极电极、以及第二栅极、漏极电极分别耦接至多个引脚中的第一引脚、第二引脚、第三引脚、第四引脚以及第五引脚。第一源极电极连接至多个引脚中的第一引脚,第一栅极电极通过第一键合线耦接至多个引脚中的第二引脚,第一漏极电极通过第二键合线耦接至多个引脚中的第三引脚,第二栅极电极通过第三键合线耦接至多个引脚中的第四引脚,以及第二漏极电极通过第四键合线耦接至多个引脚中的第五引脚。
在一个实施例中,第一垂直型晶体管芯片和第二垂直型晶体管芯片均具有第一表面和与第一表面平行相对的第二表面。
在一个实施例中,步骤701中第一垂直型晶体管的制作步骤包括:在第一垂直型晶体管芯片的第一表面制作第一漏极电极和第一栅极电极,在第一垂直型晶体管芯片的第二表面制作第一源极电极。第二垂直型晶体管的制作步骤包括:在第二垂直型晶体管芯片的第一表面制作第二漏极电极和第二栅极电极,在第二垂直型晶体管芯片的第二表面制作第二源极电极。在一个实施例中,第二垂直型晶体管芯片的尺寸小于第一垂直型晶体管芯片的尺寸,以露出一部分第一漏极电极。
在一个实施例中,步骤701中第一垂直型晶体管的制作步骤包括:在第一垂直型晶体管芯片的第一表面制作第一源极电极和第一栅极电极,在第一垂直型晶体管芯片的第二表面制作第一漏极电极。第一垂直型晶体管的制作步骤还包括:在第一垂直型晶体管芯片的第二表面制作接触板。第二垂直型晶体管的制作步骤包括:在第二垂直型晶体管芯片的第一表面制作第二源极电极和第二栅极电极,在第二垂直型晶体管芯片的第二表面制作第二漏极电极。在一个实施例中,第二垂直型晶体管芯片的尺寸小于第一垂直型晶体管芯片的尺寸,以露出一部分第一漏极电极和一部分接触板。在步骤702中提供具有彼此隔离的第一接触板和第二接触板的封装。在步骤703中,在引线框架上贴装第一垂直型晶体管芯片的步骤包括将第一源极电极耦接至引线框架的第一接触板,以及将第一栅极电极耦接至引线框架的第二接触板。在步骤704中,在第一垂直型晶体管芯片上堆叠第二垂直型晶体管芯片的步骤还包括将第二栅极电极耦接至第一垂直型晶体管芯片的接触板。在步骤705中,引线框架的第一接触板被耦接至多个引脚中的第一引脚,引线框架的第二接触板被耦接至多个引脚中的第二引脚,第一垂直型晶体管芯片的第一漏极电极经第一键合线被耦接至多个引脚中的第三引脚,第一垂直型晶体管芯片的接触板经第二键合线被耦接至多个引脚中的第四引脚,第二漏极电极经第三键合线被耦接至多个引脚中的第五引脚。
上述本发明的说明书和实施仅仅以示例性的方式对本发明进行了说明,这些实施例不是完全详尽的,并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的,其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其他变化和修改并不超出本发明的精神和保护范围。
Claims (5)
1.一种半导体器件,包括:
引线框架,包括彼此电隔离的第一平板和第二平板;
第一垂直型晶体管芯片,包括具有第一源极电极、第一漏极电极和第一栅极电极的第一垂直型晶体管,其中第一垂直型晶体管芯片附着至引线框架,第一源极电极电耦接至引线框架;以及
第二垂直型晶体管芯片,包括具有第二源极电极、第二漏极电极和第二栅极电极的第二垂直型晶体管,其中第二垂直型晶体管芯片堆叠在第一垂直型晶体管芯片上,第二源极电极电耦接至第一垂直型晶体管的第一漏极电极;其中
第一垂直型晶体管和第二垂直型晶体管均包括:衬底,具有上表面和与上表面相对的下表面;和外延层,位于衬底的上表面,具有与衬底的上表面相对的上表面;并且第一源极电极和第一栅极电极位于第一垂直型晶体管的外延层的上表面,第一漏极电极位于第一垂直型晶体的衬底的下表面;以及第二源极电极和第二栅极电极位于第二垂直型晶体管的外延层的上表面,第二漏极电极位于第二垂直型晶体管的衬底的下表面;
其特征在于:
第一垂直型晶体管芯片还包括接触板,该接触板位于所述第一垂直型晶体管的衬底的下表面上;
第一源极电极通过倒装凸块耦接至引线框架的第一平板;
第一栅极电极通过倒装凸块耦接至引线框架的第二平板;
第二源极电极通过倒装凸块耦接至第一垂直型晶体管芯片的第一漏极电极;
第二栅极电极通过倒装凸块耦接至第一垂直型晶体管芯片的接触板。
2.如权利要求1所述的半导体器件,其中第一垂直型晶体管和第二垂直型晶体管进一步包括:
源极区和栅极,位于外延层中并邻近外延层的上表面;以及其中
源极电极,位于外延层的上表面,与源极区耦接并与栅极隔离;
漏极电极,位于衬底的下表面;以及
栅极电极,靠近外延层的上表面并与源极区隔离。
3.如权利要求1所述的半导体器件,其中
引线框架还包括多个引脚;
引线框架的第一平板耦接至多个引脚中的第一引脚;
引线框架的第二平板耦接至多个引脚中的第二引脚;
第一垂直型晶体管芯片的第一漏极电极通过第一键合线耦接至多个引脚中的第三引脚;
第一垂直型晶体管芯片的接触板通过第二键合线耦接至多个引脚中的第四引脚;以及
第二漏极电极通过第三键合线耦接至多个引脚中的第五引脚。
4.如权利要求1所述的半导体器件,进一步包括控制电路芯片,其中:
引线框架还包括多个引脚;
引线框架的第一平板耦接至多个引脚中的第一引脚;
引线框架的第二平板耦接至控制电路芯片;
第一垂直型晶体管芯片的第一漏极电极通过第一键合线耦接至多个引脚中的第二引脚;
第一垂直型晶体管芯片的接触板通过第二键合线耦接至控制电路芯片;以及
第二漏极电极通过第三键合线耦接至多个引脚中的第四引脚。
5.一种半导体器件的制作方法,该半导体器件包括第一垂直型晶体管芯片和第二垂直型晶体管芯片,该制作方法包括:
制作具有第一源极电极、第一漏极电极和第一栅极电极的第一垂直型晶体管;
制作具有第二源极电极、第二漏极电极和第二栅极电极的第二垂直型晶体管;
将第一垂直型晶体管芯片贴装于引线框架上,使第一源极电极电耦接至引线框架;以及
将第二垂直型晶体管芯片堆叠于第一垂直型晶体管芯片上,使第二源极电极耦接至第一垂直型晶体管芯片的第一漏极电极;其中
所述引线框架包括彼此隔离的第一平板和第二平板;
制作第一垂直型晶体管的步骤包括:提供衬底,该衬底具有上表面和与上表面相对的下表面;在该衬底的上表面上制作外延层,该外延层具有与该衬底的上表面相对的上表面;在该外延层的上表面上制作所述第一源极电极和第一栅极电极,以及在该衬底的下表面制作所述第一漏极电极;
制作第二垂直型晶体管的步骤包括:提供衬底,该衬底具有上表面和与上表面相对的下表面;在该衬底的上表面上制作外延层,该外延层具有与该衬底的上表面相对的上表面;在该外延层的上表面上制作所述第二源极电极和第二栅极电极,以及在该衬底的下表面制作所述第二漏极电极;其特征在于:
制作第一垂直型晶体管的步骤还包括:在该第一垂直型晶体管的衬底的下表面上制作接触板;
将第一垂直型晶体管贴装于引线框架上的步骤包括:将所述第一源极电极通过倒装凸块耦接至引线框架的第一平板,以及将所述第一栅极电极通过倒装凸块耦接至引线框架的第二平板;
将第二垂直型晶体管芯片堆叠于第一垂直型晶体管芯片上的步骤包括:将所述第二源极电极通过倒装凸块耦接至所述第一漏极电极,以及将所述第二栅极电极通过倒装凸块耦接至第一垂直型晶体管芯片的接触板。
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CN103035631B (zh) * | 2011-09-28 | 2015-07-29 | 万国半导体(开曼)股份有限公司 | 联合封装高端和低端芯片的半导体器件及其制造方法 |
JP5924110B2 (ja) * | 2012-05-11 | 2016-05-25 | 株式会社ソシオネクスト | 半導体装置、半導体装置モジュールおよび半導体装置の製造方法 |
CN102832189B (zh) * | 2012-09-11 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | 一种多芯片封装结构及其封装方法 |
US9117873B2 (en) * | 2012-09-27 | 2015-08-25 | Apple Inc. | Direct multiple substrate die assembly |
US9589929B2 (en) | 2013-03-14 | 2017-03-07 | Vishay-Siliconix | Method for fabricating stack die package |
US9966330B2 (en) | 2013-03-14 | 2018-05-08 | Vishay-Siliconix | Stack die package |
US9385070B2 (en) * | 2013-06-28 | 2016-07-05 | Delta Electronics, Inc. | Semiconductor component having a lateral semiconductor device and a vertical semiconductor device |
US9484601B2 (en) * | 2013-07-30 | 2016-11-01 | Elwha Llc | Load-managed electrochemical energy generation system |
CN103441124B (zh) * | 2013-08-27 | 2016-01-06 | 矽力杰半导体技术(杭州)有限公司 | 电压调节器的叠层封装方法及相应的叠层封装装置 |
US9570379B2 (en) * | 2013-12-09 | 2017-02-14 | Infineon Technologies Americas Corp. | Power semiconductor package with integrated heat spreader and partially etched conductive carrier |
US9704787B2 (en) | 2014-10-16 | 2017-07-11 | Infineon Technologies Americas Corp. | Compact single-die power semiconductor package |
US9620475B2 (en) | 2013-12-09 | 2017-04-11 | Infineon Technologies Americas Corp | Array based fabrication of power semiconductor package with integrated heat spreader |
US9653386B2 (en) | 2014-10-16 | 2017-05-16 | Infineon Technologies Americas Corp. | Compact multi-die power semiconductor package |
US9437589B2 (en) * | 2014-03-25 | 2016-09-06 | Infineon Technologies Ag | Protection devices |
US9859732B2 (en) | 2014-09-16 | 2018-01-02 | Navitas Semiconductor, Inc. | Half bridge power conversion circuits using GaN devices |
US10373921B2 (en) * | 2017-06-20 | 2019-08-06 | Micron Technology, Inc. | Power gate circuits for semiconductor devices |
US10784213B2 (en) * | 2018-01-26 | 2020-09-22 | Hong Kong Applied Science and Technology Research Institute Company Limited | Power device package |
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US20120280308A1 (en) | 2012-11-08 |
CN102646670A (zh) | 2012-08-22 |
US8742490B2 (en) | 2014-06-03 |
CN202601610U (zh) | 2012-12-12 |
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