CN101432874A - 包括多个管芯和一公共节点结构的半导体管芯封装 - Google Patents

包括多个管芯和一公共节点结构的半导体管芯封装 Download PDF

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CN101432874A
CN101432874A CNA2007800148492A CN200780014849A CN101432874A CN 101432874 A CN101432874 A CN 101432874A CN A2007800148492 A CNA2007800148492 A CN A2007800148492A CN 200780014849 A CN200780014849 A CN 200780014849A CN 101432874 A CN101432874 A CN 101432874A
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semiconductor element
die package
semiconductor
substrate
semiconductor die
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R·约什
V·艾耶
J·克莱因
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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Publication of CN101432874A publication Critical patent/CN101432874A/zh
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Abstract

公开了一种能安装到母板上的半导体管芯封装。该半导体管芯封装包括基板以及安装在该基板上的第一半导体管芯，其中该第一半导体管芯包括第一垂直器件，其包括位于该第一半导体管芯相反表面上的第一输入区和第一输出区。该半导体管芯封装包括安装在基板上的第二半导体管芯，其中该第二半导体管芯包括第二垂直器件，其包括位于该第二半导体管芯相反表面上的第二输入区和第二输出区。基本平面的导电节点夹使第一半导体管芯中的第一输出区与第二半导体管芯中的第二输入区电连通。第一半导体管芯和第二半导体管芯位于基板和导电节点夹之间。

Description

包括多个管芯和一公共节点结构的半导体管芯封装
发明背景
同步降压转换器用于电压调整。典型的同步降压转换器可使用控制器IC(集成电路)、高侧功率MOSFET和低侧功率MOSFET。
图1示出典型的同步降压转换器的简化电路图。同步降压转换器(SBC)10包括高侧金属氧化物半导体场效应晶体管(MOSFET)12和低侧MOSFET14。低侧MOSFET 14的漏极D与高侧MOSFET 12的源极S通过节点S电连接。PWM(脉宽调制)控制器可控制高侧MOSFET 12的栅极G和低侧MOSFET 14的栅极G。
为使SBC 10以中到高的工作/开关频率使用，SBC 10中高侧MOSFET12的源极S和低侧MOSFET 14的漏极D之间的节点连接合乎需要地具有非常低的电感。当MOSFET 12和14被配置成分立器件时，SBC 10的电路布置的设计被合乎需要地最优化以减小寄生电感。或者，SBC 10可在单个封装中的单个转换器中被配置成全集成同步降压转换器，其被设计并布置成减小高侧MOSFET 12的源极S和低侧MOSFET 14的漏极D之间的连接中的寄生电感。然而，这种全集成器件倾向于是经常与其他应用和/或设计不兼容的相当应用和/或设计特定的器件。更进一步地，连接MOSFET的印刷电路板迹线/导体通常不适于传输中到高电平的电流。
在使用常规封装的同步降压转换器中，高侧MOSFET源极通过接合线连接到低侧MOSFET漏极。这产生了高寄生电感。此外，在常规封装中，驱动器IC到高侧MOSFET和低侧MOSFET的栅极、源极和漏极的连接也使用接合线和支承MOSFET的各个管芯焊盘来执行。使用各个焊盘需要使用较长的接合线。这些因素降低了常规封装的高频功率效率和热性能。一般而言，多管芯焊盘封装具有比本发明各实施例低的封装可靠性级别。此外，一般而言，因为封装的物理大小较大多管芯焊盘器件被横向排列，从而导致较低的封装可靠性(例如，在回流/焊接/安装工艺期间对湿度敏感)。此外，常规封装散热不佳，因而期望改进这种类型的封装的散热特性。
因此，期望提供经改进的半导体管芯封装、用于制造半导体管芯封装的方法、及使用这些半导体管芯封装的电气组件。
发明概要
本发明的各实施例涉及各种半导体管芯封装，用于制造半导体管芯封装的各种方法、以及包括半导体管芯封装的各种电气组件。
本发明的一个实施例涉及半导体管芯封装。该半导体管芯封装包括基板以及安装在该基板上的第一半导体管芯，其中该第一半导体管芯包括第一垂直器件，其包括位于该第一半导体管芯相反表面上的第一输入区和第一输出区。该半导体管芯封装包括安装在基板上的第二半导体管芯，其中该第二半导体管芯包括第二垂直器件，其包括位于该第二半导体管芯相反表面上的第二输入区和第二输出区。导电节点夹使第一半导体管芯中的第一输出区(例如低侧MOSFET中的漏极区)与第二半导体管芯中的第二输入区(例如高侧MOSFET中的源极区)电连通。第一半导体管芯和第二半导体管芯位于基板和导电节点夹之间。
本发明的另一实施例涉及用于制造半导体管芯封装的方法。该方法包括将第一半导体管芯安装到基板上，其中该第一半导体管芯包括第一垂直器件，其包括位于该第一半导体管芯相反表面上的第一输入区和第一输出区。该方法还包括将第二半导体管芯安装到该基板上，其中该第二半导体管芯包括第二垂直器件，其包括位于该第二半导体管芯相反表面上的第二输入区和第二输出区。然后，导电节点夹被附连到第一半导体管芯和第二半导体管芯。该导电节点夹使第一半导体管芯中的第一输出区与第二半导体管芯中的第二输入区电连通。
本发明的又一实施例涉及用于制造能被安装到母板上的半导体管芯封装的方法，该方法包括：获得第一半导体管芯，其中该第一半导体管芯包括第一垂直器件，其包括位于该第一半导体管芯相反表面上的第一输入区和第一输出区；获得第二半导体管芯，其中该第二半导体管芯包括第二垂直器件，其包括位于该第二半导体管芯相反表面上的第二输入区和第二输出区件；将导电节点夹附连到第一半导体管芯和第二半导体管芯，其中该导电节点夹使第一半导体管芯中的第一输出区与第二半导体管芯中的第二输入区电连通；将第一半导体管芯、第二半导体管芯以及导电节点夹附连到基板；以及执行模制工艺，从而形成封装。
以下对这些及其他各实施例进行进一步详细描述。
附图简述
图1示出同步降压转换器电路的电路图。
图2(a)示出本发明一实施例的截面侧视图。
图2(b)示出包括MOSFET BGA型封装和置于导电节点夹上的未模制封装的两个子封装。
图3示出根据本发明一实施例的引线框结构的平面图。
图4示出控制器管芯安装其上的引线框结构的平面图。
图5示出具有控制器管芯、包括低侧MOSFET的第一半导体管芯和包括高侧MOSFET的第二半导体管芯的引线框结构的平面图。
图6示出控制器管芯、包括低侧MOSFET的第一半导体管芯和包括高侧MOSFET的第二半导体管芯安装其上的引线框结构的平面图。第二基板和漏极夹也在图6中示出。
图7示出图6所示的实施例，且导电节点夹附连到第二基板和漏极夹，因此附连到第一半导体管芯和第二半导体管芯。
图8示出根据本发明一实施例的模制半导体管芯封装的俯视图。
详细描述
本发明各实施例涉及半导体管芯封装及用于制造半导体管芯封装的方法。根据本发明一实施例的半导体管芯封装包括基板和安装于该基板上的第一半导体管芯，其中该第一半导体管芯包括第一垂直器件(例如低侧MOSFET)，其包括位于该第一半导体管芯相反表面上的第一输入区(例如源极区)和第一输出区(例如漏极区)。该半导体管芯封装包括安装于该基板上的第二半导体管芯。该第二半导体管芯包括第二垂直器件(例如高侧MOSFET)，其包括位于该第二半导体管芯相反表面上的第一输入区(例如源极区)和第二输出区(例如漏极区)。导电节点夹使第一半导体管芯中的第一输出区与第二半导体管芯中的第二输入区电连通。第一半导体管芯和第二半导体管芯位于基板和导电节点夹之间。制模材料可覆盖基板、第一半导体管芯和第二半导体管芯以及导电节点夹的至少一部分。该半导体管芯封装可以是独立的，且能被安装到母板上。
用在半导体管芯封装内的基板可具有任何适当的构造。在本发明各优选实施例中，基板是引线框结构形式。术语“引线框结构”可指从引线框获得的结构。引线框结构可通过例如本领域已知的冲压工艺形成。示例性引线框结构还可通过蚀刻连续导电板以形成预定图案来形成。因而，在本发明的各实施例中，半导体管芯封装中的引线框结构可以是连续的金属结构或者不连续的金属结构。
根据本发明一实施例的引线框结构可最初是以通过系杆连接在一起的引线框结构阵列中的许多引线框结构中的一个。在制造半导体管芯封装的工艺期间，引线框结构阵列可被切割以使各个引线框结构相互分离。作为此切割的结果，最终的半导体管芯封装中的引线框结构(诸如源极引线和栅极引线)的各部分可相互电气和机械去耦。在其他各实施例中，在制造根据本发明各实施例的半导体管芯封装时不使用引线框结构阵列。
根据本发明一实施例的引线框结构可包括任何适当的材料，可具有任何适当的形式，且可具有任何适当的厚度。示例性的引线框结构材料包括诸如铜、铝、金等之类的金属及其合金。引线框结构还可包括诸如金电镀层、铬电镀层、银电镀层、钯电镀层、镍电镀层等之类的电镀层。
根据本发明一实施例的引线框结构还可具有任何适当的构造。例如，引线框结构还可具有任何适当的厚度，包括小于约1mm(例如小于约0.5mm)的厚度。此外，引线框结构可具有多个可形成管芯附连焊盘(DAP)的管芯附连区。引线可横向伸出管芯附连区。它们还可具有与形成管芯附连区的表面共面和/或不共面的表面。例如，在某些实施例中，引线可相对管芯附连区向下弯曲。
如果引线框结构的引线不横向向外伸出制模材料，则可认为基板是“无引线”基板，且可认为包括该基板的封装是“无引线”封装。如果引线框结构的引线伸出制模材料，则基板可以是“有引线”基板，且封装可以是“有引线封装”。
制模材料可包括任何适当的材料。适当的制模材料包括基于联苯的材料、以及多功能交联环氧树脂复合材料。适当的制模材料以液体或半固体形式被沉积在引线框结构上，且在此后固化以使它们变硬。
安装在基板上的第一半导体管芯和第二半导体管芯可包括任何适当类型的垂直半导体器件。垂直器件至少具有在管芯一侧的输入和在该管芯另一侧的输出，以使电流可垂直地流经该管芯。在2004年12月29日提交的美国专利申请No.11/026,276中也对示例性的半导体器件进行了描述，该专利为了所有目的通过引用完全结合于此。
垂直功率晶体管包括VDMOS晶体管和垂直双极晶体管。VDMOS晶体管是具有两个或更多个通过扩散形成的半导体区的MOSFET。它具有源极区、漏极区和栅极。该器件是垂直的，因为源极区和漏极区位于半导体管芯的相反表面。栅极可以是沟槽栅极结构或平面栅极结构，且与源极区在同一表面形成。沟槽栅极结构是优选的，因为沟槽栅极结构相比平面栅极结构较窄并占据较少空间。在运行期间，VDMOS器件中从源极区流到漏极区的电流与管芯表面基本垂直。
图2(a)示出根据本发明一实施例的半导体管芯封装100的截面侧视图。该半导体管芯封装100包括引线框结构51，其包括漏极结构D1、源极结构S2、以及开关节点结构SW。以下参考图3提供关于引线框结构51的进一步细节。
第一半导体管芯22安装在引线框结构51上。第一半导体管芯22可包括在该管芯22一侧的第一输入区和在该管芯22另一侧的第二输出区。在此示例中，第一输入区可以是源极区S，而输出区可以是漏极区D。漏极区D远离引线框结构51，而源极区S靠近引线框结构51。第一半导体管芯22中的源极区S、漏极区D、以及栅极区可形成低侧MOSFET器件。低侧MOSFET器件可在同步降压转换器电路或其他电路中使用。
第一半导体管芯22的源极区S可使用焊球21与引线框结构51的源极结构S2电耦合。代替焊球21，在其他各实施例中可使用焊柱、焊材(solderlog)、导电柱和/或导电粘合剂代替。
漏极夹40通过焊料24或某些其他导电材料(例如导电粘合剂)附连到第一半导体管芯22中的漏极区D。漏极夹21可具有多个可比第一半导体管芯22的厚度长的冲压区40(a)。该冲压区40(a)可以是导电锥体的形式，且可使第一半导体管芯22中的漏极区D与引线框结构51的开关节点结构SW电连接。漏极夹40可以是单片金属，且可由诸如铜之类的导电材料制成。
可使用焊料30将第二半导体管芯32安装到引线框结构51的漏极结构D1。漏极结构D1和源极结构D2可以是引线框结构51中的两个单独的管芯附连焊盘的一部分。第二半导体管芯32的漏极区D靠近引线框结构51，而第二半导体管芯32的源极区S远离引线框结构51。第二半导体管芯32中的源极区S、漏极区D和栅极区(未示出)可以是同步降压转换器电路或其他电路中的高侧MOSFET器件的一部分。
可任选第二基板36可附连到第二半导体管芯的源极区S。如以下将进一步详细解释地，第二基板36可使第二半导体管芯32中的栅极区和源极区与引线框结构51的其他部分(未示出)电耦合。它还可使导电节点夹52与第二半导体管芯32中的源极区S电耦合。第二基板36可以是具有两个或更多个导电层和绝缘层的电路化基板，且可将源极和栅极电流传送到第二半导体管芯中的源极区S和栅极区。
导电节点夹52可包括诸如铜、铝及其合金之类的导电材料。它可具有一般的平面构造。在图2中，导电节点夹52具有阶梯式结构，且通常是平面的。该阶梯式结构提供一致形状的管芯封装。它还可分别通过焊料24和焊料34使第一半导体管芯22的漏极区D与第二半导体管芯32的源极区S电耦合。
在第一半导体管芯22和第二半导体管芯32周围模制制模材料50，且制模材料50的外表面可与导电节点夹片52的外表面基本共面。以上对适当的制模材料进行了描述。
在半导体管芯封装100中，制模材料50的外表面可与引线框结构51的表面和导电节点夹52的表面基本共面。在此示例中，引线框结构51的引线不伸出制模材料50的侧面。
为形成图2(a)所示的半导体管芯封装，可首先形成多个子封装，且可将这些子封装安装到引线框结构等以形成组件。然后可对随后形成的组件进行模制、然后切割。
作为例示，图2(b)从立体视角示出先前所述的半导体管芯封装的一些部分。在图2(a)到图2(b)中，相同的附图标记指示相同的元件，所以在此无需重复对图2(b)中元件的描述。
图2(b)示出包括两个子封装300(a)、300(b)的组件。第一子封装300(a)可称为MOSFET BGA(球栅阵列)型封装，而第二子封装300(b)可称为基于基板的未模制型封装。在某些实施例中，这些子封装可单独形成，然后被安装到导电节点夹52上。例如，可形成包括夹40和附连到夹40的带焊料隆起焊盘的第一半导体管芯22的第一子封装300(a)。在此之前或之后，可形成包括第二基板36、安装于第二基板36上的第二半导体管芯32、及附连到第二半导体管芯32的焊料202、203的第二子封装300(b)。第一子封装300(a)和第二子封装300(b)然后可安装到导电节点夹52(例如用焊料或导电粘合剂)。然后，图2(b)所示的组件可通过翻转整个组件安装到图4所示的引线框结构51上(有或没有结合控制器110)。然后，可形成模制工艺以在子封装300(a)、300(b)周围形成制模材料，且可执行切割工艺以使所形成的封装与其他封装分离。因而，此后可制造出图2(a)所示的封装。
图3到图8提供关于根据本发明各实施例的封装的各种部件的更多细节。虽然，形成封装的优选方式是形成如上所述的子封装，但是在某些情况下可组装封装的部件而不形成子封装。
图3示出根据本发明一实施例的引线框结构51的俯视图。引线框结构51包括供漏极连接到高侧MOSFET中漏极区的第一管芯附连焊盘(DAP)50(a)、以及供源极连接到低侧MOSFET中源极区的第二DAP 50(b)。还示出的有旨在分别与高侧MOSFET中的栅极区、高侧MOSFET中的源极区、以及低侧MOSFET中的栅极区耦合的附连区50(c)、50(d)、50(e)。如以下将描述的，附连区50(c)、50(d)、50(e)可用于引线接合连接。由箭头2-2形成的线通常可对应于图2(a)所示的截面图。
在图3中，多条供输入和输出到所形成封装的引线也用缩写示出。缩写可以如下：SW(开关节点)；S2(源极2)；D1(漏极1)；G1(栅极1)；S1(源极1)；C(控制器引脚)；G2(栅极2)；以及NC(无连接)。
如图4所示，控制器管芯110可安装在第二DAP 50(b)上，且最终将驻留于先前所述的带低侧MOSFET的第一半导体管芯22旁边。控制器管芯110可用来对同步降压转换器应用中的低侧MOSFET和高侧MOSFET的栅极进行控制。可购得控制器管芯110，且可使用本领域已知的任何适当的安装工艺进行安装。
多个引线接合112可用来使与控制器管芯110相关联的输入和输出与对应于G1、S1和G2的各附连区50(c)、50(d)、50(c)、以及标记为C的引线耦合。控制器管芯110优选与低侧MOSFET安装在同一DAP上，以减小来自将驻留于第一DAP 50(a)上的高侧MOSFET的开关干扰的可能性。
如图5所示，包括低侧MOSFET的第一半导体管芯22可安装到第二DAP 50(b)，以使第一半导体管芯22中的源极区面对第二DAP 50(b)，而漏极区背离第二DAP 50(b)。示出了多个焊球21，且焊球会在第二DAP 50(b)和第一半导体管芯22中的源极区之间，并会起到连接它们的作用。标记为G的单个焊球可连接到附连区50(d)、引线G2、以及引出到控制器管芯110的引线接合。
包括高侧MOSFET的第二半导体管芯32(具有源极区32(s)和栅极区32(g))可安装到第一DAP 50(a)上，以使第二半导体管芯32中的漏极区面对第一DAP 50(a)，而第二半导体管芯32中的源极区32(s)背离第一DAP50(a)。
如图6所示，第二基板36可存在于和/或安装到先前所述的第二半导体管芯32上。该第二基板36可包括使第二半导体管芯32中的高侧MOSFET中的一个或多个栅极区连接到标记为G1的附连区50(c)、并使高侧MOSFET中的一个或多个源极区附连到标记为S1的管芯附连区50(d)的电路。焊球203还可使第二基板36中的该电路连接到附连区50(d)，同时焊球202可使第二基板36中的该电路连接到附连区50(c)。第二基板36还可提供第二半导体管芯32中的源极区与上覆的导电节点夹(未示出)之间的连接。
导电夹40被示为置于第一半导体管芯22之上，并提供第一半导体管芯22的低侧MOSFET中的漏极区和先前所述的开关节点(SW)引线之间的电连接。细长的导电冲压区40(a)可提供从导电夹40的平面部分经由焊点到开关节点(SW)引线的垂直导电路径。该冲压区40(a)可比第一半导体管芯22的厚度长。
如图7所示，导电开关节点夹52可起连接第一半导体管芯22中的低侧MOSFET中的漏极区和第二半导体管芯32中的高侧MOSFET中的源极区的作用。该导电节点夹可由包括铜、铝、或其合金的任何适当的导电材料制成。
如图8所示，在开关节点夹52的侧面边缘周围模制制模材料50。因为开关节点夹52位于顶部，所以它提供所形成半导体管芯封装中改进的冷却。
根据本发明各实施例的各种半导体管芯封装可被结合入任何适当的电气组件。电气组件的示例包括蜂窝电话、个人和膝上型计算机、服务器计算机、电视机等。
本发明的各实施例具有许多优点。第一，参考图2(a)，在本发明的各实施例中，冷却可从封装100的顶部经由开关节点夹52、并且从底部经由引线框结构51发生。第二，在本发明的各实施例中，开关节点连接(开关节点夹52)包含于封装中，并且不依赖于母板。第三，控制器管芯、高侧MOSFET和低侧MOSFET可包含于单个封装中，从而对同步降压转换器提供紧凑部件。第四，因为开关节点是在封装之内，这最小化了高侧源极和低侧漏极之间连接的回路长度，从而减小了电源路径中的寄生电感。还存在更少的引线接合，从而减小了封装的电感和电阻。所有这些特性容许更高的开关频率和更高的功率密度。第五，所形成的封装可具有微引线框(MLP)型构造，且可以以常规方式安装到母板上。无需特殊的安装工艺。
上述任何实施例和/或其任何特征可与其他一个或多个实施例和/或一个或多个特征组合，而不背离本发明的范围。
以上说明书是示例性的而非限制性的。本发明的许多变体对本领域的技术人员而言是在仔细察看本发明内容后显而易见的。因此，本发明的范围不应参考以上说明来确定，而应参考所附权利要求及其全部范围或等效方案来确定。
对诸如“顶部”、“底部”、“上”、“下”等位置的任何引用参考附图，并且是为了便于例示而使用的，并不旨在是限制性的。它们并不是旨在指绝对位置。
“一”、“一个”或“该”的叙述旨在表示“一个或更多”，除非具体指定为相反情况。
上述所有专利、专利申请、出版物和说明为了所有目的通过引用完整结合于此。没有一项被认为是现有技术。

Claims (22)

1.一种能安装到母板上的半导体管芯封装，所述半导体管芯封装包括：
基板；
安装到所述基板上的第一半导体管芯，其中所述第一半导体管芯包括第一垂直器件，其包括位于所述第一半导体管芯相反表面上的第一输入区和第一输出区；
安装到所述基板上的第二半导体管芯，其中所述第二半导体管芯包括第二垂直器件，其包括位于所述第二半导体管芯相反表面上的第二输入区和第二输出区；以及
电连通所述第一半导体管芯中的第一输出区和所述第二半导体管芯中的第二输入区的导电节点夹，
其中所述第一半导体管芯和所述第二半导体管芯在所述基板和所述导电节点夹之间。
2.如权利要求1所述的半导体管芯封装，其特征在于，所述基板是引线框结构。
3.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括制模材料，其中所述制模材料覆盖所述第一半导体管芯和所述第二半导体管芯。
4.如权利要求1所述的半导体管芯封装，其特征在于，所述第一半导体管芯包括低侧MOSFET，且所述第二半导体管芯包括高侧MOSFET，且其中所述第一和第二输入区是源极区、且所述第一和第二输出区是漏极区。
5.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括安装在所述基板上的控制器管芯。
6.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括制模材料，其中所述制模材料覆盖所述第一半导体管芯和所述第二半导体管芯，且其中所述导电节点夹经由所述制模材料暴露，并具有基本上与所述制模材料的外表面基本共面的表面。
7.如权利要求1所述的半导体管芯封装，其特征在于，所述半导体管芯封装是微引线框封装(MLP)。
8.如权利要求1所述的半导体管芯封装，其特征在于，进一步包括位于所述第二半导体管芯和所述导电节点夹之间的第二基板。
9.如权利要求1所述的半导体管芯封装，其特征在于，所述第一半导体管芯、所述第二半导体管芯和所述导电节点夹形成同步降压转换器电路的各部分。
10.如权利1所述的半导体管芯封装，其特征在于，所述导电节点夹具有阶梯式结构。
11.一种包括如权利要求1所述的半导体管芯封装的电气组件。
12.一种用于制造能安装到母板的半导体管芯封装的方法，所述方法包括：
将第一半导体管芯安装到基板，其中所述第一半导体管芯包括第一垂直器件，其包括位于所述第一半导体管芯相反表面上的第一输入区和第一输出区；
将第二半导体管芯安装到所述基板，其中第二半导体管芯包括第二垂直器件，其包括位于所述第二半导体管芯相反表面上的第二输入区和第二输出区；以及
将导电节点夹附连到所述第一半导体管芯和所述第二半导体管芯，其中所述导电节点夹使所述第一半导体管芯中的所述第一输出区与所述第二半导体管芯中的所述第二输入区电连通。
13.如权利要求12所述的方法，进一步包括在所述第一半导体管芯和所述第二半导体管芯周围模制制模材料。
14.如权利要求12所述的第一半导体管芯，其特征在于，所述第二半导体管芯、所述导电节点夹形成同步降压转换器电路的一部分。
15.如权利要求12所述的方法，其特征在于，所述基板是引线框结构。
16.如权利要求12所述的方法，其特征在于，进一步包括在所述第一半导体管芯和所述第二半导体管芯周围模制制模材料，其中所述制模材料具有与所述导电节点夹的表面基本共面的外表面。
17.如权利要求12所述的方法，其特征在于，所述第一半导体管芯包括低侧MOSFET，且所述第二半导体管芯包括高侧MOSFET，且其中所述第一和第二输入区是源极区、且所述第一和第二输出区是漏极区。
18.如权利要求12所述的方法，其特征在于，在所述第一半导体管芯安装到所述基板时所述第一半导体管芯是第一子封装的一部分，且在所述第二半导体管芯安装到所述基板时所述第二半导体管芯是所述第二子封装的一部分。
19.如权利要求12所述的方法，其特征在于，所述导电节点夹包括铜。
20.如权利要求12所述的方法，其特征在于，进一步包括将控制器管芯安装到所述基板。
21.一种用于制造能安装到母板的半导体管芯封装的方法，所述方法包括：
获得第一半导体管芯，其中所述第一半导体管芯包括第一垂直器件，其包括位于所述第一半导体管芯相反表面上的第一输入区和第一输出区；
获得第二半导体管芯，其中所述第二半导体管芯包括第二垂直器件，其包括位于所述第二半导体管芯相反表面上的第二输入区和第二输出区；
将导电节点夹附连到所述第一半导体管芯和所述第二半导体管芯，其中所述导电节点夹使所述第一半导体管芯中的所述第一输出区与所述第二半导体管芯中的所述第二输入区电连通；
将所述第一半导体管芯、所述第二半导体管芯、以及所述导电节点夹附连到基板；以及
执行模制工艺，从而形成封装。
22.如权利要求21所述的方法，其特征在于，所述第一和所述第二半导体管芯在附连到所述导电节点夹之前存在于单独的子封装中。
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US20070249092A1 (en) 2007-10-25
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US7618896B2 (en) 2009-11-17
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US8212361B2 (en) 2012-07-03
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