CN105914197B - 一种采用植球工艺的小功率整流元器件及其制造方法 - Google Patents

一种采用植球工艺的小功率整流元器件及其制造方法 Download PDF

Info

Publication number
CN105914197B
CN105914197B CN201610419529.6A CN201610419529A CN105914197B CN 105914197 B CN105914197 B CN 105914197B CN 201610419529 A CN201610419529 A CN 201610419529A CN 105914197 B CN105914197 B CN 105914197B
Authority
CN
China
Prior art keywords
lead frame
chip
conducting sphere
steel mesh
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201610419529.6A
Other languages
English (en)
Other versions
CN105914197A (zh
Inventor
朱坤恒
孔凡伟
段花山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shandong Crystal Guided Microelectronic Ltd By Share Ltd
Original Assignee
Shandong Crystal Guided Microelectronic Ltd By Share Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shandong Crystal Guided Microelectronic Ltd By Share Ltd filed Critical Shandong Crystal Guided Microelectronic Ltd By Share Ltd
Priority to CN201610419529.6A priority Critical patent/CN105914197B/zh
Publication of CN105914197A publication Critical patent/CN105914197A/zh
Application granted granted Critical
Publication of CN105914197B publication Critical patent/CN105914197B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

本发明公开了一种采用植球工艺的小功率整流元器件及其制造方法，所述整流元器件包括塑封环氧树脂，塑封环氧树脂内设置有引线框架A和位于引线框架A下方的引线框架B；引线框架A的下表面焊接有芯片且芯片的正极朝下，引线框架B的上表面且对应芯片的位置设置有导电球，导电球与芯片的正极点接触以形成电流通路。本发明采用导电球的焊接工艺，导电路径更短，焊接更可靠，具有更好的导电和导热性能，提升了产品的品质；且不再使用昂贵的金丝，大大降低了原材料成本；植入的导电球与芯片是点接触，因此可生产尺寸很小的芯片，植球工艺简单、成熟，对比金属丝线焊接工艺，其生产效率可提升8倍左右。

Description

一种采用植球工艺的小功率整流元器件及其制造方法
技术领域
本发明涉及一种采用植球工艺的小功率整流元器件及其制造方法，属于半导体器件技术领域。
背景技术
小功率的二极管和整流桥半导体元器件，如：SOD123、SOD323、MB、和ABS等，芯片正极和引脚间一般有以下三种焊接连接方式：1、金属丝线焊接连接，如图2所示；2、引线框架叠加焊接的连接方式，如图1所示，其中和芯片正极接触的引线框架，通常有一个被挤压形成的凸台平面或被折弯形成的弯折平面，平面投影形状一般为规则四边形或圆形；3、跳片（Clip）焊接连接方式，跳片上也有一个和芯片正极接触的平面部分，其形成方法和引线框架叠加连接方式类似。
金属丝线焊接工艺，如SOD123和SOD523等。对小功率二极管或整流元器件来说，芯片尺寸一般小于30mil×30mil, 一般使用的是直径1mil以下的金丝焊线。虽然，近年来出现了铜丝线和银丝线，但是目前的生产工艺能力还不能提供1mil以下的铜丝线和银丝线。并且金是一种稀有贵金属，采用金丝线的焊接工艺，不仅生产原材料成本较高，而且生产工艺的效率也相对较低。
引线框架叠加和跳片焊接工艺，如：SOD123、MB、UMB等，由于引线框架冲压制造工艺的局限性，和芯片正极接触的平面（凸台平面或弯折平面），其长和宽或直径尺寸不能小于0.3mm，否则，加工难度非常大，品质很不稳定，因此，采用引线框架叠加和跳片焊接工艺的生产企业，无法生产出高品质高良率30mil×30mil以下小尺寸芯片的产品。30mil×30mil的芯片，其正极有效焊接区域的长和宽非常接近0.3mm，如果与芯片正极接触的平面的长和宽或直径为0.3mm，那么与芯片接触的引线框架平面很容易接触到芯片边缘的保护层，严重影响半导体元器件的品质。对比金属丝线焊接工艺，虽然引线框架叠加和跳片焊接工艺生产设备比较简单，生产效率较高，但很难生产小尺寸芯片的二极管和整流桥半导体器件，这就是小功率二极管几乎都采用金属丝焊接工艺的原因。
发明内容
本发明为了克服以上技术的不足，提供了一种采用植球工艺的小功率整流元器件，本发明所述小功率整流元器件是指整流元器件的芯片尺寸小于等于30mil×30mil。本发明还提供了一种上述整流元器件的制造方法。
本发明克服其技术问题所采用的技术方案是：
一种采用植球工艺的小功率整流元器件，包括塑封环氧树脂，塑封环氧树脂内设置有引线框架A和位于引线框架A下方的引线框架B；引线框架A的下表面焊接有芯片且芯片的正极朝下，引线框架B的上表面且对应芯片的位置设置有导电球，导电球与芯片的正极点接触以形成电流通路。
优选的，所述引线框架B的上表面通过设置一球冠状凹坑或通孔以固定导电球。
一种上述整流元器件的制造方法，包括如下步骤：
S1、固定芯片：在所有引线框架A与芯片焊接的芯片焊接面上沾涂上焊料；将芯片放置于沾涂有焊料的芯片焊接面上，芯片正极朝上，使得芯片固定于引线框架A上；
S2、植球：在所有引线框架B的导电球焊接面上沾涂上焊料或助焊剂；然后采用钢网将导电球植入沾涂有焊料或助焊剂的导电球焊接面上，使得导电球固定于引线框架B上；
S3、组装：将引线框架B平放于定位治具上，然后将引线框架A翻转，按照设定的对应位置，将引线框架A放置于引线框架B上；
S4、焊接：将载有引线框架A和引线框架B的定位治具送入回流炉中，使引线框架A和引线框架B焊接在一起；
S5、塑封：将步骤S4中已焊接在一起的引线框架A和引线框架B进行塑封成型；
S6、电镀；
S7、切筋：按照规定的尺寸要求，将塑封成型后的整流元器件切筋分离。
优选的，所述步骤S1和S2中，焊料采用锡膏。
优选的，所述步骤S2之前，在引线框架B的导电球焊接面上加工球冠状凹坑或通孔以固定导电球。
优选的，所述步骤S2中，采用钢网将导电球植入沾涂有焊料或助焊剂的导电球焊接面上的具体过程包括：
制造一个与引线框架B匹配的钢网，钢网上设置有若干个开孔，开孔的尺寸略大于导电球的直径；
将钢网放置在已沾涂好焊料或助焊剂的引线框架B的上方，使钢网与引线框架B之间的距离≤导电球的直径；
将导电球撒在钢网上，用刮刀把导电球拨到钢网的开孔内，使钢网的每个开孔中都有一个导电球；
移开钢网，导电球被固定在引线框架B的导电球焊接面上。
本发明的有益效果是：
1、本发明突破了支架冲压凸点尺寸的限制，支架冲压凸点的长和宽或直径的最小尺寸为0.3mm左右，如再要生产更小尺寸的凸点，工艺将很不稳定，加工难度非常大，尺寸和品质也很难保证。
2、对比金属丝线焊接工艺，本发明植入导电球，使得导电路径更短，焊接更可靠，具有更好的导电和导热性能，提升了产品的品质；且不再使用昂贵的金丝，大大降低了原材料成本。
3、本发明植入的导电球与芯片是点接触，因此可生产尺寸很小的芯片，植球工艺简单、成熟，对比金属丝线焊接工艺，其生产效率可提升8倍左右。
附图说明
图1是现有技术中采用引线框架叠加焊接工艺制造的整流元器件的结构示意图。
图2是现有技术中采用金属丝线焊接工艺制造的整流元器件的结构示意图。
图3是本发明采用植球焊接工艺制造的整流元器件的结构示意图。
图4是本发明实施例2中引线框架A上沾涂焊料后的结构示意图。
图5是本发明实施例2中引线框架A上固定芯片后的结构示意图。
图6是本发明实施例2中引线框架B上沾涂焊料后的结构示意图。
图7是本发明实施例2中引线框架B上植入导电球后的结构示意图。
图中，1、引线框架A，2、引线框架B，3、塑封环氧树脂，4、芯片，5、焊料，6、凸点，7、金属丝线，8、导电球，11、芯片焊接面，21、导电球焊接面，22、凹坑或通孔。
具体实施方式
为了便于本领域人员更好的理解本发明，下面结合附图和具体实施例对本发明做进一步详细说明，下述仅是示例性的不限定本发明的保护范围。
实施例1、
如图3所示，本发明采用植球工艺的小功率整流元器件，包括塑封环氧树脂3，塑封环氧树脂3内设置有引线框架A 1和位于引线框架A下方的引线框架B 2；引线框架A 1的下表面焊接有芯片4且芯片的正极朝下，引线框架B 2的上表面且对应芯片的位置设置一球冠状凹坑或通孔22以固定导电球8，导电球8与芯片4的正极点接触以形成电流通路。
实施例2、
一种如实施例1所述的小功率整流元器件的制造方法，包括步骤如下：
S1、固定芯片：在所有引线框架A 1与芯片焊接的芯片焊接面11上沾涂上焊料5，如图4所示，所述焊料5采用锡膏；将芯片4放置于沾涂有焊料的芯片焊接面11上，芯片正极朝上，如图5所示，使得芯片4固定于引线框架A 1上。
S2、植球：
植球之前，在引线框架B 2的导电球焊接面21上加工球冠状凹坑或通孔22以固定导电球，如图7所示；
在所有引线框架B 2的导电球焊接面21上沾涂上焊料5或助焊剂，如图6所示，所述焊料5采用锡膏；
制造一个与引线框架B 2匹配的钢网，钢网上设置有若干个开孔，开孔的尺寸略大于导电球8的直径；
将钢网放置在已沾涂好焊料或助焊剂的引线框架B 2的上方，使钢网与引线框架B之间的距离≤导电球的直径；
将导电球8撒在钢网上，用刮刀把导电球拨到钢网的开孔内，使钢网的每个开孔中都有一个导电球；
移开钢网，导电球落入引线框架B 2的导电球焊接面21的球冠状凹坑或通孔22内，如图7所示，完成导电球的植入。
S3、组装：将引线框架B 2平放于定位治具上，然后将引线框架A 1翻转，按照设定的对应位置，将引线框架A 1放置于引线框架B 2上。
S4、焊接：将载有引线框架A 1和引线框架B 2的定位治具送入回流炉中，使引线框架A 1和引线框架B 2焊接在一起。
S5、塑封：将步骤S4中已焊接在一起的引线框架A 1和引线框架B 2进行塑封成型。
S6、电镀。
S7、切筋：按照规定的尺寸要求，将塑封成型后的整流元器件切筋分离，完成小功率整流元器件的整个制造过程。
以上仅描述了本发明的基本原理和优选实施方式，本领域人员可以根据上述描述作出许多变化和改进，这些变化和改进应该属于本发明的保护范围。

Claims (6)

1.一种采用植球工艺的小功率整流元器件，其特征在于，包括塑封环氧树脂（3），塑封环氧树脂（3）内设置有引线框架A（1）和位于引线框架A（1）下方的引线框架B（2）；引线框架A（1）的下表面焊接有芯片（4）且芯片的正极朝下，引线框架B（2）的上表面且对应芯片的位置设置有导电球（8），导电球（8）与芯片（4）的正极点接触以形成电流通路。
2.根据权利要求1所述的整流元器件，其特征在于，所述引线框架B（2）的上表面通过设置一球冠状凹坑或通孔（22）以固定导电球（8）。
3.根据权利要求1或2所述的整流元器件的制造方法，其特征在于，包括如下步骤：
S1、固定芯片：在所有引线框架A（1）与芯片焊接的芯片焊接面（11）上沾涂上焊料（5）；将芯片（4）放置于沾涂有焊料的芯片焊接面（11）上，芯片正极朝上，使得芯片（4）固定于引线框架A（1）上；
S2、植球：在所有引线框架B（2）的导电球焊接面（21）上沾涂上焊料（5）或助焊剂；然后采用钢网将导电球（8）植入沾涂有焊料（5）或助焊剂的导电球焊接面（21）上，使得导电球（8）固定于引线框架B（2）上；
S3、组装：将引线框架B（2）平放于定位治具上，然后将引线框架A（1）翻转，按照设定的对应位置，将引线框架A（1）放置于引线框架B（2）上；
S4、焊接：将载有引线框架A（1）和引线框架B（2）的定位治具送入回流炉中，使引线框架A（1）和引线框架B（2）焊接在一起；
S5、塑封：将步骤S4中已焊接在一起的引线框架A（1）和引线框架B（2）进行塑封成型；
S6、电镀；
S7、切筋：按照规定的尺寸要求，将塑封成型后的整流元器件切筋分离。
4.根据权利要求3所述的制造方法，其特征在于，所述步骤S1和S2中，焊料（5）采用锡膏。
5.根据权利要求3所述的制造方法，其特征在于，所述步骤S2之前，在引线框架B（2）的导电球焊接面（21）上加工球冠状凹坑或通孔（22）以固定导电球。
6.根据权利要求3所述的制造方法，其特征在于，所述步骤S2中，采用钢网将导电球（8）植入沾涂有焊料（5）或助焊剂的导电球焊接面（21）上的具体过程包括：
制造一个与引线框架B（2）匹配的钢网，钢网上设置有若干个开孔，开孔的尺寸略大于导电球（8）的直径；
将钢网放置在已沾涂好焊料或助焊剂的引线框架B（2）的上方，使钢网与引线框架B之间的距离≤导电球的直径；
将导电球（8）撒在钢网上，用刮刀把导电球拨到钢网的开孔内，使钢网的每个开孔中都有一个导电球；
移开钢网，导电球被固定在引线框架B（2）的导电球焊接面（21）上。
CN201610419529.6A 2016-06-14 2016-06-14 一种采用植球工艺的小功率整流元器件及其制造方法 Active CN105914197B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610419529.6A CN105914197B (zh) 2016-06-14 2016-06-14 一种采用植球工艺的小功率整流元器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610419529.6A CN105914197B (zh) 2016-06-14 2016-06-14 一种采用植球工艺的小功率整流元器件及其制造方法

Publications (2)

Publication Number Publication Date
CN105914197A CN105914197A (zh) 2016-08-31
CN105914197B true CN105914197B (zh) 2018-09-04

Family

ID=56751340

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610419529.6A Active CN105914197B (zh) 2016-06-14 2016-06-14 一种采用植球工艺的小功率整流元器件及其制造方法

Country Status (1)

Country Link
CN (1) CN105914197B (zh)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205680678U (zh) * 2016-06-14 2016-11-09 山东晶导微电子有限公司 一种植入导电球结构的小功率整流元器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101091896B1 (ko) * 2004-09-04 2011-12-08 삼성테크윈 주식회사 플립칩 반도체 패키지 및 그 제조방법
US7618896B2 (en) * 2006-04-24 2009-11-17 Fairchild Semiconductor Corporation Semiconductor die package including multiple dies and a common node structure
CN103503132B (zh) * 2011-06-09 2016-06-01 三菱电机株式会社 半导体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN205680678U (zh) * 2016-06-14 2016-11-09 山东晶导微电子有限公司 一种植入导电球结构的小功率整流元器件

Also Published As

Publication number Publication date
CN105914197A (zh) 2016-08-31

Similar Documents

Publication Publication Date Title
US9305889B2 (en) Leadless integrated circuit package having standoff contacts and die attach pad
CN101335217B (zh) 半导体封装件及其制法
CN104779220A (zh) 一种芯片封装结构及其制造方法
KR20070074489A (ko) 반도체 장치 및 그 제조 방법
CN102165582A (zh) 引线框基板及其制造方法以及半导体装置
CN110473853A (zh) 一种dfn器件的封装结构、无引线框架载体及dfn器件的封装方法
JP2015170822A (ja) 半導体装置及びその製造方法
US9362254B1 (en) Wire bonding method and chip structure
JP2000252388A (ja) 半導体デバイスとその製法
CN104409370B (zh) 一种钉头凸点芯片的倒装装片方法及施加装片压力的方法
CN105914197B (zh) 一种采用植球工艺的小功率整流元器件及其制造方法
US10645807B1 (en) Component attach on metal woven mesh
CN108183091A (zh) 一种封装结构及其工艺方法
CN205680678U (zh) 一种植入导电球结构的小功率整流元器件
TW200849419A (en) Semiconductor package and method for fabricating the same
US20050266611A1 (en) Flip chip packaging method and flip chip assembly thereof
JP2000252389A (ja) はんだボールを模擬する隆起部を有する集積回路及びその製造方法
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN105355567B (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
TWI661509B (zh) 晶片封裝方法及晶片封裝結構
CN105448871B (zh) 功率半导体器件及制备方法
CN104538377A (zh) 一种基于载体的扇出封装结构及其制备方法
CN103441116A (zh) 一种半导体封装件及其制造方法
CN100459123C (zh) 堆叠型芯片封装结构、芯片封装体及其制造方法
CN206412355U (zh) 一种活动顶针内绝缘封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 273100 Taiwan City Industrial Park, Qufu City, Jining, Shandong.

Applicant after: Shandong crystal guided microelectronic Limited by Share Ltd

Address before: 273100 Taiwan City Industrial Park, Qufu City, Jining, Shandong.

Applicant before: Shandong Jing Dao Microtronics A/S

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant