TWI765334B - 具有集成電感器的功率半導體封裝及其製造方法 - Google Patents

具有集成電感器的功率半導體封裝及其製造方法 Download PDF

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TWI765334B
TWI765334B TW109130126A TW109130126A TWI765334B TW I765334 B TWI765334 B TW I765334B TW 109130126 A TW109130126 A TW 109130126A TW 109130126 A TW109130126 A TW 109130126A TW I765334 B TWI765334 B TW I765334B
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conductive material
metal clip
side fet
power semiconductor
semiconductor package
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TW109130126A
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TW202125730A (zh
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曉天 張
瑪麗•簡•Ｒ 阿琳
陳波
大衛•布裏安 小奧拉博尼
隆慶 王
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加拿大商萬國半導體國際有限合夥公司
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Abstract

一種功率半導體封裝包括一個引線框、一個低端場效電晶體(FET)、一個高端FET、一個第一金屬夾、一個第二金屬夾、一個電感器組件以及一個模塑封裝。低端FET翻轉並連接到引線框的第一晶片焊盤上。一種功率半導體封裝的製備方法。該方法包括以下步驟：製備一個引線框；將低端FET和高端FET連接到引線框上；安裝第一金屬夾和第二金屬夾；安裝一個電感器；製備一個模塑封裝；並且使用切單工藝。

Description

具有集成電感器的功率半導體封裝及其製造方法
本發明主要涉及一種半導體封裝及其製造方法。更確切地說，本發明涉及一種具有集成電感器的驅動金屬-氧化物-矽電晶體(DrMOS)。
傳統的DrMOS在DrMOS封裝外部具有一個電感器。圖2所示的Yin等人的美國專利號10、111和333，在切換電源模組中具有一個電感器。本發明說明書在DrMOS封裝中具有一個集成的電感器。本發明還使用金屬夾互連，以便降低電子噪聲，並增大散熱。
本發明所述的功率半導體封裝包括一個控制器、兩個場效電晶體(FET)以及一個電感器。由於集成了電感器，其優點包括更小的外形尺寸、更好的散熱和更高的電效率。透過集成方法，針對驅動器和FET動態性能、系統電感和功率FET RDS(ON)，優化了完整的開關功率級。
本發明提出了一種半導體封裝，包括一個引線框、一個低端場效電晶體(FET)、一個高端FET、一個第一金屬夾、一個第二金屬夾、一個電感器組件以及一個模塑封裝。低端FET翻轉並連接到引線框架的第一晶片焊盤上。
本發明還公開了一種用於製造功率半導體封裝的方法。該方法包括提供引線框的步驟；將低端FET和高端FET附接到引線框架；安裝第一金屬夾和第二金屬夾；安裝電感器；形成模制封裝；並應用切單工藝。
100:功率半導體封裝
120:引線框
140:低端FET
140D:汲電極
140G:閘電極
140S:源電極
150:高端FET
150G:閘電極
150S:源電極
160:第一金屬夾
167:升高部分
170:第二金屬夾
177:升高部分
180:電感器組件
181:線圈
182:第一引線
184:第二引線
190:模塑封裝
201:第一導電材料
202:第二導電材料
203:第三導電材料
204:第四導電材料
205:第五導電材料
206:第六導電材料
300:DrMOS的電路圖
302:子封裝
310:控制器
326:VSWH端口
328:Vout端口
330:電感器
340:低端FET
350:高端FET
370:電容器
400:製備工藝
402:區塊
404:區塊
406:區塊
408:區塊
410:區塊
412:區塊
414:區塊
522:第一晶片焊盤
524:第二晶片焊盤
526:第一終端焊盤
528:第二終端焊盤
531:功率半導體封裝
533:功率半導體封裝
551:線
591:積體電路(IC)
593:連接引線
595:引線
圖1表示在本發明的示例中，一種半導體封裝的透視圖。
圖2表示在本發明的示例中，圖1所示的功率半導體封裝的剖面圖。
圖3表示在本發明的示例中，一種DrMOS的電路圖。
圖4表示在本發明的示例中，製造一種功率半導體封裝工藝的流程圖。
圖5A、5B、5C、5D、5E和5F表示在本發明的示例中，製造功率半導體封裝工藝的步驟。
圖1表示在本發明的示例中，功率半導體封裝100的透視圖。圖2表示沿圖1的AA’線，功率半導體封裝100的剖面圖。功率半導體封裝100包括一個引線框120、一個低端場效電晶體(FET)140、一個圖5B所示的高端FET 150、一個第一金屬夾160、一個第二金屬夾170、一個電感器組件180以及一個模塑封裝190。引線框120包括一個圖5A所示的第一晶片焊盤522、一個第二晶片焊盤524、一個第一終端焊盤526以及一個第二終端焊盤528。第一終端焊盤526電連接到圖3所示的開關節點VSWH端口326上。第二終端焊盤528電連接到圖3所示的 Vout端口328上。
低端FET 140被翻轉並被連接到第一晶片焊盤522。導電FET 140包括在低端FET 140的頂表面上的源電極140S和閘電極140G。高端FET 150被連接在第二晶片焊盤524上。高端FET 150包括一個圖5B所示的源電極150S，以及一個在高端FET 150頂面上的閘電極150G。
第一金屬夾160將低端FET 140的汲極140D以及高端FET 150中圖5B所示的源電極150S，連接到引線框120中圖5A所示的第一終端焊盤526上。第二金屬夾170安裝在引線框架120的圖5A所示的第二終端焊盤528上。
電感器組件180包括一個線圈181；一個連接到第一金屬夾160上的第一引線182；以及一個連接到第二金屬夾170上的第二引線184。
模塑封裝190封裝了低端FET 140、高端FET 150、第一金屬夾160、第二金屬夾170、電感器組件180以及引線框120的絕大部分。在本發明的示例中，引線框120的底面暴露於模塑封裝190。
在本發明的示例中，第一金屬夾160透過第一導電材料201，電子地並機械地連接到低端FET 140的汲電極140D上。第一金屬夾160透過圖5C所示的第二導電材料202(如圖中虛線所示)，電子地並機械地連接到高端FET 150的源電極150S上。第一金屬夾160透過第三導電材料203，電子地並機械地連接到引線框120的第一終端焊盤526上。第二金屬夾170透過第四導電材料204，電子地並機械地連接到引線框120的第二終端焊盤528上。在本發明的示例中，第一導電材料201由一種焊錫膏材料製成。第二導電材料202由一種焊錫膏材料製成。第三導電材料203由一種焊錫膏材料製成。第四導電材料204由一種焊錫膏材料製成。
在本發明的示例中，第一金屬夾160包括一個升高部分167。電感器組件180的第一引線182透過第五導電材料205，電子地並機械地連接到第一金屬夾160的升高部分167上。電感器組件180的第二引線184透過第六導電材料206，電子地並機械地連接到第二金屬夾170的升高部分177上。
在本發明的示例中，第五導電材料205和第六導電材料206的每一種導電材料都是由透過混合燒結工藝實現的粉末冶金材料製成的。
在本發明的示例中，第五導電材料205和第六導電材料206的每一種導電材料都是由一種彈性體材料製成的。
在本發明的示例中，第五導電材料205和第六導電材料206的每一種導電材料都是由一種環氧材料製成的。
在本發明的示例中，積體電路(IC)591安裝在引線框120上。多個連接引線593將IC 591連接到引線框120的多個引線595上。
圖3表示在本發明的示例中，一種DrMOS的電路圖300。該DrMOS包括一個子封裝302、一個電感器330以及多個電容器370。子封裝302包括一個控制器310、一個低端FET 340以及一個高端FET 350。
圖4表示在本發明的示例中，一種功率半導體封裝的製備工藝400的流程圖。工藝400從區塊402開始。為了簡便，圖5F的虛線中的右側部分(與實線中相應的左側部分一樣)並沒有表示在圖5A、5B、5C、5D和5E中。
在區塊402中，參見圖5A，提供了一個引線框120。引線框120包括一個第一晶片焊盤522、一個第二晶片焊盤524、一個第一終端焊盤526以及一個第二終端焊盤528。區塊402之後是區塊404。
在區塊404中，參見圖5A，低端FET 140翻轉並連接到第一晶片焊盤522上。低端FET 140包括一個圖2所示的源電極140S以及一個在低端FET 140頂面上的如圖2所示的閘電極140G。高端FET 150連接到第二晶片焊盤524上。高端FET 150包括一個源電極150S以及一個在高端FET 150頂面上的閘電極150G。區塊404之後是區塊406。
在區塊406中，如圖5C所示，第一金屬夾160將低端FET 140中如圖2所示的汲電極140D以及高端FET 150中圖5B所示的源電極150S，連接到引線框120的第一終端焊盤526上。第二金屬夾170安裝在引線框120的第二終端焊盤528上。
第一金屬夾160透過圖2所示的第一導電材料201，電子地並機械地連接到低端FET 140中圖2所示的汲電極140D上。第一金屬夾160透過第二導電材料(如圖中虛線所示)，電子地並機械地連接到高端FET 150中圖5B所示的源電極150S上。第一金屬夾160透過圖2所示的第三導電材料203，電子地並機械地連接到引線框120的第一終端焊盤526上。第二金屬夾170透過圖2所示的第四導電材料204，電子地並機械地連接到引線框120的第二終端焊盤528上。在本發明的示例中，第一導電材料201由一種焊錫膏材料製成。第二導電材料202由一種焊錫膏材料製成。第三導電材料203由一種焊錫膏材料製成。第四導電材料204由一種焊錫膏材料製成。在本發明的示例中，焊錫膏材料含有鉛(Pb)。焊錫膏材料的回流溫度高於兩百攝氏度。區塊406之後是區塊408。
在區塊408中，參見圖5D，積體電路(IC)591安裝在引線框120上。多個連接引線593將IC 591連接到引線框120的多個引線595上。區塊408之後是區 塊410。
在區塊410中，參見圖5E，電感器組件180安裝在圖5C所示的第一金屬夾160和第二金屬夾170上。電感器組件180包括一個圖2所示的線圈181；一個連接到圖5C所示第一金屬夾160的第一引線182；以及一個連接到第二金屬夾170上的第二引線184。
第一金屬夾160包括一個圖2所示的升高部分167。電感器組件180的第一引線182透過圖2所示的第五導電材料205(第一個所選的導電材料)，電子地並機械地連接到第一金屬夾160中圖2所示的升高部分167上。第二金屬夾170包括一個圖2所示的升高部分177。電感器組件180的第二引線184透過圖2所示的第六導電材料206(第二個所選的導電材料)，電子地並機械地連接到第二金屬夾170中圖2所示的升高部分177上。
在本發明的示例中，第五導電材料205(第一個所選的導電材料)以及第六導電材料206(第二個所選的導電材料)中的每種導電材料都包括一個透過混合燒結工藝實現的粉末冶金材料，在195攝氏度至205攝氏度的溫度範圍內實現的。
在本發明的示例中，第五導電材料205(第一個所選的導電材料)以及第六導電材料206(第二個所選的導電材料)中的每種導電材料都包括一個彈性體材料，在75攝氏度至85攝氏度的溫度範圍內實現的。
在本發明的示例中，第五導電材料205(第一個所選的導電材料)以及第六導電材料206(第二個所選的導電材料)中的每種導電材料都包括一個環氧材料，在170攝氏度至180攝氏度的溫度範圍內實現的。區塊410之後是區塊 412。
在區塊412中，參見圖1，形成模塑封裝190。模塑封裝190封裝了低端FET 140、高端FET 150、第一金屬夾160、第二金屬夾170、電感器組件180以及引線框120的絕大部分。在本發明的示例中，引線框120的底面暴露於模塑封裝190。區塊412之後是區塊414。
在區塊414中，參見圖5F，沿551線進行切單工藝。將功率半導體封裝531與鄰近的功率半導體封裝533(如圖中虛線所示)分開。雖然圖5F中僅表示出了兩個功率半導體封裝。但是同一個切單工藝中切分的功率半導體封裝的數量可以有所不同。
本領域的普通技術人員可以理解，本發明公開的實施例的修改是可能的。例如，第二金屬夾170的升高部分177的高度可能變化。本領域普通技術人員還可以想到其他修改，並且所有這樣的修改被認為屬於本發明的範圍之內，如同發明申請專利範圍所限定的那樣。
100:功率半導體封裝
120:引線框
160:第一金屬夾
170:第二金屬夾
180:電感器組件
182:第一引線
184:第二引線
190:模塑封裝
591:積體電路(IC)
593:連接引線
595:引線

Claims (8)

  1. 一種功率半導體封裝，包括：一個引線框，包括一個第一晶片焊盤；一個第二晶片焊盤；一個第一終端焊盤；以及一個第二終端焊盤；一個低端場效電晶體(FET)翻轉並連接到第一晶片焊盤上，低端FET包括一個源電極以及一個閘電極，在低端FET的頂面上；一個連接到第二晶片焊盤上的高端FET，高端FET包括一個源電極和一個閘電極，在高端FET的頂面上；一個第一金屬夾，將低端FET的汲電極以及高端FET的源電極連接到引線框的第一終端焊盤上；一個第二金屬夾，安裝在引線框的第二終端焊盤上；一個電感器組件，包括：一個連接到第一金屬夾的第一引線；以及一個連接到第二金屬夾的第二引線；以及一個模塑封裝，封裝了低端FET、高端FET、第一金屬夾、第二金屬夾、電感器組件以及引線框的大部分：其中第一金屬夾包括一個升高部分；其中電感器組件的第一引線透過第五導電材料，電子地並機械地連接到第一金屬夾的升高部分； 其中第二金屬夾包括一個升高部分；並且其中電感器組件的第二引線透過第六導電材料，電子地並機械地連接到第二金屬夾的升高部分。
  2. 如請求項1所述之功率半導體封裝，其中第一金屬夾透過第一導電材料，電子地並機械地連接到低端FET的汲電極；其中第一金屬夾透過第二導電材料，電子地並機械地連接到高端FET的源電極；其中第一金屬夾透過第三導電材料，電子地並機械地連接到引線框的第一終端焊盤；以及其中第二金屬夾透過第四導電材料，電子地並機械地連接到引線框的第二終端焊盤。
  3. 如請求項2所述之功率半導體封裝，其中第一導電材料、第二導電材料、第三導電材料以及第四導電材料中的每種導電材料都是由一種焊錫膏材料製成。
  4. 如請求項1所述之功率半導體封裝，其中第五導電材料和第六導電材料中的每種導電材料都是由一種粉末冶金材料製成。
  5. 如請求項1所述之功率半導體封裝，其中第五導電材料和第六導電材料中的每種導電材料都是由一種彈性體材料製成。
  6. 如請求項1所述之功率半導體封裝，其中第五導電材料和第六導電材料中的每種導電材料都是由一種環氧材料製成。
  7. 如請求項1所述之功率半導體封裝，其中引線框的底面暴露於模塑封裝。
  8. 如請求項1所述之功率半導體封裝，還包括一個安裝在引線框上的積體電路(IC)，其中多個接合引線將IC連接到引線框的多個引線上。
TW109130126A 2019-09-18 2020-09-03 具有集成電感器的功率半導體封裝及其製造方法 TWI765334B (zh)

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