TWI751678B - 具有集成電感器，電阻器和電容器的功率半導體封裝 - Google Patents

具有集成電感器，電阻器和電容器的功率半導體封裝 Download PDF

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TWI751678B
TWI751678B TW109130130A TW109130130A TWI751678B TW I751678 B TWI751678 B TW I751678B TW 109130130 A TW109130130 A TW 109130130A TW 109130130 A TW109130130 A TW 109130130A TW I751678 B TWI751678 B TW I751678B
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die pad
pad
side fet
power semiconductor
semiconductor package
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TW109130130A
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TW202125731A (zh
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曉天 張
瑪麗•簡•Ｒ 阿琳
陳波
大衛•布裏安 小奧拉博尼
隆慶 王
健 印
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萬國半導體國際有限合夥公司
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Priority claimed from US16/575,193 external-priority patent/US20210082790A1/en
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Abstract

一種功率半導體封裝包括一個引線框、一個低端場效電晶體(FET)、一個高端FET、一個電容器、一個電阻器、一個電感器組件、第一種多個接合引線以及一個模塑封裝。在一個示例中，整個電感器組件放置在高於整個低端FET、高於整個高端FET以及高於整個第一種接合引線的位置上。在另一個示例中，低端FET的底面和電感器組件的底面是共面的。

Description

具有集成電感器，電阻器和電容器的功率半導體封裝
本專利申請是2019年9月18日提交的待决申請16/575,193的部分繼續申請(CIP)。專利申請16/575,193中的公開內容通過引用合併於此，以作參考。
本發明主要涉及一種半導體封裝及其製造方法。更確切地說，本發明涉及一種具有一個集成的電感器、一個集成的電容器以及一個集成的電阻器的驅動金屬-氧化物-矽電晶體(DrMOS)。
傳統的DrMOS在DrMOS封裝外部具有一個電感器。圖2所示的Yin等人的美國專利號10,111,333，在DrMOS封裝中具有一個集成的電感器、一個集成的電容器以及一個集成的電阻器。本發明沒有使用金屬夾片。在一個示例中，封裝的尺寸從7毫米×7毫米×5毫米縮小至6毫米×6毫米×5毫米。電流從20-60安培降至小於10安培。
本發明所述的功率半導體封裝包括一個控制器、兩個場效電晶體(FET)以及一個集成的電感器、一個集成的電容器以及一個集成的電阻器。由於集成了電感器，其優點包括更小的外形尺寸、更好的散熱和更高的電效率。通過集成方法，針對驅動器和FET動態性能、系統電感和功率FET RDS(ON)，優化了完整的開關功率級。
本發明提出了一種功率半導體封裝，包括一個引線框、一個低端場效電晶體(FET)、一個高端FET、一個電容器、一個電阻器、一個電感器組件、多個接合引線以及一個模塑封裝。
在一個示例中，整個電感器組件都放置在高於整個低端FET、高於整個高端FET並且高於第一種多個接合引線的位置上。在另一個示例中，低端FET的底面和電感器組件的底面是共面的。
100:電路圖
102:子封裝
110:控制器
126:VSWH端口
128:Vout端口
130:電感器
140:低端FET
150:高端FET
170:電容器
180:電阻器
200:功率半導體封裝
220:引線框
222:第一個晶片焊盤
224:第二個晶片焊盤
226:第一個末端焊盤
228:第二個末端焊盤
231:第一引線
233:第一升高部分
235:第一導電材料
240:低端FET
240G:閘電極
240S:源電極
241:第二引線
243:第二升高部分
245:第二導電材料
250:高端FET
250S:源電極
250G:閘電極
260:電容器
270:電阻器
280:電感器組件
290:模塑封裝
291:接合引線
298:接合引線
299:積體電路
300:功率半導體封裝
320:引線框
322:第一晶片焊盤
324:第二晶片焊盤
326:第一末端焊盤
335:第一導電材料
340:低端FET
340G:閘電極
340S:源電極
341:底面
345:第二導電材料
350:高端FET
350G:閘電極
350S:源電極
360:電容器
370:電阻器
380:電感器組件
381:底面
390:模塑封裝
391:接合引線
398:接合引線
399:積體電路
圖1表示在本發明的示例中，一種DrMOS的電路圖。
圖2A和圖2B分別表示在本發明的示例中，功率半導體封裝沿AA’線的俯視圖和剖面圖。
圖3A和圖3B分別表示在本發明的示例中，功率半導體封裝沿BB’線的俯視圖和剖面圖。
在本發明的示例中，圖1表示一種DrMOS的電路圖100。該DrMOS包括一個子封裝102。子封裝102包括一個控制器110、一個電感器130、一個低端FET 140、一個高端FET 150、多個電容器170以及多個電阻器180。
圖2A和圖2B分別表示在本發明的示例中，功率半導體封裝200沿AA’線的俯視圖和剖面圖。該功率半導體封裝200包括一個引線框220、一個低端 場效電晶體(FET)240、一個高端FET 250、一個電容器260、一個電阻器270、一個電感器組件280、第一種多個接合引線291以及一個模塑封裝290。引線框220包括一個第一個晶片焊盤222、一個在第一個晶片焊盤222附近的第二個晶片焊盤224、一個在第一個晶片焊盤222和第二個晶片焊盤224附近的第一個末端焊盤226、以及一個在第一個晶片焊盤222和第二個晶片焊盤224附近但又通過第一個晶片焊盤222和第二個晶片焊盤224與第一個末端焊盤226分隔開的第二個末端焊盤228。第一個末端焊盤226電連接到第一個晶片焊盤222，並作為圖1所示的開關節點VSWH端口126。第二個末端焊盤228與引線框的其他部分電絕緣，並作為圖1所示的Vout端口128。第一個末端焊盤226和第二個末端焊盤228放置在高於第一個晶片焊盤222和第二個晶片焊盤224的位置上。
低端FET240具有一個底面汲電極，連接到第一個晶片焊盤222上。低端FET 240包括一個源電極240S和一個閘電極240G，在低端FET 240的頂面上。高端FET 250具有一個底面汲電極，連接到第二個晶片焊盤224上。高端FET 250包括一個源電極250S和一個閘電極250G，在高端FET的頂面上。第一種多個接合引線291將高端FET 250的頂面源電極連接到第一個晶片焊盤222上。
引線框的第一引線231電連接到電感器組件280的第一端口上，並且堆棧在第一個晶片焊盤226上。引線框的第二引線241連接到電感器組件280的第二端口上，並且堆棧在第二個晶片焊盤228上。第一引線231包括一個第一升高部分233，在第一個晶片焊盤222和第二個晶片焊盤224上方。第二引線241包括一個第二升高部分243，在第一個晶片焊盤222和第二個晶片焊盤224上方。至少一部分第一升高部分233構成第一個晶片焊盤226，至少一部分第二升高部分243構成第二個晶片焊盤228。第一引線231的第一升高部分233通過第一導電材料235， 電子地並機械地連接到電感器組件280上。第二引線241的第二升高部分243通過第二導電材料245，電子地並機械地連接到電感器組件280上。在一個示例中，第一導電材料235和第二導電材料245中的任何一種導電材料都是由動力冶金材料製成的。在另一個示例中，第一導電材料235和第二導電材料245中的任何一種導電材料都是由一種彈性體材料製成的。在本發明的示例中，第一升高部分233的高度至少比第一晶片焊盤222和第二晶片焊盤224高250微米。第二升高部分243的高度至少比第一晶片焊盤222和第二晶片焊盤224高250微米。如圖所示，第一晶片焊盤226和第一引線231形成一個整體，第二模塊焊盤228和第二引線241形成一個整體。還可選擇，第一末端焊盤226和第二末端焊盤228可以分別通過堆叠在第一引線231和第二引線241的部分上的導電間隔物而形成(圖中沒有表示出)。
模塑封裝290封裝了低端FET 240、高端FET 250、第一種多個接合引線291、電容器260、電阻器270、電感器組件280、第一引線231的絕大部分、第二引線241的絕大部分以及引線框220的絕大部分。
在本發明的示例中，引線框220的底面暴露於模塑封裝290。第一引線231的底面暴露於模塑封裝290。第二引線241的底面暴露於模塑封裝290。
在本發明的示例中，電感器組件280的整體都放置在高於低端FET240的整體、高端FET 250的整體以及第一種多個接合引線291的整體的位置上。
在本發明的示例中，功率半導體封裝200還包括一個積體電路(IC)299，安裝在第二個晶片焊盤224上。第二種多個接合引線298將IC 299連接到引線框220的多個引線上。模塑封裝290封裝了IC 299。
圖3A和圖3B分別表示在本發明的示例中，功率半導體封裝300沿 BB’線的俯視圖和剖面圖。
功率半導體封裝300包括一個引線框320、一個低端場效電晶體(FET)340、一個高端FET 350、一個電容器360、一個電阻器370、一個電感器組件380、第一種多個接合引線391以及模塑封裝390。引線框320包括第一晶片焊盤322、在第一晶片焊盤322附近的第二晶片焊盤324，以及第一末端焊盤326第一晶片焊盤322。
低端FET 340具有一個底面汲電極，連接到第一晶片焊盤322上。低端FET 340包括一個源電極340S和一個閘電極340G，在低端FET 340的頂面上。高端FET 350具有一個底面汲電極，連接到第二晶片焊盤324上。高端FET 350包括一個源電極350S和一個閘電極350G，在高端FET的頂面上。第一種多個接合引線391將高端FET 350的頂面源電極連接到第一晶片焊盤322上。
模塑封裝390封裝低端FET340、高端FET 350、第一種多個接合引線391、電容器360、電阻器370、電感器組件380以及引線框320的絕大部分。在本發明的示例中，引線框320的底面暴露於模塑封裝390。
在本發明的示例中，低端FET 340的底面341以及電感器組件380的底面381是共面的。
電感器組件380的一個第一端口通過第一導電材料335，電子地並機械地連接到第一晶片焊盤322上。電感器組件的第二端口通過第二導電材料345，電子地並機械地連接到第一末端焊盤326上。在一個示例中，第一導電材料335和第二導電材料345中的任何一種導電材料都是由一種粉末冶金材料製成的。在另一個示例中，第一導電材料335和第二導電材料345中的任何一種導電材料都是由一種彈性體材料製成的。
在本發明的示例中，功率半導體封裝300還包括一個安裝在第二晶片焊盤324上的積體電路(IC)399。第二種多個接合引線398將IC 399連接到引線框320的多個引線上。模塑封裝390封裝了IC 399。
本領域的普通技術人員可以理解，本發明公開的實施例的修改是可能存在的。例如，第一升高部分233的高度以及第二升高部分243的高度可以有所不同。本領域普通技術人員還可以想到其他修改，並且所有這樣的修改被認為屬於本發明的範圍之內，如同發明申請專利範圍所限定的那樣。
200:功率半導體封裝
220:引線框
222:第一個晶片焊盤
224:第二個晶片焊盤
226:第一個末端焊盤
228:第二個末端焊盤
240:低端FET
240G:閘電極
240S:源電極
250:高端FET
250S:源電極
250G:閘電極
260:電容器
270:電阻器
280:電感器組件
291:接合引線
298:接合引線
299:積體電路

Claims (7)

  1. 一種功率半導體封裝，包括：一個引線框，包括一個第一晶片焊盤；一個第二晶片焊盤；一個第一末端焊盤；以及一個第二末端焊盤，其中第一末端焊盤和第二末端焊盤設置在高於第一晶片焊盤和第二晶片焊盤的位置上；一個低端場效電晶體(FET)，其底面汲電極連接到第一晶片焊盤上，低端FET包括一個源電極和一個閘電極，在低端FET的頂面上；一個高端FET，其底面汲電極連接到第二晶片焊盤上，高端FET包括一個源電極和一個閘電極，在高端FET的頂面上；多個第一接合引線，將高端FET的頂面源電極連接到第一晶片焊盤上；一個電感器組件，包括一個第一端口和一個第二端口，第一端口堆棧在第一末端焊盤上，第二端口堆棧在第二末端焊盤上；一個第一引線，連接到第一末端焊盤上；以及一個第二引線，連接到第二末端焊盤上；以及一個模塑封裝，封裝低端FET、高端FET、多個第一接合引線、電感器組件、第一引線的大部分、第二引線的大部分以及引線框的大部分；其中第一引線包括一個第一升高部分，在第一晶片焊盤和第二晶片焊盤上方，第二引線包括一個第二升高部分，在第一晶片焊盤和第二晶片焊盤上方；其中至少一部分第 一升高部分構成第一末端焊盤，至少一部分第二升高部分構成第二末端焊盤。
  2. 如請求項1所述之功率半導體封裝，其中第一引線的第一升高部分通過第一導電材料，電子地並機械地連接到電感器組件；並且其中第二引線的第二升高部分通過第二導電材料，電子地並機械地連接到電感器組件。
  3. 如請求項2所述之功率半導體封裝，其中第一導電材料和第二導電材料的任何一種導電材料都是由一種粉末冶金材料製成的。
  4. 如請求項2所述之功率半導體封裝，其中第一導電材料和第二導電材料的任何一種導電材料都是由一種彈性體材料製成的。
  5. 如請求項2所述之功率半導體封裝，其中引線框的底面暴露於模塑封裝。
  6. 如請求項2所述之功率半導體封裝，還包括一個安裝在第二晶片焊盤上的積體電路(IC)，其中第二種多個接合引線將IC連接到引線框的多個引線上。
  7. 如請求項6所述之功率半導體封裝，其中模塑封裝封裝了IC。
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