CN112530917A - 具有集成电感器的功率半导体封装及其制造方法 - Google Patents

具有集成电感器的功率半导体封装及其制造方法 Download PDF

Info

Publication number
CN112530917A
CN112530917A CN202010917135.XA CN202010917135A CN112530917A CN 112530917 A CN112530917 A CN 112530917A CN 202010917135 A CN202010917135 A CN 202010917135A CN 112530917 A CN112530917 A CN 112530917A
Authority
CN
China
Prior art keywords
conductive material
metal clip
power semiconductor
semiconductor package
side fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010917135.XA
Other languages
English (en)
Inventor
张晓天
玛丽·简·R·阿琳
陈波
小大卫·布里安·奥拉博尼
王隆庆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alpha and Omega Semiconductor Cayman Ltd
Original Assignee
Alpha and Omega Semiconductor Cayman Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alpha and Omega Semiconductor Cayman Ltd filed Critical Alpha and Omega Semiconductor Cayman Ltd
Publication of CN112530917A publication Critical patent/CN112530917A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H01L2224/84815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

一种功率半导体封装包括一个引线框、一个低端场效应晶体管(FET)、一个高端FET、一个第一金属夹、一个第二金属夹、一个电感器组件以及一个模塑封装。低端FET翻转并连接到引线框的第一芯片焊盘上。一种功率半导体封装的制备方法。该方法包括以下步骤：制备一个引线框；将低端FET和高端FET连接到引线框上；安装第一金属夹和第二金属夹；安装一个电感器；制备一个模塑封装；并且使用切单工艺。

Description

具有集成电感器的功率半导体封装及其制造方法
技术领域
本发明主要涉及一种半导体封装及其制造方法。更确切地说，本发明涉及一种具有集成电感器的驱动金属-氧化物-硅晶体管(DrMOS)。
背景技术
传统的DrMOS在DrMOS封装外部具有一个电感器。图2所示的Yin等人的美国专利号10、111和333，在切换电源模块中具有一个电感器。本发明说明书在DrMOS封装中具有一个集成的电感器。本发明还使用金属夹互连，以便降低电子噪声，并增大散热。
本发明所述的功率半导体封装包括一个控制器、两个场效应晶体管(FET)以及一个电感器。由于集成了电感器，其优点包括更小的外形尺寸、更好的散热和更高的电效率。通过集成方法，针对驱动器和FET动态性能、系统电感和功率FET RDS(ON)，优化了完整的开关功率级。
发明内容
本发明提出了一种半导体封装，包括一个引线框、一个低端场效应晶体管(FET)、一个高端FET、一个第一金属夹、一个第二金属夹、一个电感器组件以及一个模塑封装。低端FET翻转并连接到引线框架的第一芯片焊盘上。
本发明还公开了一种用于制造功率半导体封装的方法。该方法包括提供引线框的步骤；将低端FET和高端FET附接到引线框架；安装第一金属夹和第二金属夹；安装电感器；形成模制封装；并应用切单工艺。
附图说明
图1表示在本发明的示例中，一种半导体封装的透视图。
图2表示在本发明的示例中，图1所示的功率半导体封装的剖面图。
图3表示在本发明的示例中，一种DrMOS的电路图。
图4表示在本发明的示例中，制造一种功率半导体封装工艺的流程图。
图5A、5B、5C、5D、5E和5F表示在本发明的示例中，制造功率半导体封装工艺的步骤。
具体实施方式
图1表示在本发明的示例中，功率半导体封装100的透视图。图2表示沿图1的AA’线，功率半导体封装100的剖面图。功率半导体封装100包括一个引线框120、一个低端场效应晶体管(FET)140、一个图5B所示的高端FET 150、一个第一金属夹160、一个第二金属夹170、一个电感器组件180以及一个模塑封装190。引线框120包括一个图5A所示的第一芯片焊盘522、一个第二芯片焊盘524、一个第一终端焊盘526以及一个第二终端焊盘528。第一终端焊盘526电连接到图3所示的开关节点VSWH端口326上。第二终端焊盘528电连接到图3所示的Vout端口328上。
低端FET 140被翻转并被连接到第一芯片焊盘522。导电FET 140包括在低端FET140的顶表面上的源电极140S和栅电极140G。高端FET 150被连接在第二芯片焊盘524上。高端FET 150包括一个图5B所示的源电极150S，以及一个在高端FET 150顶面上的栅电极150G。
第一金属夹160将低端FET 140的漏极140D以及高端FET 150中图5B所示的源电极150S，连接到引线框120中图5A所示的第一末端焊盘526上。第二金属夹170安装在引线框架120的图5A所示的第二末端焊盘528上。
电感器组件180包括一个线圈181；一个连接到第一金属夹160上的第一引线框182；以及一个连接到第二金属夹170上的第二引线框184。
模塑封装190封装了低端FET 140、高端FET 150、第一金属夹160、第二金属夹170、电感器组件180以及引线框120的绝大部分。在本发明的示例中，引线框120的底面暴露于模塑封装190。
在本发明的示例中，第一金属夹160通过第一导电材料201，电子地并机械地连接到低端FET 140的漏电极140D上。第一金属夹160通过图5C所示的第二导电材料202(如图中虚线所示)，电子地并机械地连接到高端FET 150的源极电极150S上。第一金属夹160通过第三导电材料203，电子地并机械地连接到引线框120的第一末端焊盘526上。第二金属夹170通过第四导电材料204，电子地并机械地连接到引线框120的第二末端焊盘528上。在本发明的示例中，第一导电材料201由一种焊锡膏材料制成。第二导电材料202由一种焊锡膏材料制成。第三导电材料203由一种焊锡膏材料制成。第四导电材料204由一种焊锡膏材料制成。
在本发明的示例中，第一金属夹160包括一个升高部分167。电感器组件180的第一引线182通过第五导电材料205，电子地并机械地连接到第一金属夹160的升高部分167上。电感器组件180的第二引线184通过第六导电材料206，电子地并机械地连接到第二金属夹170的升高部分177上。
在本发明的示例中，第五导电材料205和第六导电材料206的每一种导电材料都是由通过混合烧结工艺实现的粉末冶金材料制成的。
在本发明的示例中，第五导电材料205和第六导电材料206的每一种导电材料都是由一种弹性体材料制成的。
在本发明的示例中，第五导电材料205和第六导电材料206的每一种导电材料都是由一种环氧材料制成的。
在本发明的示例中，集成电路(IC)591安装在引线框120上。多个连接引线593将IC591连接到引线框120的多个引线595上。
图3表示在本发明的示例中，一种DrMOS的电路图300。该DrMOS包括一个子封装302、一个电感器330以及多个电容器370。子封装302包括一个控制器310、一个低端FET 340以及一个高端FET 350。
图4表示在本发明的示例中，一种功率半导体封装的制备工艺400的流程图。工艺400从区块402开始。为了简便，图5F的虚线中的右侧部分(与实线中相应的左侧部分一样)并没有表示在图5A、5B、5C、5D和5E中。
在区块402中，参见图5A，提供了一个引线框120。引线框120包括一个第一芯片焊盘522、一个第二芯片焊盘524、一个第一末端焊盘526以及一个第二末端焊盘528。区块402之后是区块404。
在区块404中，参见图5A，低端FET 140翻转并连接到第一芯片焊盘522上。低端FET140包括一个图2所示的源极电极140S以及一个在低端FET 140顶面上的如图2所示的栅极电极140G。高端FET 150连接到第二芯片焊盘524上。高端FET 150包括一个源极电极150S以及一个在高端FET 150顶面上的栅极电极150G。区块404之后是区块406。
在区块406中，如图5C所示，第一金属夹160将低端FET 140中如图2所示的漏极电极140D以及高端FET 150中图5B所示的源极电极150S，连接到引线框120的第一末端焊盘526上。第二金属夹170安装在引线框120的第二末端焊盘528上。
第一金属夹160通过图2所示的第一导电材料201，电子地并机械地连接到低端FET140中图2所示的漏极电极140D上。第一金属夹160通过第二导电材料(如图中虚线所示)，电子地并机械地连接到高端FET 150中图5B所示的源极电极150S上。第一金属夹160通过图2所示的第三导电材料203，电子地并机械地连接到引线框120的第一末端焊盘526上。第二金属夹170通过图2所示的第四导电材料204，电子地并机械地连接到引线框120的第二末端焊盘528上。在本发明的示例中，第一导电材料201由一种焊锡膏材料制成。第二导电材料202由一种焊锡膏材料制成。第三导电材料203由一种焊锡膏材料制成。第四导电材料204由一种焊锡膏材料制成。在本发明的示例中，焊锡膏材料含有铅(Pb)。焊锡膏材料的回流温度高于两百摄氏度。区块406之后是区块408。
在区块408中，参见图5D，集成电路(IC)591安装在引线框120上。多个连接引线593将IC 591连接到引线框120的多个引线595上。区块408之后是区块410。
在区块410中，参见图5E，电感器组件180安装在图5C所示的第一金属夹160和第二金属夹170上。电感器组件180包括一个图2所示的线圈181；一个连接到图5C所示第一金属夹160的第一引线182；以及一个连接到第二金属夹170上的源极引线184。
第一金属夹160包括一个图2所示的升高部分167。电感器组件180的第一引线182通过图2所示的第五导电材料205(第一个所选的导电材料)，电子地并机械地连接到第一金属夹160中图2所示的升高部分167上。第二金属夹170包括一个图2所示的升高部分177。电感器组件180的第二引线184通过图2所示的第六导电材料206(第二个所选的导电材料)，电子地并机械地连接到第二金属夹170中图2所示的升高部分177上。
在本发明的示例中，第五导电材料205(第一个所选的导电材料)以及第六导电材料206(第二个所选的导电材料)中的每种导电材料都包括一个通过混合烧结工艺实现的粉末冶金材料，在195摄氏度至205摄氏度的温度范围内实现的。
在本发明的示例中，第五导电材料205(第一个所选的导电材料)以及第六导电材料206(第二个所选的导电材料)中的每种导电材料都包括一个弹性体材料，在75摄氏度至85摄氏度的温度范围内实现的。
在本发明的示例中，第五导电材料205(第一个所选的导电材料)以及第六导电材料206(第二个所选的导电材料)中的每种导电材料都包括一个环氧材料，在170摄氏度至180摄氏度的温度范围内实现的。区块410之后是区块412。
在区块412中，参见图1，形成模塑封装190。模塑封装190封装了低端FET 140、高端FET 150、第一金属夹160、第二金属夹170、电感器组件180以及引线框120的绝大部分。在本发明的示例中，引线框120的底面暴露于模塑封装190。区块412之后是区块414。
在区块414中，参见图5F，沿551线进行切单工艺。将功率半导体封装531与邻近的功率半导体封装533(如图中虚线所示)分开。虽然图5F中仅表示出了两个功率半导体封装。但是同一个切单工艺中切分的功率半导体封装的数量可以有所不同。
本领域的普通技术人员可以理解，本发明公开的实施例的修改是可能的。例如，第二金属夹170的升高部分177的高度可能变化。本领域普通技术人员还可以想到其他修改，并且所有这样的修改被认为属于本发明的范围之内，如同权利要求所限定的那样。

Claims (9)

1.一种功率半导体封装包括：
一个引线框，包括
一个第一芯片焊盘；
一个第二芯片焊盘；
一个第一末端焊盘；以及
一个第二末端焊盘；
一个低端场效应晶体管(FET)翻转并连接到第一芯片焊盘上，低端FET包括一个源极电极以及一个栅极电极，在低端FET的顶面上；
一个连接到第二芯片焊盘上的高端FET，高端FET包括一个源极电极和一个栅极电极，在高端FET的顶面上；
一个第一金属夹，将低端FET的漏极电极以及高端FET的源极电极连接到引线框的第一末端焊盘上；
一个第二金属夹，安装在引线框的第二末端焊盘上；
一个电感器组件，包括：
一个连接到第一金属夹的第一引线；以及
一个连接到第二金属夹的第二引线；以及
一个模塑封装，封装了低端FET、高端FET、第一金属夹、第二金属夹、电感器组件以及引线框的大部分。
2.权利要求1所述的功率半导体封装，其中第一金属夹通过第一导电材料，电子地并机械地连接到低端FET的漏极电极；
其中第一金属夹通过第二导电材料，电子地并机械地连接到高端FET的源极电极；
其中第一金属夹通过第三导电材料，电子地并机械地连接到引线框的第一末端焊盘；并且
其中第二金属夹通过第四导电材料，电子地并机械地连接到引线框的第二末端焊盘。
3.权利要求2所述的功率半导体封装，其中第一金属夹包括一个升高部分；
其中电感器组件的第一引线通过第五导电材料，电子地并机械地连接到第一金属夹的升高部分；
其中第二金属夹包括一个升高部分；并且
其中电感器组件的第二引线通过第六导电材料，电子地并机械地连接到第二金属夹的升高部分。
4.权利要求3所述的功率半导体封装，其中第一导电材料、第二导电材料、第三导电材料以及第四导电材料中的每种导电材料都是由一种焊锡膏材料制成。
5.权利要求4所述的功率半导体封装，其中第五导电材料和第六导电材料中的每种导电材料都是由一种粉末冶金材料制成。
6.权利要求4所述的功率半导体封装，其中第五导电材料和第六导电材料中的每种导电材料都是由一种弹性体材料制成。
7.权利要求4所述的功率半导体封装，其中第五导电材料和第六导电材料中的每种导电材料都是由一种环氧材料制成。
8.权利要求4所述的功率半导体封装，其中引线框的底面暴露于模塑封装。
9.权利要求4所述的功率半导体封装，还包括一个安装在引线框上的集成电路(IC)，其中多个接合引线将IC连接到引线框的多个引线上。
CN202010917135.XA 2019-09-18 2020-09-03 具有集成电感器的功率半导体封装及其制造方法 Pending CN112530917A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/575,193 US20210082790A1 (en) 2019-09-18 2019-09-18 Power semiconductor package having integrated inductor and method of making the same
US16/575,193 2019-09-18

Publications (1)

Publication Number Publication Date
CN112530917A true CN112530917A (zh) 2021-03-19

Family

ID=74869800

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010917135.XA Pending CN112530917A (zh) 2019-09-18 2020-09-03 具有集成电感器的功率半导体封装及其制造方法

Country Status (3)

Country Link
US (1) US20210082790A1 (zh)
CN (1) CN112530917A (zh)
TW (1) TWI765334B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007137221A2 (en) * 2006-05-19 2007-11-29 Fairchild Semiconductor Corporation Dual side cooling integrated transistor module and methods of manufacture
CN104603948A (zh) * 2012-09-05 2015-05-06 德克萨斯仪器股份有限公司 垂直堆叠的功率fet和具有低导通电阻的同步降压转换器
US20160104665A1 (en) * 2014-10-08 2016-04-14 International Rectifier Corporation Power Converter Package with Integrated Output Inductor
US20160365304A1 (en) * 2015-06-09 2016-12-15 Infineon Technologies Americas Corp. Semiconductor Package with Embedded Output Inductor
CN107546191A (zh) * 2016-06-23 2018-01-05 万国半导体股份有限公司 具有单列直插引线模块的半导体功率器件及其制备方法
CN112530918A (zh) * 2019-09-18 2021-03-19 万国半导体国际有限合伙公司 具有集成电感器，电阻器和电容器的功率半导体封装

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8304887B2 (en) * 2009-12-10 2012-11-06 Texas Instruments Incorporated Module package with embedded substrate and leadframe
KR101033044B1 (ko) * 2009-12-30 2011-05-09 제일모직주식회사 반도체용 접착 조성물 및 이를 포함하는 다이 접착 필름
CN105990265B (zh) * 2015-02-26 2019-04-05 台达电子工业股份有限公司 功率转换电路的封装模块及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007137221A2 (en) * 2006-05-19 2007-11-29 Fairchild Semiconductor Corporation Dual side cooling integrated transistor module and methods of manufacture
CN104603948A (zh) * 2012-09-05 2015-05-06 德克萨斯仪器股份有限公司 垂直堆叠的功率fet和具有低导通电阻的同步降压转换器
US20160104665A1 (en) * 2014-10-08 2016-04-14 International Rectifier Corporation Power Converter Package with Integrated Output Inductor
US20160365304A1 (en) * 2015-06-09 2016-12-15 Infineon Technologies Americas Corp. Semiconductor Package with Embedded Output Inductor
CN107546191A (zh) * 2016-06-23 2018-01-05 万国半导体股份有限公司 具有单列直插引线模块的半导体功率器件及其制备方法
CN112530918A (zh) * 2019-09-18 2021-03-19 万国半导体国际有限合伙公司 具有集成电感器，电阻器和电容器的功率半导体封装

Also Published As

Publication number Publication date
TWI765334B (zh) 2022-05-21
TW202125730A (zh) 2021-07-01
US20210082790A1 (en) 2021-03-18

Similar Documents

Publication Publication Date Title
US8345458B2 (en) Semiconductor device
US10930582B2 (en) Semiconductor device having terminals directly attachable to circuit board
US8508052B2 (en) Stacked power converter structure and method
US8023279B2 (en) FLMP buck converter with a molded capacitor and a method of the same
CN104603948A (zh) 垂直堆叠的功率fet和具有低导通电阻的同步降压转换器
US8063472B2 (en) Semiconductor package with stacked dice for a buck converter
CN112530917A (zh) 具有集成电感器的功率半导体封装及其制造方法
CN106024773B (zh) 包括多层级载体的化合物半导体装置
US11309233B2 (en) Power semiconductor package having integrated inductor, resistor and capacitor
EP3690937B1 (en) Cascode semiconductor device and method of manufacture

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination