CN102637632A - 一种薄膜晶体管阵列的制作方法和薄膜晶体管阵列 - Google Patents
一种薄膜晶体管阵列的制作方法和薄膜晶体管阵列 Download PDFInfo
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Abstract
本发明提供一种薄膜晶体管阵列的制作方法和薄膜晶体管阵列,用以解决现有4Mask工艺生产工艺较复杂、生产成本较高、生产周期较长的问题。该方法包括:在基板上依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,进行第一道成像光刻工艺,形成公共电极线、栅线、栅电极、源电极、漏电极和沟道;沉积钝化层,进行第二道成像光刻工艺,在源电极上方的钝化层上形成第一过孔,在漏电极上方的钝化层上形成第二过孔;依次沉积像素电极层和数据线层,进行第三道成像光刻工艺,形成数据线和像素电极,数据线通过第一过孔与源电极连接,像素电极通过第二过孔与漏电极连接。该方案减少了工艺循环次数,降低了生产时间和成本,提高了生产效率。
Description
技术领域
本发明涉及薄膜晶体管阵列技术领域,特别涉及一种薄膜晶体管阵列的制作方法和薄膜晶体管阵列。
背景技术
为了有效地降低薄膜晶体管液晶显示器的价格和提高其成品率,薄膜晶体管阵列的制造工艺逐步得到简化,目前普遍采用的是4Mask工艺。
4Mask工艺采用四道成像光刻工艺来实现薄膜晶体管阵列的制作,其中,第一道成像光刻工艺用于栅线和公共电极线的成型,第二道成像光刻工艺用于数据线以及薄膜晶体管器件的初步成型,第三道成像光刻工艺用于将薄膜晶体管漏电极的钝化层去除,从而将像素电极与漏电极连接起来,第四道成像光刻工艺用于像素电极的成型。经过这四次工艺循环即可实现薄膜晶体管阵列的制作。这一工艺虽然相对成熟,但是仍然存在生产工艺较复杂、生产成本较高、生产周期较长的问题。
发明内容
本发明实施例提供了一种薄膜晶体管阵列的制作方法和薄膜晶体管阵列,用以解决现有4Mask工艺具有生产工艺较复杂、生产成本较高、生产周期较长的问题。
本发明实施例提供了一种薄膜晶体管阵列的制作方法,包括:
在基板上依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,进行第一道成像光刻工艺,形成公共电极线、栅线、栅电极、源电极、漏电极和位于所述源电极与所述漏电极之间的一沟道;
沉积钝化层,进行第二道成像光刻工艺,在所述源电极上方的钝化层上形成第一过孔,在所述漏电极上方的钝化层上形成第二过孔;
依次沉积像素电极层和数据线层,进行第三道成像光刻工艺,形成数据线和像素电极,所述数据线通过所述第一过孔与所述源电极连接,所述像素电极通过所述第二过孔与所述漏电极连接。
所述公共电极线包括相邻的第一公共电极线和第二公共电极线;
所述依次沉积像素电极层和数据线层之前,所述制作方法还包括:
在所述第一公共电极线上方的钝化层上形成第三过孔,在所述第二公共电极线上方的钝化层上形成第四过孔;
所述形成数据线的同时,所述制作方法还包括:
形成公共电极互连线,所述公共电极互连线的一端与所述第三过孔连接,所述公共电极互连线的另一端与所述第四过孔连接。
所述在基板上依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,进行第一道成像光刻工艺,形成公共电极线、栅线、栅电极、源电极、漏电极和位于所述源电极与所述漏电极之间的一沟道,具体为:
在基板上,依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,采用第一掩模版进行掩模和曝光;
进行刻蚀,形成公共电极线图形、栅线图形和栅电极图形;
刻蚀掉所述公共电极线图形和栅线图形上方的半导体层和源漏电极层,形成公共电极线和栅线;
对所述栅电极图形上方的栅绝缘层、半导体层和源漏电极层进行刻蚀,使所述栅电极图形上方的栅绝缘层、半导体层和源漏电极层的边角呈梯形边角;
对所述栅电极图形上方的源漏电极层进行刻蚀,形成沟道,所述沟道两侧分别为源电极和漏电极。
所述依次沉积像素电极层和数据线层,进行第三道成像光刻工艺,形成数据线和像素电极,所述数据线通过所述第一过孔与所述源电极连接,所述像素电极通过所述第二过孔与所述漏电极连接,具体为:
依次沉积像素电极层和数据线层,采用第三掩模版,进行掩模和曝光;
进行刻蚀,形成像素电极图形和数据线,所述数据线通过所述第一过孔与所述源电极连接;
刻蚀掉所述像素电极图形上方的数据线层,形成像素电极,所述像素电极通过所述第二过孔与所述漏电极连接。
所述数据线层包括数据金属层和氧化铟锡层。
所述像素电极层为氧化铟锡层;
所述栅金属层和/或所述数据金属层为Cr、W、Ti、Ta、Mo、Al或Cu的单层;或者
所述栅金属层和/或所述数据金属层为Cr、W、Ti、Ta、Mo、Al、Cu中的任意两种或两种以上的金属组合构成的复合层。
所述栅金属层和/或所述数据金属层的刻蚀用液体为磷酸、醋酸和硝酸;
所述像素电极层的刻蚀用液体为硫酸、醋酸和硝酸。
所述半导体层为氢化非晶硅层或多晶硅层;
所述源漏电极层为N+非晶硅层或掺杂多晶硅层。
所述栅绝缘层、半导体层、源漏电极层和钝化层的刻蚀用气体为Cl2和SF6。
本发明实施例还提供了一种利用上述制作方法制作的薄膜晶体管阵列。
相比现有4Mask工艺,本发明实施例中的3Mask工艺调整了部分膜层的沉积顺序,利用新型Mask版,合理安排每次Mask所处理的膜层,实现了薄膜晶体管阵列的3Mask工艺流程,减少了工艺循环次数,降低了生产时间和成本,提高了生产效率。
附图说明
图1为本发明实施例中薄膜晶体管阵列的制作方法流程图;
图2为本发明实施例中步骤S11中的步骤A1沉积膜层的截面示意图;
图3为本发明实施例中步骤S11中的步骤A2形成图形的平面示意图;
图4A为本发明实施例中步骤S11中的步骤A3-A4形成器件的截面示意图;
图4B为图4A对应的平面示意图;
图5A为本发明实施例中步骤S11中的步骤A5形成器件的截面示意图;
图5B为图5A对应的平面示意图;
图6为本发明实施例中步骤S12沉积钝化层后的截面示意图;
图7A为本发明实施例中步骤S12形成过孔的截面示意图;
图7B为图7A对应的平面示意图;
图8为本发明实施例中步骤S13中的步骤B1沉积像素电极层和数据线层后的截面示意图;
图9A为本发明实施例中步骤S13中的步骤B2-B3形成器件的截面示意图;
图9B为图9A对应的平面示意图;
图10A为本发明实施例中相邻的公共电极线上形成有过孔的水平示意图;
图10B为本发明实施例中通过公共电极互连线连接公共电极线的水平示意图。
具体实施方式
为使本发明实施例要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
本发明实施例提供的薄膜晶体管阵列的制作方法属3Mask工艺,通过调整部分膜层的沉积顺序,利用新型Mask版,合理安排每次Mask所处理的膜层,实现了薄膜晶体管阵列的3Mask工艺流程,减少了工艺循环次数,降低了生产时间和成本,提高了生产效率。
如图1所示,本发明实施例提供了一种薄膜晶体管阵列的制作方法,包括:
S11、在基板上依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,进行第一道成像光刻工艺,形成公共电极线、栅线、栅电极、源电极、漏电极和位于源电极与漏电极之间的一沟道。
具体地,步骤S11包括:
A1、在基板1上,依次沉积栅金属层2、栅绝缘层3、半导体层4和源漏电极层5(如图2),采用第一掩模版进行掩模和曝光;
A2、进行刻蚀,形成公共电极线图形、栅线图形(方格填充部分的竖向段)和栅电极图形(方格填充部分的横向段)(如图3);
A3、刻蚀掉公共电极线图形和栅线图形上方的半导体层和源漏电极层,形成公共电极线6和栅线7;
A4、对栅电极图形上方的栅绝缘层、半导体层和源漏电极层进行刻蚀,使栅电极图形上方的栅绝缘层、半导体层和源漏电极层的边角呈梯形边角(如图4A、4B,栅电极8与栅线7成一体);
A5、对栅电极图形上方的源漏电极层进行刻蚀,形成沟道,沟道两侧分别为源电极9和漏电极10(如图5A、5B)。
S12、沉积钝化层11(如图6),进行第二道成像光刻工艺,在源电极9上方的钝化层上形成第一过孔,在漏电极10上方的钝化层上形成第二过孔(如图7A、7B)。
第一过孔用于与接下来沉积的数据线连接,第二过孔用于与接下来沉积的像素电极连接。
S13、依次沉积像素电极层和数据线层,进行第三道成像光刻工艺,形成数据线和像素电极,数据线通过第一过孔与源电极连接,像素电极通过第二过孔与漏电极连接。
具体地,步骤S13包括:
B1、依次沉积像素电极层12和数据线层(如图8,数据线层包括数据金属层13和氧化铟锡层14,氧化铟锡层14起到防止数据线氧化的作用,氧化铟锡层14亦可用其它防氧化材料层代替),采用第三掩模版,进行掩模和曝光;
B2、进行刻蚀,形成像素电极图形和数据线15,数据线15通过第一过孔与源电极9连接;
B3、刻蚀掉像素电极图形上方的数据线层,形成像素电极16,像素电极16通过第二过孔与漏电极10连接(如图9A、9B)。
为了实现公共电极线的互连、便于维修GO类不良,步骤S12在形成第一过孔和第二过孔的同时,还可以在两条相邻的公共电极线上方的钝化层上形成过孔;步骤S13在形成数据线的同时,形成通过过孔将两条相邻的公共电极线互连起来的公共电极互连线。
如图10(未示出像素电极),相邻的第一公共电极线17和第二公共电极线18,步骤S12在形成第一过孔和第二过孔的同时,在第一公共电极线17上方的钝化层上形成第三过孔,在第二公共电极线18上方的钝化层上形成第四过孔;步骤S13在形成数据线的同时,形成公共电极互连线19,公共电极互连线19的一端与第三过孔连接,公共电极互连线19的另一端与第四过孔连接。
公共电极互连线使得公共电极线形成网状互连,因此,在维修GO类不良时可以借助公共电极线进行维修,而不用担心造成CO。
上述制作方法中,栅绝缘层的沉积用材料为SiH4、NH3和N2;半导体层的沉积用材料为SiH4和H2;源漏电极层的沉积用材料为SiH4、PH3和H2;钝化层的沉积用材料为SiH4、NH3和N2。
栅金属层和/或数据金属层为Cr、W、Ti、Ta、Mo、Al或Cu等金属的单层,或者栅金属层和/或数据金属层为Cr、W、Ti、Ta、Mo、Al、Cu等金属中的任意两种或两种以上的金属组合构成的复合层。栅金属层和/或数据金属层的刻蚀用液体为磷酸、醋酸和硝酸。
像素电极层为氧化铟锡层、铟锌氧化物层或者其它电极材料层。像素电极层的刻蚀用液体为硫酸、醋酸和硝酸。
栅绝缘层和钝化层为绝缘氧化物层、绝缘氮化物层、绝缘氮氧化物层或者其它绝缘材料层,较佳地,钝化层的绝缘性高于栅绝缘层。半导体层为氢化非晶硅层(a-Si:H)、多晶硅层或其它半导体材料层。源漏电极层为N+非晶硅层(N+a-Si:H)、掺杂多晶硅层或其它半导体材料层。栅绝缘层、半导体层、源漏电极层和钝化层的刻蚀用气体为Cl2和SF6。
本发明实施例中各膜层的构成材料、沉积方法、沉积用材料和刻蚀用材料可根据需要进行选择,并不限于以上所述。
下表1是本发明实施例提出的3Mask工艺流程,下表2是现有4Mask工艺流程表格。
对比表1、表2可知,相比现有4Mask工艺,本发明实施例提出的3Mask工艺调整了部分膜层的沉积顺序,利用新型Mask版,合理安排每次Mask所处理的膜层,实现了薄膜晶体管阵列的3Mask工艺流程,减少了工艺循环次数,降低了生产时间和成本,提高了生产效率。
表1:本发明3Mask工艺流程
表2:现有4Mask工艺流程
另外,本发明实施例还提供了一种利用本发明实施例提供的上述制作方法制作的薄膜晶体管阵列。
如图9A、9B所示,本发明实施例提供的薄膜晶体管阵列包括:
基板1;
公共电极线6、栅线7和与栅线7一体的栅电极8,形成于基板1上;
栅绝缘层3,形成于公共电极线6、栅线7和栅电极8的上方;
半导体层4,形成于栅电极8上方的栅绝缘层3的上方;
源电极9和漏电极10,形成于半导体层4的上方,源电极9与漏电极10之间具有一沟道,源电极9和漏电极10的边角呈梯形边角;
钝化层11,形成于上述各器件的上方;
第一过孔,形成于源电极9上方的钝化层上;
第二过孔,形成于漏电极10上方的钝化层上;
数据线15,通过第一过孔与源电极9连接;
像素电极16,通过第二过孔与漏电极10连接。
另外,为了实现公共电极线的互连、便于维修GO类不良,如图10A、10B所示,公共电极线包括相邻的第一公共电极线17和第二公共电极线18;薄膜晶体管阵列还包括:
第三过孔,形成于第一公共电极线17上方的钝化层上(如图10A);
第四过孔,形成于第二公共电极线18上方的钝化层上(如图10A);
公共电极互连线19,一端与第三过孔连接,另一端与第四过孔连接(如图10B)。
公共电极互连线使得公共电极线形成网状互连,因此,在维修GO(GateOpen,栅线断路)类不良时可以借助公共电极线进行维修,而不用担心造成CO(Common Open,公共电极断路)。
本发明实施例提出的薄膜晶体管阵列的结构并不限于以上所述,凡是按照本发明实施例提供的3Mask工艺制作而成的薄膜晶体管阵列,都包含在本发明保护范围之内。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (10)
1.一种薄膜晶体管阵列的制作方法,其特征在于,包括:
在基板上依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,进行第一道成像光刻工艺,形成公共电极线、栅线、栅电极、源电极、漏电极和位于所述源电极与所述漏电极之间的一沟道;
沉积钝化层,进行第二道成像光刻工艺,在所述源电极上方的钝化层上形成第一过孔,在所述漏电极上方的钝化层上形成第二过孔;
依次沉积像素电极层和数据线层,进行第三道成像光刻工艺,形成数据线和像素电极,所述数据线通过所述第一过孔与所述源电极连接,所述像素电极通过所述第二过孔与所述漏电极连接。
2.如权利要求1所述的制作方法,其特征在于,
所述公共电极线包括相邻的第一公共电极线和第二公共电极线;
所述依次沉积像素电极层和数据线层之前,所述制作方法还包括:
在所述第一公共电极线上方的钝化层上形成第三过孔,在所述第二公共电极线上方的钝化层上形成第四过孔;
所述形成数据线的同时,所述制作方法还包括:
形成公共电极互连线,所述公共电极互连线的一端与所述第三过孔连接,所述公共电极互连线的另一端与所述第四过孔连接。
3.如权利要求1或2所述的制作方法,其特征在于,所述在基板上依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,进行第一道成像光刻工艺,形成公共电极线、栅线、栅电极、源电极、漏电极和位于所述源电极与所述漏电极之间的一沟道,具体为:
在基板上,依次沉积栅金属层、栅绝缘层、半导体层和源漏电极层,采用第一掩模版进行掩模和曝光;
进行刻蚀,形成公共电极线图形、栅线图形和栅电极图形;
刻蚀掉所述公共电极线图形和栅线图形上方的半导体层和源漏电极层,形成公共电极线和栅线;
对所述栅电极图形上方的栅绝缘层、半导体层和源漏电极层进行刻蚀,使所述栅电极图形上方的栅绝缘层、半导体层和源漏电极层的边角呈梯形边角;
对所述栅电极图形上方的源漏电极层进行刻蚀,形成沟道,所述沟道两侧分别为源电极和漏电极。
4.如权利要求1或2所述的制作方法,其特征在于,所述依次沉积像素电极层和数据线层,进行第三道成像光刻工艺,形成数据线和像素电极,所述数据线通过所述第一过孔与所述源电极连接,所述像素电极通过所述第二过孔与所述漏电极连接,具体为:
依次沉积像素电极层和数据线层,采用第三掩模版,进行掩模和曝光;
进行刻蚀,形成像素电极图形和数据线,所述数据线通过所述第一过孔与所述源电极连接;
刻蚀掉所述像素电极图形上方的数据线层,形成像素电极,所述像素电极通过所述第二过孔与所述漏电极连接。
5.如权利要求1所述的制作方法,其特征在于,
所述数据线层包括数据金属层和氧化铟锡层。
6.如权利要求5所述的制作方法,其特征在于,
所述像素电极层为氧化铟锡层;
所述栅金属层和/或所述数据金属层为Cr、W、Ti、Ta、Mo、Al或Cu的单层;或者
所述栅金属层和/或所述数据金属层为Cr、W、Ti、Ta、Mo、Al、Cu中的任意两种或两种以上的金属组合构成的复合层。
7.如权利要求6所述的制作方法,其特征在于,
所述栅金属层和/或所述数据金属层的刻蚀用液体为磷酸、醋酸和硝酸;
所述像素电极层的刻蚀用液体为硫酸、醋酸和硝酸。
8.如权利要求1所述的制作方法,其特征在于,
所述半导体层为氢化非晶硅层或多晶硅层;
所述源漏电极层为N+非晶硅层或掺杂多晶硅层。
9.如权利要求8所述的制作方法,其特征在于,
所述栅绝缘层、半导体层、源漏电极层和钝化层的刻蚀用气体为Cl2和SF6。
10.一种利用上述权利要求1-9中任一制作方法制作的薄膜晶体管阵列。
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