CN102456668B - 用于三维集成电路(3dic)的穿透硅通孔(tsv)的测试结构 - Google Patents
用于三维集成电路(3dic)的穿透硅通孔(tsv)的测试结构 Download PDFInfo
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- CN102456668B CN102456668B CN201110317964.5A CN201110317964A CN102456668B CN 102456668 B CN102456668 B CN 102456668B CN 201110317964 A CN201110317964 A CN 201110317964A CN 102456668 B CN102456668 B CN 102456668B
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Abstract
将基板上的或者3维集成电路(3DIC)中的多个穿透硅通孔(TSV)链接在一起。将TSV链接在一起,从而增大了电信号。多个测试焊盘能够用于测试TSV。一个测试焊盘接地。剩下的测试焊盘电连接到链中的TSV,或者接地。
Description
相关申请的交叉参考
本申请要求于2010年10月26日提交的美国临时专利申请第61/406,763号以及2010年10月27日提交的美国临时专利申请第61/407,268号的优先权,其全部内容并入本申请作为参考。
技术领域
本发明基本上涉及集成电路,更具体地来说,涉及三维集成电路(3DIC)。
背景技术
各种电子元件(即,晶体管、二极管、电阻器、电容器等等)集成密度的不断改进带动了集成电路的迅猛发展。在很大程度上,集成密度上的改进来自于最小元件尺寸的不断减小,从而使得在给定芯片区域上能够集成更多的元件。
集成元件所占据位置接近半导体晶圆的表面。尽管光刻法的快速发展为二维(2D)集成电路的形成带来了相当大的发展,但是在二维中对密度存在着物理限制。而且,当有更多器件放置到一个芯片中时,所需要的设计更加复杂。随着器件数量的增加,由器件之间互连的数量和长度的巨大增长而产生了附加限制。当互连的数量和长度增加时,电路RC延迟和能量损耗增加。
由此产生出了三维集成电路(3DIC),其中,可以将管芯堆叠,利用引线接合、倒装芯片接合、和/或穿透硅通孔(TSV)将管芯堆叠在一起,并且将管芯连接到封装基板。
发明内容
针对现有技术中的缺陷,本发明提供了一种用于在基板上链接穿透硅通孔(TSV)的测试结构,所述测试结构包括:多个TSV,从所述基板的第一表面延伸到相对于所述第一对面的所述基板的第二表面,其中,所述多个TSV通过互连而链接在一起,以及多个测试焊盘,其中,所述多个测试焊盘中的至少一个接地到所述基板,并且,其中,剩下的所述多个测试焊盘或者与所述链接的TSV连接,或者接地。
根据本发明所述的测试结构,其中,链接所述多个TSV的所述互连包括重分布层中的结构。
根据本发明所述的测试结构,其中,多个测试焊盘包括五个测试焊盘,一个测试焊盘接地到所述基板,两个测试焊盘连接到所述链接的TSV的一端,剩下的两个测试焊盘链接到所述链接的TSV的另一端。
根据本发明所述的测试结构,其中,配置所述测试结构以实施电性测试,从而确定所述基板上的所述多个TSV的质量和特性。
根据本发明所述的测试结构,其中,配置所述测试结构以测试所述链接的TSV的频率、电阻、电容和泄露。
根据本发明所述的测试结构,其中,所述多个TSV的数量等于或者大于约2。
根据本发明所述的测试结构,其中,所述多个TSV以菊花链方式链接在一起。
根据本发明所述的测试结构,包括:多于一个测试区域,并且,其中,每个所述测试区域都有所述的五个测试焊盘。
根据本发明所述的测试结构,其中,所述基板的所述多个TSV在每个所述测试区域中链接在一起,并且链接在一个所述测试区域中的所述TSV进一步与在另一测试区域内链接的所述TSV相链接,从而能够测试每个测试区域中的TSV以及穿过多个所述测试区域的所述链接的TSV。
根据本发明所述的测试结构,其中,所述测试结构位于所述结构的管芯内。
根据本发明所述的测试结构,进一步包括:倍频器;以及分频器,其中,所述倍频器和所述分频器能够连接到所述链接的TSV,从而允许通过所述测试结构在所述TSV上实施高频率测试。
根据本发明所述的测试结构,其中,所述互连包括:重分布层的重分布结构、金属层、或者通孔中的至少一种。
根据本发明所述的测试结构,其中,所述测试结构包括多个测试区域,并且,其中,所述多个测试区域的一个中的所述TSV具有第一尺寸和第一间距,所述多个测试区域的另一个中的所述TSV具有第二尺寸和第二间距,并且,其中,所述第二尺寸或所述第二间距的至少之一分别不同于所述第一尺寸或所述第一间距。
根据本发明所述的一种测试三维集成电路(3DIC)的测试结构,所述测试结构包括:第一基板,具有多个第一穿透硅通孔(TSV)和至少五个测试焊盘,其中,所述多个第一TSV通过互连链接在一起,其中,所述五个测试焊盘中的一个接地到基板,并且,其中,剩下的四个所述测试焊盘中的两个电连接到所述多个第一TSV中的一个,剩下的两个所述测试焊盘电连接到所述多个第一TSV中的另一个;以及第二基板,其中,所述第二基板通过金属凸块接合到所述第一基板。
根据本发明所述的测试结构,其中,所述金属凸块与所述多个第一TSV对准。
根据本发明所述的测试结构,其中,链接所述多个第一TSV的至少一部分互连位于所述第二基板上。
根据本发明所述的测试结构,其中,所述测试结构配置为测试所述多个第一TSV的频率、电阻、电容和泄露。
根据本发明所述的测试结构,其中,所述第二基板包括多个个第二TSV,其中,所述多个第二TSV分别与所述多个第一TSV对准,并且,其中,所述多个第二TSV和所述多个第一TSV链接在一起用于电性测试。
根据本发明所述的测试结构,进一步包括:第三基板,其中,所述第三基板夹在所述第一基板和所述第二基板之间,其中,所述第三基板具有多个第三TSV,其中,所述多个第三TSV分别与所述多个第一TSV对准,并且,其中,所述第一基板、所述第二基板、和所述第三基板通过金属凸块接合在一起。
根据本发明所述的测试结构,其中,所述接地的测试焊盘通过用于接地的互连而接地到所述基板,所述用于接地的互连延伸穿过具有所述多个第一TSV的区域。
附图说明
通过结合附图所作的详细描述,本发明将易于理解,并且相似的参考标号表示相似的结构部件。
图1示出了根据一些实施例的三维集成电路(3DIC)结构的横截面图。
图2A-图2D示出了根据一些实施例的带有测试结构的基板的立体图。
图3A示出了根据一些实施例的器件区域(或者测试区域)的立体图。
图3B示出了根据一些实施例的另一器件区域(或者测试区域)的立体图。
图4A示出了根据一些实施例的TSV的测试区域的俯视图。
图4B示出了根据一些其他实施例的TSV的测试区域的俯视图。
图5A示出了根据一些实施例的接合在一起的两个基板测试结构。
图5B示出了根据一些实施例的接合在一起的多个基板测试结构。
图5C示出了根据一些实施例的设置在上部基板上的探测焊盘。
图5D示出了根据一些实施例的不位于TSV正上方的凸块。
图6示出了根据一些实施例的在芯片区域内(或者通过划片槽限定的边界中)带有测试区域的芯片的立体图。
具体实施方式
应该理解,以下公开内容提供了许多用于实施所公开的不同特征的不同实施例或实例。以下描述组件和配置的具体实例以简化本发明。当然,这仅仅是实例,并不是用于限制本发明。另外,本公开的内容可以在不同实例中重复参考标号和/或字母。这种重复是为了简化和清晰的目的,并且没有在本质上表示各个实施例和/或所讨论配置之间的关系。
图1示出了根据一些实施例的三维集成电路(3DIC)结构的横截面图。图1示出了堆叠在基板20上的管芯A、管芯B、和管芯C,其中,一个管芯堆叠在另一个管芯的顶部上。管芯A、管芯B、和管芯C都带有一个或者多个穿透硅通孔40(TSV),用于管芯间通信和热消散。TSV 40通过金属凸块30连接到其他TSV或者基板20,该金属凸块30可以电连接到每个管芯中的集成电路(未示出)。金属凸块(和金属柱)30可以由各种类型的金属制成,比如焊料(solder)、金、铜等等。
管芯的制造涉及复杂的基板加工操作和控制。为了制备3DIC结构(比如图1中所示的一个),需要对管芯进行预测试,从而区分出好管芯和坏管芯。只有好管芯才能选择用来构造3DIC结构。将好管芯堆叠在一起,从而形成3DIC结构。目前的管芯电性测试主要集中于管芯上的集成电路的电性能。由于TSV和金属凸块的电阻率(比如,在毫欧姆级)和电容(比如,在10-15法拉级)较低,因此,为了直接测试TSV及其相关的金属凸块/柱/支柱的质量和性能,需要高精度自动测试设备(ATE)。目前的ATE没有配置为针对带有TSV的芯片和3DIC的商业测试,这是由于目前的ATE对于测试单个TSV和凸块缺乏高分辨率。
对于带有TSV的基板和3DIC基板所进行的前期测试使得形成得较差的TSV和金属凸块能够在前期阶段被识别出,从而能够校正工艺过程,并且停止已经产生问题的器件封装。已经提出了各种结构,用来分别测试电容、电阻、或者频率。然而,需要不同的结构来测试不同的TSV特性。根据以下一些实施例所描述的测试结构可以用来测试TSV及其相关凸块的各类电特性。
图2A示出了根据一些实施例的带有测试结构250的基板200的立体图。基板200带有五个金属焊盘(编号为201、202、203、204、和205)以及TSV 211、和TSV 212。TSV 211和TSV 212通过重分布层(RDL)的重分布结构220或者顶部金属层相连接。TSV 211和TSV 212以及重分布层220仅仅是实例。存在附加TSV和重分布结构,而没有在图2A中示出。五个金属焊盘(201-205)都是探测焊盘。焊盘201和焊盘202通过互连213和互连214连接到TSV 211,该互连213和互连214可以包括多层金属线和金属通孔。图2A中所示的互连213和互连214仅仅是示意图。互连213和互连214可以通过凸块221与TSV 211相连接,也可以直接与TSV211相连接。类似地,焊盘204和焊盘205连接到TSV 222。焊盘203通过互连217接地到硅基板200。
五个焊盘及其与TSV 211、TSV 212和硅基板200的连接能够测试所连接的TSV结构的各种特性,例如,频率、电阻、电容、和泄露中的一种或者多种。图2B示出了根据一些实施例的用于测试频率的焊盘202和焊盘204。时钟频率从焊盘202上进入,然后返回到焊盘204,该焊盘202连接到TSV(比如,TSV 211、TSV 212)和重分布结构(比如结构220)。在焊盘204测量出输出时钟频率。为了进行测试,可以将多个TSV链接在一起,形成像菊花链一样的结构。这些TSV可以通过重分布结构(比如结构200)相连接。测试结果可以用来检查信号特性的改变,比如通过带有振幅参数(parameter of amplitude)、抖动(jitter)、和/或延迟的眼状图,从而显示出与TSV和接口质量有关的信息。可选地,可以利用焊盘201(而不是焊盘202)来输入时钟频率,利用焊盘205(而不是焊盘204)来测量输出频率。
图2C示出了根据一些实施例的用来进行电阻测试的焊盘201、202、204和205。施加电流,使该电流到焊盘202和焊盘204之间流动。可以通过焊盘201和焊盘205来测试电压降。在这种方法中,在结构上强加电流,并且测量出电压降。可选地,可以在焊盘201上施加电压,从而在焊盘202和焊盘204之间形成电流。在焊盘205上测量出电压降,还测量出电流。在这种方法中,在结构上强加电压,并且测量出电流和电压。基于所收集到的数据,所连接的TSV的电阻可以通过四点探针(four-point-probes)方法计算出。如上所述,单个TSV的电阻太小,以至于无法通过ATE探测出。通过将多个TSV链接(chain)在一起,信号被放大,从而能够测量出电阻。用于电流测量和电压测量的焊盘可以转换。例如,可以在焊盘202上施加电压,在焊盘204上测量出电压,还可以在焊盘201上施加电流,在焊盘205上测量出电压。在电阻测试期间,焊盘203断开。
图2D示出了根据一些实施例的用于测试电容和泄露的焊盘202、和焊盘203。将电压施加到焊盘202和焊盘203,其中,施加到一个焊盘的电压高于施加到另一个焊盘的电压,从而将连接到焊盘202和焊盘203以及焊盘202和焊盘203周围的结构预充电。然后,可以通过吸收电流和测量焊盘202上的放电率(比如通过测量电压和时间常数)计算出电容。使用焊盘202仅仅是一个实例。可选地,焊盘201、204和205代替焊盘202来进行测量。为了测量TSV的泄露,将电压施加到焊盘203,在焊盘202上测量电流作为泄露量。可选地,可以将电压施加到焊盘203,并且在焊盘230上测试电流。该测试能够探测出连接到焊盘202的任意TSV(比如TSV 211和TSV 212)的泄露。类似地,使用焊盘202仅仅是一个实例。可选地,焊盘201、204和205可以用来代替焊盘202,用来进行测试。
图2A-图2D中所示出的测试结构是示意图,这些示意图示出了如何利用探测焊盘(或者测试焊盘)对TSV之间的重分布结构、以及连接到TSV的金属凸块实施特性测试。如上所述,单个TSV的电阻率、电容、和泄露可能太小,以至于无法利用现有的电子测试器测量出来。为了能够测量出电阻率、电容、和泄露,可以将更多的TSV链接在一起,从而增加用于检测的信号级别。
图3A示出了根据一些实施例的器件区域(或者测试区域)300的立体图。为了进行上述电阻、电容、频率、和泄露的测试,多个TSV(比如TSV211和TSV 218)链接在一起。图3A示出了TSV如何通过底部上的重分布结构(比如,结构231)、顶部上的重分布结构(比如,结构232)链接在一起。链接在一起的多个TSV可以为任意数量(较小或者较大均可)。在一些实施例中,链接在一起的多个TSV的数量处于大约10到大约100的范围内。在一些其他实施例中,链接在一起的TSV的数量处于大约50到大约200的范围内。在又一些其他实施例中,链接在一起TSV的数量处于大约100到大约300的范围内。
图3A中所示出的测试结构包括在同一层中的TSV。在一些实施例中,为了进行测试,链接(或者连接)在一起的TSV位于多层上,或者位于多个芯片上。图3B示出了根据一些实施例的另一器件区域(或者测试区域)350的立体图。在器件区域350中有两个基板(或者芯片)351和352。基板351和基板352中的多个TSV链接在一起,用于进行上述电阻、电容、频率、和泄露测试。
图3B示出了如何将TSV通过基板351底部上的重分布结构(比如,结构353)和顶部上的重分布结构(比如,结构354)链接在一起。由于不同层(或者基板)上的TSV(比如,TSV 355和TSV 356)通过凸块(比如,凸块357、凸块258)、或者其他类型的导电结构相互连接,还要对于所形成的凸块的质量和特性进行测试。链接在一起的多个TSV可以为任意数量(较小或者较大均可)。在一些实施例中,链接在一起的多个TSV的数量处于大约10到大约100的范围内。在一些其他实施例中,链接在一起的TSV的数量处于大约50到大约200的范围内。在又一些其他实施例中,链接在一起TSV的数量处于大约100到大约300的范围内。图3A和图3B中的箭头示出了在焊盘202和焊盘204的测试中,电流的流动方向,图3A和图3B中的结构仅仅是实例。还可以使用其他排列方式。
上述器件区域350包括两个基板。可选地,堆叠在一起的基板数量可以多于两个,比如三个或者四个。这些多层基板(或者芯片)通过TSV及其相关的金属凸块进行互连,这些TSV的质量和特性可以通过类似于上述的结构测试出。可以在将芯片堆叠在下面芯片上方之前和/或之后,实施TSV测试。
图4A示出了根据一些实施例的TSV的测试区域400的俯视图。图4示出了测试区域410、420、和430。在一些实施例中,在区域400中,存在有其他测试区域类似于测试区域410、420、和430。在测试区域410、420、和430中,存在至少5个测试焊盘,类似于上面所述的焊盘201-205。例如,测试410带有测试焊盘401、402、403、404、和405,类似于测试焊盘201、202、203、204、和205。然而,测试区域410、420、或者430不需要每个都具有测试焊盘。图4中的两个或者三个区域中的TSV可以链接在一起,并且可以通过图4中所示的三组测试焊盘中的一组进行测试。在一些实施例中,测试焊盘不需要排列为彼此相邻。例如,测试焊盘401、402、和403可以与焊盘424和425一同用于实施上述电性测试。
存在有上部互连(用实线标记,比如线406),连接TSV(比如,TSV409和TSV 451)的上部。还存在由下部互连(用虚线标记,比如线407),连接TSV(比如,TSV 408和TSV 409)的下部。测试区域410、420、和430中的TSV链接在一起,从而增加了信号级别(或者信号密度)。如上述图3B,用于连接TSV的互连(比如互连353和互连354)可以是一层中的金属线或者可以涉及不同层的金属线和通孔。图4示出了根据一些实施例的连接到区域410的探测焊盘404的接地互连(比如,互连452、互连453)在测试区域中延伸(spread out)。互连的延伸布局为区域410中的TSV提供了充分接地。图4中所示的接地线(比如互连452和互连453)的排列仅仅是一个实例。还可以使用其他排列方式或者布局,只要TSV链接在一起。
如图4中所示,由于每个测试区域都有其自身的测试焊盘,因此测试区域410、420和430都可以独立进行测试。测试区域420带有测试焊盘411-415,该测试焊盘411-415类似于测试焊盘401-405,测试区域430带有测试焊盘421-425,该测试焊盘421-425也类似于测试焊盘401-405。在一些实施例中,测试区域410的TSV 461通过互连465连接到测试区域420的TSV 462。该连接使得测试区域410和测试区域420中的TSV既可以一起进行测试,又可以分别进行测试。例如,如果使用了测试区域410的测试焊盘401和测试焊盘402以及测试区域420的测试焊盘414和测试焊盘415,则可以对两个区域的TSV一起进行频率、电阻、电容、和泄露测试。这种连接方式增加了测试中TSV的数量。类似地,区域420的TSV 463可以通过互连466连接到区域430的TSV 464。这种连接方式使得区域430中的TSV能够有与其他测试区域(比如,区域410和区域420)中的TSV一起进行测试。
除了测试区域410、420、和430中的测试焊盘401-415、411-425、和421-425,还存在有其他测试焊盘,比如测试焊盘431-435,该测试焊盘431-435能够对测试区域(比如,测试区域410)中TSV的子集进行测试。例如,一个或者多个测试焊盘431-436可以用于与一个或者多个测试焊盘401-405相结合,从而能够理解多个TSV如何需要链接在一起从而产生可以被探测出的测试信号。在图4中,测试焊盘431-436与测试区域410相邻。可选地,可以将附加测试焊盘置于测试区域410和测试区域420,或者其他区域之间,从而连接到测试区域400中的其他TSV。附加测试焊盘431-436还可以用于诊断基板或者图形效应(pattern effect)的工艺问题。例如,测试区域410的测试焊盘431-435或者测试焊盘401、402、436和431可以用于测试测试区域410左侧的TSV(比如,TSV 471-475及其之间链接的TSV)的电阻率,从而能够理解,如果TSV形成在重复图案的边缘,则产生的结果与测试区域400中的其他区域相比不同。
在一些实施例中,测试区域400还可以包括两个附加测试焊盘441、442、以及频率(或者时钟)乘法器480和分频器490、乘法器480连接到测试焊盘441和TSV 408(例如,位于将要进行测试的链的始端的TSV),除法器490连接到测试焊盘442和TSV 461(例如,位于将要就进行测试的链的末端的TSV)。该结构能够测试TSV上的高频(比如,频率大于或者等于大约5GHz)输入的效果。高频测试对于3DIC来说非常重要。进入到测试焊盘441的频率可以通过倍频器480乘以一个较大的系数,并且穿过TSV链。在频率通过除法器490分开进行除操作之后,可以在测试焊盘442测量出输出频率。
可选地,大测试区域(test area)中的不同的小测试区域(test region)所具有的TSV和凸块的间距(pitch)和尺寸可以不同。根据一些实施例,图4B示出了测试400’,该测试400’与图4A中的测试结构400相似,带有测试区域420’,该测试区域420’带有尺寸和间距较小的TSV和凸块。TSV(比如,TSV 462’和TSV 463’)的尺寸小于测试区域410和测试区域430中的TSV的尺寸。类似的,凸块(未示出)的尺寸也可以不同。测试区域420’中的间距(两个相邻TSV的中心之间的间距)与测试区域410和测试区域430中的间距不同(更小)。图4B中所示出的实例的TSV和间距更小。可选地,TSV和/或凸块的尺寸和间距可以大于其他测试区域。
图4A示出了测试区域400的俯视图。根据一些实施例,测试区域400可以形成在基板上,所有TSV都位于一个基板上。可选地,测试区域400可以以类似于图3B的方式形成在两个或者更多基板上,其中,将位于两个基板上的TSV相连接而进行测试。
图5A示出了根据一些实施例的通过凸块连接在一起的两个基板(510和520)的测试结构。下部基板510带有TSV(比如,TSV 501-504)和用于连接TSV的重分布结构(比如,结构505和506),以及用于外部连接的凸块(比如,凸块511-514)。在基板(或者芯片)510上方,存在有带有凸块(比如,凸块521-524)的基板520,该基板520与基板510上的凸块(比如凸块511-514)相接触。在基板520上,还存在有重分布结构(比如,结构525),与凸块相连接。在一些实施例中,基板520上的TSV与基板510上的TSV以图3B中所描述的方式相链接。图5A的横截面图示出了基板510上的探测焊盘530。探测焊盘530可以是以上图2A-图3B中所描述的任意探测焊盘。其他探测焊盘可以以图2A-图4B中所描述的方式设置于探测焊盘530旁边。
可选地,探测焊盘可以位于基板520上,比如探测焊盘540。图5C示出了根据一些实施例的设置在基板520上的探测焊盘540。其他探测焊盘也可以以图2A-图4B所描述的方式设置在探测焊盘540旁边。探测焊盘530和探测焊盘540电连接到基板510和基板520中的金属凸块和TSV。
对于上述3DIC,凸块对准在TSV的正上方。然而,这些图块并不需要对准在TSV的正上方(或者正下方)。图5D示出了根据一些实施例的不位于TSV正上方的凸块。存在连接结构(比如,结构531-534),将凸块与TSV相连接。
在一些实施例中,在基板520接合到基板510之前,探测焊盘530可以用于测试基板510,从而确定TSV或者TSV/凸块是否适当地形成而具有良好的电性测试结果。在基板520接合到基板510之后,可以测试这两个基板之间的接合质量。如果基板520带有TSV,则TSV的质量和特性也可以通过比较预接合结果和后接合结果而进行测试。
图5B示出了根据一些实施例的带有多个基板的器件区域,其中,每个基板的顶部位于另一基板的顶部上。图5B中的结构类似于图5A中的结构,差别为,在图5B中,在基板510和基板520之间堆叠有附加基板550和附加基板560。图5B中的结构示出了带有TSV的多层芯片,每个TSV可以堆叠在另一TSV的顶部,TSV可以链接在一起,从而能够进行多个层测试和/或单个层测试。如果在测试期间,发现芯片出现问题,可以将该芯片移除并且替换为能够正常运转的芯片。另外,可以确定导致芯片损坏的原因,从而防止生产线上再发生工艺错误。这种中间层测试有利于在接合步骤中确定损坏的芯片,而不是一直等到整个封装过程结束才确定。另外,这种中间级测试用于早早地确定出现问题的源头,从而防止再出现工艺错误,进而节省了成本。
图6示出了根据一些实施例的在芯片区域内(或者通过划片槽限定的边界中,并且与产品器件在同一侧)带有测试区域650的芯片610的立体图。测试区域650带有上述TSV和凸块测试结构。在一些实施例中,测试区域的结构使得TSV和凸块能够进行2D和3D测试。如果涉及3D测试,则接合到另一芯片620的芯片带有对应的测试区域,该测试区域带有TSV和凸块,该TSV和凸块连接到该芯片。通过将多个TSV链接在一起,当前的ATE可以用于实施该测试。现有的ATE的实例包括,但不限于,Verigy(惠瑞杰)出品的HP93000、Advantest(爱德万)出品的T2000、以及Teradyne(泰瑞达)出品的U-Flex。
上述实施例提供了用于测试基板上或者3维集成电路(3DIC)中的穿透硅通孔(TSV)的特性的方法和结构。将TSV链接在一起,从而增大了电信号,如果只测试单个TSV,电信号无法通过自动测试设备探测出。五个测试焊盘能够用于测试频率、电阻率、电容、和泄露。一个测试焊盘接地。两个测试焊盘中电连接到位于链始端的TSV,另外两个焊盘电连接到位于链末端的TSV。测试结构可以延伸到3DIC中的测试TSV和凸块。在封装之前和3DIC封装工艺期间,对于基板上的TSV进行预测试,可以降低用损坏部件继续封装期间的风险,并且还能够早早地确定生产线上出现的问题。
在一个实施例中,提供了一种用于基板上的链接穿透硅通孔(TSV)的测试结构,该测试结构包括:多个TSV,从基板的第一表面延伸到基板的第二表面,第二表面相对于第一对面,其中,多个TSV通过互连而链接在一起,以及多个测试焊盘,其中,多个测试焊盘中的至少一个接地到基板,并且,其中,剩下的多个测试焊盘中连接到链接TSV,或者接地。
在另一实施例中,提供了一种用于测试三维集成电路(3DIC)的测试结构。该测试结构包括:第一基板,带有多个第一穿透硅通孔(TSV)和至少五个测试焊盘,其中,多个第一TSV通过互连链接在一起,其中,五个测试焊盘中的一个接地到基板,并且,其中,剩下的四个测试焊盘中的两个电连接到多个第一TSV中的一个,剩下的两个测试焊盘电连接到多个第一TSV中的另一个;以及第二基板,其中,第二基板通过金属凸块接合到第一基板。
在公开的方法和系统的布置、操作、和细节中,本领域技术人员可以很容易作出各种修改、改变、和变化。尽管上述发明为了能够更清楚地理解而进行了详细描述,但是很明显,可以做出一些改变和修改而不超出附加权利要求的范围。因此,本实施例可以认为是说明性的而非限定性的,本发明并不限于本文所给出的细节,可以在附加权利要求及其等效范围内和对所列举的实施例进行修改。
Claims (20)
1.一种用于在基板上链接穿透硅通孔TSV的测试结构,所述测试结构包括:
多个TSV,从所述基板的第一表面延伸到相对于所述第一表面的所述基板的第二表面,其中,所述多个TSV通过互连而链接在一起,以及
多个测试焊盘,其中,所述多个测试焊盘中的至少一个接地到所述基板,并且,其中,剩下的所述多个测试焊盘或者与所述链接的TSV连接,或者接地。
2.根据权利要求1所述的测试结构,其中,链接所述多个TSV的所述互连包括重分布层中的结构。
3.根据权利要求1所述的测试结构,其中,多个测试焊盘包括五个测试焊盘,一个测试焊盘接地到所述基板,两个测试焊盘连接到所述链接的TSV的一端,剩下的两个测试焊盘链接到所述链接的TSV的另一端。
4.根据权利要求1所述的测试结构,其中,配置所述测试结构以实施电性测试,从而确定所述基板上的所述多个TSV的质量和特性。
5.根据权利要求1所述的测试结构,其中,配置所述测试结构以测试所述链接的TSV的频率、电阻、电容和泄露。
6.根据权利要求1所述的测试结构,其中,所述多个TSV的数量等于或者大于2。
7.根据权利要求1所述的测试结构,其中,所述多个TSV以菊花链方式链接在一起。
8.根据权利要求3所述的测试结构,包括:多于一个测试区域,并且,其中,每个所述测试区域都有所述的五个测试焊盘。
9.根据权利要求8所述的测试结构,其中,所述基板的所述多个TSV在每个所述测试区域中链接在一起,并且链接在一个所述测试区域中的所述TSV进一步与在另一测试区域内链接的所述TSV相链接,从而能够测试每个测试区域中的TSV以及穿过多个所述测试区域的所述链接的TSV。
10.根据权利要求1所述的测试结构,其中,所述测试结构位于所述基板的管芯内。
11.根据权利要求1所述的测试结构,进一步包括:
倍频器;以及
分频器,其中,所述倍频器和所述分频器能够连接到所述链接的TSV,从而允许通过所述测试结构在所述TSV上实施高频率测试。
12.根据权利要求1所述的测试结构,其中,所述互连包括:重分布层的重分布结构、金属层、或者通孔中的至少一种。
13.根据权利要求1所述的测试结构,其中,所述测试结构包括多个测试区域,并且,其中,所述多个测试区域的一个中的所述TSV具有第一尺寸和第一间距,所述多个测试区域的另一个中的所述TSV具有第二尺寸和第二间距,并且,其中,所述第二尺寸或所述第二间距的至少之一分别不同于所述第一尺寸或所述第一间距。
14.一种测试三维集成电路3DIC的测试结构,所述测试结构包括:
第一基板,具有多个第一穿透硅通孔TSV和至少五个测试焊盘,其中,所述多个第一TSV通过互连链接在一起,其中,所述五个测试焊盘中的一个接地到基板,并且,其中,剩下的四个所述测试焊盘中的两个电连接到所述多个第一TSV中的一个,剩下的两个所述测试焊盘电连接到所述多个第一TSV中的另一个;以及
第二基板,其中,所述第二基板通过金属凸块接合到所述第一基板。
15.根据权利要求14所述的测试结构,其中,所述金属凸块与所述多个第一TSV对准。
16.根据权利要求14所述的测试结构,其中,链接所述多个第一TSV的至少一部分互连位于所述第二基板上。
17.根据权利要求14所述的测试结构,其中,所述测试结构配置为测试所述多个第一TSV的频率、电阻、电容和泄露。
18.根据权利要求14所述的测试结构,其中,所述第二基板包括多个个第二TSV,其中,所述多个第二TSV分别与所述多个第一TSV对准,并且,其中,所述多个第二TSV和所述多个第一TSV链接在一起用于电性测试。
19.根据权利要求14所述的测试结构,进一步包括:第三基板,其中,所述第三基板夹在所述第一基板和所述第二基板之间,其中,所述第三基板具有多个第三TSV,其中,所述多个第三TSV分别与所述多个第一TSV对准,并且,其中,所述第一基板、所述第二基板、和所述第三基板通过金属凸块接合在一起。
20.根据权利要求14所述的测试结构,其中,所述接地的测试焊盘通过用于接地的互连而接地到所述基板,所述用于接地的互连延伸穿过具有所述多个第一TSV的区域。
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