CN102386158B - 半导体装置及其制法 - Google Patents

半导体装置及其制法 Download PDF

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Publication number
CN102386158B
CN102386158B CN201110049451.0A CN201110049451A CN102386158B CN 102386158 B CN102386158 B CN 102386158B CN 201110049451 A CN201110049451 A CN 201110049451A CN 102386158 B CN102386158 B CN 102386158B
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CN102386158A (zh
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林正忠
刘重希
周孟纬
林国诚
吕文雄
黄见翎
黄英叡
陆德源
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置及其制法，特别是关于一种焊料柱状凸块。通过电镀导电材料于集成电路端点之上，以形成导电材料的柱状物，亦即柱状凸块连接点系形成于输出/输入端点之上。柱状凸块的底端部分具有比上段部分更宽的宽度。柱状凸块的底部部分的剖面图可形成梯形、矩形或倾斜形状。焊料材料可形成于柱状结构上表面上。因此，焊接柱状凸块的成品形成细微间距(fine pitch)封装焊料连接，此结构比现有技术更具可靠度(reliable)。

Description

半导体装置及其制法
技术领域
本发明涉及一种集成电路，特别是涉及一种柱状凸块结构与其制法。
背景技术
对于高阶电子电路，特别是对于在半导体制造工艺中作为集成电路(integrated circuits，ICs)的电路而言，需要使用一柱状物(pillar)或圆柱状物(column)位于集成电路端点(terminal)之上，以形成一柱状焊料凸块(pillarsolder bump)或圆柱状焊料凸块(column solder bump)或焊接圆柱接触(soldercolumn contact)。在一封装(packaging)或导线(interconnection)的现有倒装芯片(flip chip)方法中，焊料凸块(solder bump)用于将一单晶集成电路(其中该单晶集成电路(monolithic IC)可能是一具有有源或无源电路元件及连接点(connections)形成于其上的硅基板，或者也可能是其他半导体基材，包括砷化镓(gallium arsenide，GaAs)、绝缘层上覆硅(silicon-on-insulator，SOI)及硅锗(silicon germanium))的外部端点(external terminal)耦合至一封装基板或电路板。有时候也会加入一中介层(interposer)，并将集成电路固定于中介层上，接着再将具有集成电路的中介层固定于该电路板或封装基板上。中介层用于提供裸片(die)与应力消除装置(stress relief)较佳的热匹配性(thermalmatching)。这些集成电路元件可能具有数十个或数百个输入及输出端点，这些端点用于接收或传送信号及/或耦合至电源供应连接点。在某些集成电路设计中，这些端点设置于集成电路的周边位置，并且远离有源电路(activecircuitry)。在较高阶或较复杂的集成电路中，这些端点可设置于有源区域之上，并且位于集成电路内部的有源元件之上。在存储器集成电路中，有时候会使用一中心垫(center-pad)。
在一倒装芯片应用中，集成电路是以面朝下(翻转)的方向设置于基板上。端点开口形成于一保护绝缘层中，其中该保护绝缘层又称为钝化层且位于包括集成电路的晶片上，其中钝化层位于集成电路元件的表面上。集成电路的导电性输入/输出端点暴露于这些开口中。焊料(包括无铅焊接材料)凸块、焊接圆柱(solder column)或焊球设置于这些端点之上。可利用导电材料自集成电路的表面延伸，以形成半球状或圆柱状焊料凸块。这些焊料凸块或焊接圆柱接着用于形成集成电路的外部接触。这些焊料凸块可利用“晶片规模(waferscale)”或“晶片等级(wafer level)”工艺方法形成于完整的集成电路上，或者，可在晶片切割成个别的集成电路元件(又称为晶块，dice)之后加入焊料连接点(solder connector)。目前，采用晶片等级(wafer level)的凸块加工(bumpingoperation)技术有逐渐增加的趋势。
总之，一热焊接回焊工艺(thermal solder reflow process)通常会使焊料凸块熔化随后回焊，以完成倒装芯片集成电路与基板之间的机械接触与电性接触。基板可能是树脂或环氧化物、层压板(laminated board)、薄膜、印刷电路板或是其他硅元件。在热回焊(thermal reflow)的过程中，焊料凸块、焊球或焊接圆柱(这些焊料可能是含铅焊料或无铅焊料)先熔化随后冷却，借以在集成电路的端点与基板之间形成永久机械性固定且电性导通的连接。已结合的倒装芯片集成电路与基板接着被封装成一单一集成电路。一般而言，可采用球状栅格阵列封装(ball grid array)或针脚栅格阵列封装(pin grid array)完成这些倒装芯片封装。另外，在一多晶模块中，倒装芯片可与其他同为倒装芯片的集成电路结合，或者可以使用焊线接合(wire bond connection)。例如，有时候存储器元件，例如快闪非易失性元件(FLASH nonvolatile device)，以及利用快闪元件进行程序或数据存储的处理器(processor)，两者结合在单一封装元件之中。集成电路元件可利用一较大的基板、中介层或电路板采取垂直堆叠或水平并排的方式设置。
在目前的晶片等级(wafer level)工艺中，晶片通常通过一晶片规模(waferscale)的程序进行凸块加工。至少直到焊料凸块完全形成于晶片的每一个元件上，该晶片被视为一个单位进行处理，接着可进行一切割程序，以将集成电路分割成个别的晶块(dice)或裸片(dies)。之后这些经过凸块接合的裸片各自进行加工处理。在一倒装芯片应用中，翻转裸片使其面向封装基板或中介层，并将焊料凸块对准位于基板上的焊接垫(solder pad)，进行一热回焊(thermalreflow)工艺使焊料凸块熔化，在裸片(die)的端点与基板的端点之间形成一电性及机械性连接，借此完成组装(assembly)程序。组装(assembly)程序通常包括在回焊之后添加一底部填充(underfill，UF)材料，借以在该元件使用时所产生的热循环过程中更进一步地保护焊接连接点。
由于工业界进一步地推动晶片级工艺(wafer level processing，WLP)，导致在晶片等级下实施的封装步骤增加，因此在对个别晶块实施的封装步骤随之减少。然而，各种晶片等级及裸片加工等级的步骤目前仍受到采用。
最近，半导体工业已趋向采用“无铅(lead free)”封装及无铅元件连接点技术。此趋势逐渐致使厂商采用无铅焊料凸块及无铅焊球形成集成电路与封装之间的连接。这些无铅焊料由锡(tin)或锡合金(tin alloy)所组成，其中锡合金包括，例如银(silver)、镍(nickel)、铜(copper)或其他材料。这些无铅焊料成分为共熔的(eutectic)，亦即，其中所有材料皆具有一相同的熔点。相较于使用含铅焊料或焊球，使用无铅焊料对环境、从业人员以及消费者皆较为安全。然而，使用无铅焊料的焊接连接点的品质与可靠度始终无法满足需求。
此外，当元件尺寸持续下降，集成电路上的端点的脚距(pitch)也随之降低。相邻凸块之间的桥接(bridging)现象将导致电性短路。另外，焊料凸块容易受到机械应力而变形，因此在倒装芯片基材组装的完成品中的凸块高度可能不一致，且凸块经过再熔解与回焊程序之后，凸块之间的间距可能也不均等。再者，在密集脚距的元件中使用底部填充(underfill，UF)与焊料凸块，将于底部填充(underfill，UF)材料中留下孔隙(void)，进而产生其他问题，例如龟裂(cracking)及热点(hot spot)等等。
对于脚距较密集的元件而言，解决方法之一为利用具有焊料(通常为无铅焊料)顶盖(solder cap)的铜或其他导电柱状结构取代焊料凸块。除了铜(Cu)之外，也可使用其他导电性材料，例如镍(Ni)、金(Au)及钯(palladium，Pd)等等，此外，也可使用上述材料的合金。这些导电柱状结构形成一种称为“铜柱凸块(copper pillar bump)”的连接点。铜柱凸块也可包括铜合金及其他含铜导电体，或者此种柱状凸块可由其他导电材料组成。此种柱状凸块的优点之一在于导电柱状结构不会在回焊(reflow)的过程中完全变形。焊料顶盖形成一在热回焊(thermal reflow)过程中会熔化的球状顶端，而导电圆柱的柱状部分则维持其原有形状。此种铜柱的导热性较现有的焊料凸块更佳，因此可增加热量的传输。相较于现有的焊料凸块，此种直径较窄的铜柱可应用于脚距较密集的阵列，而不会产生因桥接效应所引起的短路，同时也可避免其他问题，例如凸块高度不均。由于集成电路元件的尺寸持续缩小，端点之间的脚距以及相对应的柱状凸块之间的脚距也将持续降低。随着端点之间的脚距持续降低，可以预期的是，对于使用柱状凸块时因热应力(thermal stresses)所引起的各种问题将随之增加。
发明内容
为克服现有技术的缺陷，本发明提供一种半导体装置，包括：一半导体基板，其中该半导体基板具有至少一输入/输出端点位于其表面之上；一柱状结构设置位于该至少一输入/输出端点之上，其中该柱状结构包括：一底端部分接触该输入/输出端点；一上段部分具有一第一宽度；以及一基底部分位于该底端部分之上并具有一大于该第一宽度的第二宽度。
本发明也提供一种半导体装置的制法，包括以下步骤：形成输入/输出端点于一半导体基板的一侧表面上，以作为一外部连接点；沉积一钝化层位于该输入/输出端点之上；图案化该钝化层以形成开口，以暴露该输入/输出端点的一部分；沉积一籽晶层位于该钝化层之上；沉积一光致抗蚀剂层位于该籽晶层之上；显影该光致抗蚀剂层以于该光致抗蚀剂层中形成光致抗蚀剂开口位于该输入/输出端点之上；图案化该光致抗蚀剂开口的底端部分，以形成鸟喙状图样位于该开口的底部，该鸟喙状图样自该开口向外延伸；以及形成一导电材料于该光致抗蚀剂开口之中；其中该导电材料形成一柱状结构自该籽晶层向上延伸，其中该柱状结构包括一上段部分具有一第一宽度，以及一基底部分具有大于该第一宽度的一第二宽度。
本发明另提供一种半导体装置的制法，包括以下步骤：形成输入/输出端点于一半导体基板的一侧表面上，以作为一外部连接点；沉积一钝化层位于该输入/输出端点之上；图案化该钝化层以形成开口，以暴露该输入/输出端点的一部分；沉积一光致抗蚀剂层位于该钝化层之上；显影该光致抗蚀剂层以于该光致抗蚀剂层中形成光致抗蚀剂开口位于该输入/输出端点之上，其中该光致抗蚀剂开口的作用在于定义出一基底部分及一上段部分；以及形成一导电材料于该光致抗蚀剂开口之中；其中该导电材料形成一柱状结构自该籽晶层向上延伸，其中该柱状结构包括一上段部分具有一第一宽度，以及一基底部分位于该钝化层之上，其中该基底部分具有大于该第一宽度的一第二宽度。
本发明能够减少或解决使用现有柱状凸块时，因材料中的热应力所引起的各种问题。此外，焊接柱状凸块的成品形成细微间距(fine pitch)封装焊料连接，此结构比现有技术更具可靠度(reliable)。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1为一剖面图，用以说明本发明一实施例的柱状凸块结构。
图2为一剖面图，用以说明本发明形成圆柱状凸块的实施例的中间工艺结构。
图3为一剖面图，用以说明本发明图2进行后续工艺的结构。
图4为一剖面图，用以说明本发明图3进行后续工艺的结构。
图5为一剖面图，用以说明本发明图4进行后续工艺的结构。
图6为一剖面图，用以说明本发明形成圆柱状凸块的另一实施例的中间工艺结构。
图7为一剖面图，用以说明本发明形成圆柱状凸块的又一实施例的中间工艺结构。
图8为一表格，用以比较现有柱状凸块与本发明柱状凸块的失效模式评估(failure mode evaluation)。
【主要附图标记说明】
61～柱状结构
63～上段圆柱状部分
64～斜角区域
65～基底部分
66～底部矩形部分
67～外部倾斜表面
H1～基底部分高度
W1～上段部分宽度
W2～基底部分延长宽度
73～光致抗蚀剂层
75～开口
76～端点
77～半导体基板
79～钝化层
81～阻挡层
83～籽晶层
85～鸟喙状开口
91～铜柱
93～预焊料层
95～焊料层
96～矩形底端部分
101～柱状结构
102～基底部分
104～矩形底端部分
105～柱状结构
106～上段部分
H1～基底部分高度
W1～上段部分宽度
W2～基底部分延长宽度
W3～基底部分宽度
W1～柱状结构顶端宽度
W3～柱状结构底端宽度
具体实施方式
本发明所公开的实施例提供新颖的方法与设备，用于降低使用铜柱凸块于封装的集成电路中的热应力(thermal stresses)，通过改变铜柱的形状，以减少或解决使用现有柱状凸块时，因材料中的热应力所引起的各种问题，所有实施例将在下文中详述。
图1为一剖面图，显示本发明所公开的一柱状结构61的第一实施例。需注意的是，在本实施例及整篇说明书中，剖面图用以显示柱状结构的实施例；然而，这些柱状结构为环状。此外，整篇说明书中提及“垂直”及“矩形(rectangular)”等辞汇，是广义地包括在半导体制造工艺范围内所形成的大体上垂直及大体上矩形(rectangular)的特征。
柱状结构61的上段部分(upper portion)63形成于一较宽的基底部分(baseportion)之上，其中该基底部分位于图中虚线区域内并且标示为65。基底部分65的倾斜外部表面(sloped exterior surface)67自较宽的基底部分65向上倾斜至上段圆柱状部分(upper columnar portion)63。基底部分65的外部表面(exterior surface)67与上段圆柱状部分63的垂直边于区域64以一大于90°的角度相交。基底部分65的剖面为一梯形状结构。一底部矩形部分66位于梯形状基底65的下方。此底部部分66向下延伸至集成电路的端点(图中未显示)。
针对采用本实施例的柱状结构形状而完成组装的集成电路，利用各种材料进行热应力的相关研究，结果显示对大多数的层状结构而言，例如超低介电常数(extreme low-k dielectric，ELK)层、凸块底层金属(under bumpmetallization，UBM)层、底部填充(underfill，UF)、预焊料(pre-solder)及焊料凸块，采用本实施例中如图1所示的柱状结构形状，所观察到的热应力较采用现有技术的现有柱状结构形状的热应力更低。
在图1中，实施例61可以是，例如，一柱状结构，其上段部分(upper portion)63具有一宽度W1约为85μm。基底部分65的剖面形成一梯形。基底部分65较上段圆柱状部分(upper columnar portion)63略宽。在本实施例(仅用于示范而非限制)中，基底具有一延长部分，其中该延长部分在剖面图的两侧各较其上方的圆柱状部分(columnar portion)延长一宽度W2。在一实施例中，W2为5μm，本实施例中基底部分65的宽度为95μm。因此基底部分的宽度较上段部分的宽度大10％；且基底部分的宽度大于上段部分的宽度的程度可多于或少于10％。此外，相较于上段部分，基底部分65的高度相当小；在本实施例中，高度H1约为3μm。基底部分的外部倾斜表面(exterior sloped surface)67自基底部分65最宽的部分向上倾斜至圆柱状上段部分(columnar upperportion)63，并且与圆柱状上段部分(columnar upper portion)63的垂直边相交于斜角区域64，且具有一相交角度大于90°。上段部分的高度、宽度以及基底(base)的宽度可依本实施例进行相当程度的修改。例如，高度H1可为2-10μm。例如，宽度W1可为50-110μm。宽度W2可为基底宽度W1的约5％。例如，宽度W2的变化范围可为5-11μm。
图2为一剖面图，显示形成图1的柱状结构的一中间工艺步骤。在图2中，光致抗蚀剂73经过沉积、曝光及显影，并且形成一开口75于半导体基板77之上。一集成电路可形成于半导体基板77之中。端点76通过一位于钝化层(passivation layer)79之中的开口而得以暴露在外，其中该端点76耦合至位于集成电路中的电路(图中未显示)，以形成一电性连接至电路。钝化层(passivation layer)79为一介电材料(dielectric)，例如聚酰亚胺(polyimide)、氮化物(nitride)、氧化物(oxide)或其他用于钝化的材料。阻挡层(barrier layer)81沉积于基板77(在此一工艺步骤中可能仍为晶片型态，或为一独立的裸片)之上，且一籽晶层(seed layer)83溅镀或沉积于阻挡层之上；这些层状构造共同形成一凸块底层金属(under bump metallization，UBM)层。光致抗蚀剂因此形成一垂直圆柱状的开口，并且使籽晶层83之上段表面的选定部分得以暴露在外。在一典型的实施例中，用以形成铜柱的籽晶层通常也是铜或铜合金，因此通常会在表面上形成氧化铜(copper oxide，CuO2)。阻挡层81与籽晶层83共同形成柱状结构的凸块底层金属(UBM)层。凸块底层金属(UBM)层具有多种功能。阻挡层81可提供一扩散阻挡并提供一粘着层，以改善后续各层的粘着性。籽晶层83用于后续的电镀步骤并且也可当作一额外的粘着层。
图3为一剖面图，显示本发明所公开的方法实施例经过图2之后续其他工艺步骤的结构。在图3中，光致抗蚀剂73具有一鸟喙状(bird beak)开口85，例如在图中，形成于开口75的底部，且位于籽晶层83的上表面，其中鸟喙状开口形成比开口75的上段部分更宽的基底部分。当此开口在后续的电化学电镀(electrochemical plating，ECP)工艺中被铜柱所填充，将可观察到本柱状结构实施例中的基底部分的梯形剖面(如图1所示)。此外，与现有技术中的凸块底层金属(UBM)材料相比，受到填充铜柱的基底所覆盖的凸块底层金属层材料宽度较宽，因而增加位于铜柱下方的凸块底层金属层材料余留量。
在第一方法实施例中，可在一电化学预镀(pre-ECP)步骤中利用即时原位(in-situ)的方法形成开口75的喇叭形底端部分(flared bottom portion)于光致抗蚀剂层(PR layer)73中。在称为“干式蚀刻(dry etch)”的工艺中，可进行等离子体处理，例如利用微波或无线电波(radio frequency，RF)能量进行氮气/氢气(N2/H2)等离子体气体处理。对位于开口75底部而暴露在外的籽晶层83的上表面进行等离子体处理，可从籽晶层移除氧化铜(CuO2)，同时也将在开口75底部的角落形成一鸟喙状(bird beak)开口。在等离子体处理之后，进行一电化学电镀(ECP)工艺，以低起始沉积速率(low initial deposition rate)进行铜的沉积(例如，起始沉积速率可介于0.1-0.5ASD之间。单位ASD定义为每单位面积内的电流量，安培/平方公寸(amperes/dm squared，A/dm2))。
低起始沉积速率将产生一缺口填补(gap-filling)效应，使得欲镀的铜柱材料能够填充于光致抗蚀剂开口75与铜材料所形成的鸟喙状开口85之中，并且可借此在基底部分形成一梯形剖面。
在另一方法实施例中，可在一电化学预镀(pre-ECP)步骤中，利用即时原位(in-situ)的方法形成开口75的喇叭形底端部分于光致抗蚀剂层(PR layer)73中，其中即时原位(in-situ)的方法是利用湿式清洁工艺(wet clean process)。在湿式工艺中，可使用溶液从位于开口75底部的籽晶层83移除氧化铜(CuO2)，或是利用湿式清洁剂(wet cleans)从籽晶层移除氧化铜(CuO2)。也可使用其他湿式清洁剂，例如稀释的氢氟酸(dilute HF)、食人鱼(piranha)及其他清洁剂。选用湿式化学蚀刻工艺以使鸟喙状开口区域形成于光致抗蚀剂层中。之后，以低起始沉积速率进行电化学电镀(ECP)工艺。本领技术人员应了解，以低起始沉积速率进行电化学电镀(ECP)工艺，将可填充因湿式蚀刻工艺或湿式清洁工艺而形成于光致抗蚀剂开口75中的鸟喙状开口(如图3所示的区域85)。此鸟喙状开口将因缺口填补(gap-filling)效应而受到填补，并且可借此形成梯形的铜柱基底部分。对于本湿式工艺的实施例而言，可通过改变用于氧化物清洁步骤的化学作用而在光致抗蚀剂层73中创造出如鸟喙状图样，图3所示的区域85。进行缺口填补的电化学电镀(ECP)工艺之后，以正常的起始沉积速率进行电化学电镀(ECP)工艺，以形成铜柱的其余部分。
在又一方法实施例中，可在光致抗蚀剂工艺中利用光致抗蚀剂显影步骤于开口75底部产生鸟喙状开口区域85。在光致抗蚀剂73形成的工艺中，通过刻意散焦(defocusing)与曝光不足(underexposure)，在光致抗蚀剂层中可产生鸟喙状区域85于开口之中。此方法实施例的优点在于不需要额外的掩模(mask)步骤及额外的化学品或等离子体处理步骤，因此其在实施铜柱形成工艺的成本非常低。在开口75的底部形成如区域85的鸟喙状开口之后，以低起始沉积速率(low initial deposition rate)进行缺口填补的电化学电镀(ECP)工艺，使铜柱材料能够填充于开口75底部的鸟喙状延伸部分之中。
图4为一剖面图，经过图3的后续其他工艺步骤的结构。利用电化学电镀(ECP)工艺使铜柱91形成于籽晶层83暴露的表面之上，其中铜柱91可由下列材料所组成，包括铜及其合金，或是其他导电金属及其合金，以及上述材料的组合。可利用顶盖(cap)材料覆盖于铜柱之上，顶盖(cap)材料包括例如镍(Ni)、钯(palladium，Pd)、铂(platinum，Pt)、金(Au)等等，此外，也可使用上述材料的合金，例如无电镀镍钯浸金(electroless nickel，electroless palladium，immersion gold，ENEPIG)或无电镀镍浸金(electroless nickel，immersion gold，ENEPIG)；此层可视需要实施，且未显示于图中。可形成预焊料层93于铜柱91的上表面之上。此层可通过电镀(plating)、溅镀(sputtering)、印刷(printing)或其他物理气相沉积法(physical vapor deposition，PVD)或化学气相沉积法(chemical vapor deposition，CVD)形成。接着形成焊料层95；其可通过电化学电镀(ECP)工艺进行电镀，例如利用预焊料层作为籽晶层。也可利用其他方法形成焊料层95。焊料层95可为含铅焊料(例如铅(pb)或铅/锡合金(pb/Sn))、无铅焊料(例如锡(Sn)、锡/银合金(Sn/Ag)、锡/银/铜合金(Sn/Ag/Cu))或其他常被利用作为无铅焊料的共熔(eutectic)材料。
图5显示铜柱凸块91经过图4的后续其他工艺步骤的结构。在图4到图5的转变中，通过例如灰化(ashing)或其他现有的光致抗蚀剂剥除方法将光致抗蚀剂73剥除，并且选择性地蚀刻包括籽晶层(seed layer)83及阻挡层81的凸块底层金属层(under bump metallization layer)，以从钝化层(passivationlayer)79之上移除多余的材料。经过以上工艺所完成的柱状凸块包括柱状结构91、预焊料93及焊料95，柱状凸块将继续进行一热回焊(thermal reflow)步骤，以形成带有球状或凸块状焊料顶盖的柱状凸块。
图6为一剖面图，显示另一圆柱形柱状凸块的实施例。在图6中，柱状结构105在基底部分(虚线所包围的矩形，其标号为102)具有最大的宽度，其两侧各自有一宽度为W2的矩形延伸部分自中心部分向外延伸，且柱状结构105的上段部分106具有垂直方向的延伸部分延伸至圆柱形柱状凸块105的顶端。基底部分102较顶端部分宽约10％或更多或更少，基底部分具有矩形延伸部分位于相对的两端，且各自向外，以延伸基底部分的宽度。自基底部分102向下延伸的矩形底端部分104为填充于钝化层(passivation layer)中开口(图中未显示)的柱状结构部分，底端部分104的功能在于接触位于其下方的端点(图中也未显示)。因此，基底部分102位于钝化层(passivation layer)、凸块底层金属层材料及底端部分104之上，而底端部分104位于端点之上并与端点接触。在一非限制性的实施例中，柱状结构宽度W1约为85μm。基底部分102两端的延伸部分各自具有一宽度W2约为5μm，因此在本实施例中，矩形基底部分具有一宽度W3约为95μm。高度H1可为，例如3μm。如同图1所述，在不同的实施例中也可采用其他的高度及宽度，这些实施例仅用于示范而非加以限制。例如，高度H1可为2-10μm。例如，宽度W1可为50-110μm。宽度W2约为基底宽度W1的5％。例如，宽度W2的变化范围可为5-11μm。
形成图6所示的圆柱形柱状结构105的工艺可通过两阶段光致抗蚀剂工艺实施。此两阶段光致抗蚀剂工艺的实施是通过沉积一第一光致抗蚀剂层，并且先图案化将形成基底部分的较宽开口，接着图案化一第二光致抗蚀剂层并在其上形成一开口，其中该开口具有一较窄的宽度，用以定义出上段部分于其上，借此建构出完整的柱状结构。光致抗蚀剂工艺之后，最后通过电化学电镀(ECP)工艺对该柱状结构进行电镀，以完成该柱状结构。由于基底部分的高度H1足够大，因此不需要“缺口填补(gap-filling)”或低起始沉积速率的电化学电镀(ECP)步骤。电化学电镀(ECP)工艺将对基底部分102进行电镀，并且接着形成柱状结构105的上段部分106，如图6所示。
图7为一剖面图，显示本发明所公开的又一实施例。在此实施例中，可使用具有一般梯形的柱状结构101。由于本实施例也是基底部分较宽，因此相较于使用现有的圆柱形柱状凸块，可减少各不同层材料之间的热应力(thermal stresses)。柱状结构101具有倾斜的侧边，自底部最宽的部分沿着倾斜的侧边连续地朝着顶端部分向上延伸，且倾斜的侧边形成一连续的表面。在剖面图中，柱状结构101为一梯形。自柱状结构101的基底向下延伸的矩形底端部分96为填充于钝化层(passivation layer)中开口(图中未显示)的柱状结构部分，底端部分96的功能在于接触位于其下方的端点(图中也未显示)。在一仅用于示范而非加以限制的实施例中，柱状结构101的顶端可具有一宽度W1约为85μm，而柱状结构101的底端可具有一宽度W3约为95μm。使基底部分较宽的其他种元件安排方式，以及具有如图7所示的倾斜侧边，皆可视为其他实施例。在此所公开的任何实施例，其柱状结构的尺寸可加以变更，并且可依照工艺的尺寸等级进行等比例的调整。例如，宽度W1的变化范围可为50-110μm。宽度W3约为基底宽度W1的110-130％，因此，例如，宽度W3的变化范围可为55-130μm。
图7的柱状结构101实施例可在光致抗蚀剂工艺中利用光刻散焦(photolithographic defocus)及曝光能量变化而形成。其中柱状结构101的倾斜侧边自接近底端的最宽部分向上延伸至顶端部分。此倾斜侧边是通过在光致抗蚀剂工艺中利用刻意地散焦及改变曝光能量而形成。在进行曝光及显影步骤之后，利用如上述的电化学电镀(ECP)工艺对柱状结构进行电镀，随后柱状结构的形状依照光致抗蚀剂层中的开口形状而固定其形状。
图6及图7实施例可在不需要使用电镀(electroplating)的条件下形成，可使用，例如，柱状无电镀(electroless plating)及无籽晶沉积(seedless deposition)等方法形成。由于这些实施例并不包括如图1实施例所示的鸟喙状图样，因此不需要借助低起始沉积速率产生的缺口填补(gap-filling)效应。
为了将本发明各个实施例所公开的柱状结构与使用现有的圆柱形柱状结构相比较，图8以表格形式列出归一化应力(normalized stress)的计算结果。鉴别许多柱状结构形成于测试装置上的归一化应力(normalized stress)，可针对装置进行分类和评价。超低介电常数(extreme low-k，ELK)材料的脱层(delamination)被确认为最常发生，因此也是最具象征性的失效模式。其他失效模式也已确认，包括发生于凸块底层金属(UBM)层、钝化层(passivation)、焊料凸块(表中以BUMP表示)层、预焊料层及底部填充(underfill，UF)层的脱层。用于评估的温度条件也显示于表中，若非在25℃的热回焊(thermal reflow)之后，就是在最高温(125℃)或最低温(55℃)的热循环测试(thermal cycle test)之后进行评估。
在表格登录的准备过程中，每一个的应力项目(catergory)数值皆须进行归一化(normalized)，因此将现有的柱状凸块的应力值设定为1.00。表中的任何一个应力项目的数值小于1.00，代表该项目相较于现有技术已得到改善。
在图8的表格的第一列中，显示出最重要的失效模式，超低介电常数(ELK)材料的脱层(delamination)，可用以比较包括现有技术与本发明的各实施例所使用的各种柱状结构形状。图1所显示的具有梯形基底的实施例，其超低介电常数(ELK)材料失效模式的数值为0.91。与现有技术相较已得到改善。同样地，图6所显示的具有矩形基底的柱状结构，其超低介电常数(ELK)材料脱层失效模式与现有技术相较也得到改善。表格的最后一栏为图7所显示的具有倾斜侧边与宽基底的柱状结构，其超低介电常数(ELK)材料脱层失效比率与现有技术相较也得到改善。
本发明所公开的实施例在其他应力项目方面，大多数皆较现有的柱状结构有所改善。在某些受到关注的应力点方面，本发明所公开的实施例的数值可能超过1.00，然而在最弱的失效点(ELK脱层及UBM脱层)方面，本发明所公开的实施例较现有的柱状凸块获得显著的改善。
本发明所公开的每一实施例皆具有一侧视剖面图，此侧视剖面图并非垂直地自圆柱形柱状结构的底部向上延伸至圆柱形柱状结构的顶部。相对地，每一实施例的侧视剖面图具有下列特点之一，包括具有一较顶部更宽的底端部分，具有至少一部分倾斜的侧边，或是在位于基底部分的两侧形成一水平的延伸部分自保持垂直的部分向外延伸。宽度较宽的基底部分位于凸块底层金属层(UBM layer)之上，而且由于在每一实施例中，基底部分的宽度较现有技术的柱状结构的基底部分更宽，因此位于柱状结构下方的凸块底层金属层层经过工艺步骤之后，其面积仍然大于现有技术的柱状结构的凸块底层金属层，因而得以改善热性能(thermal performance)。采用本发明所公开的实施例的柱状结构，能够有效减轻发生在现有技术的柱状结构中的热应力效应(thermal stress effect)。
采用本发明所公开的实施例的柱状结构，能够降低发生在已组装的集成电路中不同层状结构之间的热应力。采用已知的白凸块(white bump)测试，实验结果显示采用这些实施例所公开的柱状结构形状的整列铜柱凸块，并未于凸块中侦测到失效点；然而，即使形成于相同的测试晶片上并且以相同的测试条件进行测试，采用现有技术所述的柱状结构形状的整列铜柱凸块则存在许多热应力失效点。
宽度较宽的基底部分也提供一宽度较宽的凸块底层金属层，因而得以进一步降低热应力效应。模拟应力结果显示，采用本发明所公开的实施例的柱状结构，能够降低发生在已组装的集成电路中超低介电常数(ELK)材料层、钝化层(passivation)、凸块底层金属(UBM)层、凸块层及底部填充(underfill，UF)层等不同层状结构的热应力。
在一实施例中，一装置包括一半导体基板，其中该半导体基板具有至少一输入/输出端点位于其表面之上；一柱状结构设置位于该至少一输入/输出端点之上，其中该柱状结构包括：一底端部分接触该输入/输出端点；一上段部分具有一第一宽度；以及一基底部分位于该底端部分之上并具有大于该第一宽度的一第二宽度。
在另一实施例中，一方法包括形成输入/输出端点于一半导体基板的一侧表面上，以作为一外部连接点；沉积一钝化层位于该输入/输出端点之上；图案化该钝化层以形成开口，以暴露该输入/输出端点的一部分；沉积一籽晶层位于该钝化层之上；沉积一光致抗蚀剂层位于该籽晶层之上；显影该光致抗蚀剂层以在该光致抗蚀剂层中形成光致抗蚀剂开口位于该输入/输出端点之上；图案化该光致抗蚀剂开口的底端部分，以形成鸟喙状图样位于该开口的底部，该鸟喙状图样自该开口向外延伸；以及镀上一层导电材料以填充该光致抗蚀剂开口；其中该导电材料形成一柱状结构自该籽晶层向上延伸，其中该柱状结构包括一上段部分具有一第一宽度，以及一基底部分具有大于该第一宽度的一第二宽度。
在另一实施例中，一方法包括形成输入/输出端点于一半导体基板的一侧表面上，以作为一外部连接点；沉积一钝化层位于该输入/输出端点之上；图案化该钝化层以形成开口，以暴露该输入/输出端点的一部分；沉积一籽晶层位于该钝化层之上；沉积一光致抗蚀剂层位于该籽晶层之上；显影该光致抗蚀剂层以在该光致抗蚀剂层中形成光致抗蚀剂开口位于该输入/输出端点之上，其中该光致抗蚀剂开口定义出一基底部分及一上段部分；以及镀上一层导电材料以填充该光致抗蚀剂开口；其中该导电材料形成一柱状结构自该籽晶层向上延伸，其中该柱状结构包括一上段部分具有一第一宽度，以及一基底部分位于该钝化层之上，其中该基底部分具有大于该第一宽度的一第二宽度。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (10)

1.一种半导体装置，包括：
一半导体基板，其中该半导体基板具有至少一输入/输出端点位于其表面之上，且该输入/输出端点具有一端点宽度；
一柱状结构设置位于该至少一输入/输出端点之上，其中该柱状结构包括：
一底端部分接触该输入/输出端点，其中该底端部分包括凸块底层金属层且具有一底端宽度，其中该底端宽度小于该端点宽度；
一上段部分具有一第一宽度；以及
一基底部分位于该底端部分之上并具有一大于该第一宽度的第二宽度，其中该第二宽度大于该底端宽度，其中该柱状结构具有倾斜的侧边，自该基底部分的底部最宽的部分沿着倾斜的侧边连续地朝着该上段部分的顶端部分向上延伸，且倾斜的侧边形成一连续的表面，其中该柱状结构具有倾斜的侧边，自该基底部分的底部最宽的部分沿着倾斜的侧边连续地朝着该上段部分的顶端部分向上延伸，且倾斜的侧边形成一连续的表面。
2.如权利要求1所述的半导体装置，其中该基底部分具有一形状，从侧视剖面图来看，为一梯形。
3.如权利要求1所述的半导体装置，还包括：其中该凸块底层金属层包括一籽晶层及一阻挡层。
4.如权利要求1所述的半导体装置，其中该柱状结构包括铜。
5.如权利要求1所述的半导体装置，其中该柱状结构还包括该上段部分具有垂直的侧边并且设置于该基底部分之上，该基底部分具有含有非垂直部分的侧边，其中该含有非垂直部分的侧边还包括自该基底部分的底端延伸，并且与该上段部分的该垂直侧边以一大于90°的角度相交。
6.如权利要求1所述的半导体装置，其中该基底部分还包括矩形延伸部分自该基底部分的中心部分向外延伸，且该上段部分具有垂直的侧边。
7.一种半导体装置的制法，包括以下步骤：
形成输入/输出端点于一半导体基板的一侧表面上，以作为一外部连接点，其中该输入/输出端点具有一端点宽度；
沉积一钝化层位于该输入/输出端点之上；
图案化该钝化层以形成开口，以暴露该输入/输出端点的一部分；
沉积一阻挡层与一籽晶层位于该钝化层之上；
沉积一光致抗蚀剂层位于该籽晶层之上；
显影该光致抗蚀剂层以于该光致抗蚀剂层中形成光致抗蚀剂开口位于该输入/输出端点之上；
图案化该光致抗蚀剂开口的底端部分，以形成鸟喙状图样位于该开口的底部，该鸟喙状图样自该开口向外延伸；以及
形成一导电材料于该光致抗蚀剂开口之中；
其中该导电材料形成一柱状结构自该阻挡层与该籽晶层向上延伸，其中该柱状结构包括一上段部分具有一第一宽度，以及一基底部分具有大于该第一宽度的一第二宽度，且该阻挡层与该籽晶层共同形成一凸块底层金属层，其中该凸块底层金属层且具有一底端宽度，该第二宽度大于该底端宽度，且该底端宽度小于该端点宽度，其中该柱状结构具有倾斜的侧边，自该基底部分的底部最宽的部分沿着倾斜的侧边连续地朝着该上段部分的顶端部分向上延伸，且倾斜的侧边形成一连续的表面，其中该柱状结构具有倾斜的侧边，自该基底部分的底部最宽的部分沿着倾斜的侧边连续地朝着该上段部分的顶端部分向上延伸，且倾斜的侧边形成一连续的表面。
8.如权利要求7所述的半导体装置的制法，其中形成该导电材料包括以一低起始沉积速率进行电镀，借以将该导电材料填充于该鸟喙状开口中。
9.如权利要求7所述的半导体装置的制法，其中图案化该光致抗蚀剂的底端部分包括于显影该光致抗蚀剂时实施一散焦工艺。
10.一种半导体装置的制法，包括以下步骤：
形成输入/输出端点于一半导体基板的一侧表面上，以作为一外部连接点，其中该输入/输出端点具有一端点宽度；
沉积一钝化层位于该输入/输出端点之上；
图案化该钝化层以形成开口，以暴露该输入/输出端点的一部分；
沉积一阻挡层与一籽晶层位于该钝化层之上；
沉积一光致抗蚀剂层位于该籽晶层之上；
显影该光致抗蚀剂层以于该光致抗蚀剂层中形成光致抗蚀剂开口位于该输入/输出端点之上，其中该光致抗蚀剂开口的作用在于定义出一基底部分及一上段部分；以及
形成一导电材料于该光致抗蚀剂开口之中；
其中该导电材料形成一柱状结构自该阻挡层与该籽晶层向上延伸，其中该柱状结构包括一上段部分具有一第一宽度，以及一基底部分位于该钝化层之上，其中该基底部分具有大于该第一宽度的一第二宽度，且该阻挡层与该籽晶层共同形成一凸块底层金属层，其中该凸块底层金属层且具有一底端宽度，该第二宽度大于该底端宽度，且该底端宽度小于该端点宽度，其中该柱状结构具有倾斜的侧边，自该基底部分的底部最宽的部分沿着倾斜的侧边连续地朝着该上段部分的顶端部分向上延伸，且倾斜的侧边形成一连续的表面。
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