CN102347284B - 半导体元件及其形成方法 - Google Patents

半导体元件及其形成方法 Download PDF

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Publication number
CN102347284B
CN102347284B CN201110037676.4A CN201110037676A CN102347284B CN 102347284 B CN102347284 B CN 102347284B CN 201110037676 A CN201110037676 A CN 201110037676A CN 102347284 B CN102347284 B CN 102347284B
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oligo
layer
metal coupling
material layer
semiconductor element
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CN102347284A (zh
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郑明达
何明哲
刘重希
黄见翎
林正忠
蔡惠榕
林正怡
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明一实施例提供一种半导体元件及其形成方法，其中半导体元件的形成方法包括：提供一基底；于该基底上形成一焊料凸块；将一少量元素导入至一区域中，该区域邻接该焊料凸块的一顶表面；以及对该焊料凸块进行一回焊工艺以驱使该少量元素进入该焊料凸块之中。采用本发明的实施例，在公知技术中不适合加进金属凸块中的许多类型的少量元素现可被添加。因此，金属凸块的性质可获显著的提升。

Description

半导体元件及其形成方法
技术领域
本发明涉及集成电路，尤其涉及形成金属凸块(metal bumps)的方法。
背景技术
在半导体芯片的形成过程中，例如是晶体管的集成电路元件先形成于芯片中的半导体基底的表面。内连线结构随后形成于集成电路元件之上。金属凸块形成于半导体芯片的表面上，使得集成电路元件得以使用。
若添加少量元素(例如，锗、银、和/或铜)，金属凸块的性质将得以提升。例如，公知焊料凸块(solder bumps)可能遭遇过冷效应(under coolingeffect)，其是指当焊料凸块的温度上升时，由固态转液态的转换温度(transition temperature)不同于当焊料凸块的温度下降时的由液态转固态的转换温度。这造成焊料凸块的随机固化，并因而使焊料凸块的品质下降。
发明内容
为了克服现有技术中存在的缺陷，本发明一实施例提供一种半导体元件的形成方法，包括：提供一基底；于该基底上形成一焊料凸块；将一少量元素导入至一区域中，该区域邻接该焊料凸块的一顶表面；以及对该焊料凸块进行一回焊工艺以驱使该少量元素进入该焊料凸块之中。
本发明一实施例提供一种半导体元件的形成方法，包括：提供一基底；于该基底上形成一金属凸块；于该金属凸块的一表面上沉积一含少量元素材料层，其中该含少量元素材料层包括一少量元素；进行一热工艺以驱使该少量元素进入该金属凸块；以及在进行该热工艺的步骤之后，将该金属凸块接合至一集成电路构件。
本发明一实施例提供一种半导体元件，包括：一基底；一金属凸块，位于该基底之上，其中该金属凸块包括一表面层及位于该表面层之下的一内层；以及一少量元素，位于该金属凸块的该表面层之中，其中该金属凸块的该内层不具有该少量元素于其中，且其中该少量元素是选自由钴、锗、铋、锌、铟、铁、锰、铈、锑、及前述的组合所组成的族群。
还讨论其他实施例。
采用本发明的实施例，在公知技术中不适合加进金属凸块中的许多类型的少量元素现可被添加。因此，金属凸块的性质可获显著的提升。
附图说明
图1-图6显示根据本发明一实施例的包含少量元素的金属凸块的工艺剖面图，其中少量元素是添加于助熔剂之中。
图7A-图9显示根据本发明各种实施例的金属凸块的工艺剖面图，其中少量元素的导入方式包括注入或沉积。
图10-图14显示根据本发明各种实施例的焊料凸块的工艺剖面图，其中少量元素是使用无电镀法而形成于焊料凸块的表面上，并熔化进入焊料凸块之中。
【主要附图标记说明】
2～晶片；
10～基底；
12～内连线结构；
14～半导体元件；
28～金属焊盘；
30～保护层；
40～扩散缓冲层；
42～籽晶层；
45～开口；
46～掩模；
50～金属凸块；
50A、50A-1、50A-2～表面层；
52～助熔剂层；
54～少量元素；
56～焊球；
60～含少量元素材料层；
60A～钴层；
60B～镍层；
60C～铜层；
60D～金层；
64～封装基底；
68～焊料凸块；
70～缓冲层；
70A～铜层；
70B～镍层；
T～厚度。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定类型实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一层或更多其他材料层的情形。为了简单与清楚化，许多结构可能会绘成不同的尺寸。
根据本发明一实施例，提供了一种形成金属凸块的新颖方法，其包含所需的少量元素(minor element)。将说明实施例的中间工艺步骤，且将讨论实施例的变化。在各个实施例或情形的说明中，相似的附图标记将用以标示相似的元件。
请参照图1，提供晶片2，其包括基底10。基底10可包括半导体基底，例如硅基底，虽然其可包括其他半导体材料，例如硅锗、碳化硅、砷化镓、或其相似物。可于基底10的表面形成半导体元件14，其例如为晶体管。于基底10之上形成内连线结构12，其包括金属线路(metal lines)和导电通孔(vias)(未示出)形成于其中，且电性耦接至半导体元件14。金属线路及导电通孔可由铜或铜合金形成，且可使用所周知的镶嵌工艺(damasceneprocess)而形成。内连线结构12可包括层间介电层(ILD)及金属间介电层(IMDs)。在另一实施例中，晶片2为中介晶片(interposer wafer)或封装基底(package substrate)，且大抵不具有包含晶体管、电阻、电容、电感、和/或其相似物的集成电路元件。在这些实施例中，基底10可由半导体材料或介电材料所形成，例如氧化硅。
于内连线结构12上形成金属焊盘(metal pad)28。金属焊盘28可包括铝、铜(Cu)、银(Ag)、镍(Ni)、钨(W)、前述的合金、和/或前述的叠层。金属焊盘28可例如通过下方的内连线结构12而电性耦接至半导体元件14。可形成保护层30以覆盖金属焊盘28的边缘部分。在一实施例中，保护层30是由聚酰亚胺(polyimide)或其他所知的介电材料(例如，氧化硅、氮化硅、和/或前述的叠层)而形成。
请参照图2，毯覆式形成凸块下金属层(UBM)，其可包括选择性扩散缓冲层40及籽晶层42。扩散缓冲层40可为钛层、氮化钛层、钽层、或氮化钽层。籽晶层42的材质可包括铜或铜合金，因而之后或可称为铜籽晶层42。然而，也可包括其他金属，例如银、金、铝、和/或前述的组合。在一实施例中，使用物理气相沉积或其他合用的方法扩散缓冲层40及铜籽晶层42。
图3显示掩模46的形成，其例如可由光致抗蚀剂形成。因此，部分的铜籽晶层42通过掩模46中的开口45而露出。接着，将晶片2放入镀液(未示出)中，并进行镀金属工艺以于凸块下金属层(40/42)上及开口45中形成金属凸块50。镀金属工艺可为电镀、无电镀、浸镀(immersion plating)、或其相似工艺。在一实施例中，金属凸块50为焊料凸块，其可由锡-银、锡-银-铜、或其相似物而形成，且可为无铅或含铅。
在金属凸块50为铜凸块的实施例中，可于金属凸块50的表面上形成附加材料层(未示出)，例如镍、锡、钯、金、前述的合金、和/或前述的叠层。再者，附加材料层可于紧接的掩模46移除步骤之前或之后形成，该移除步骤显示于图4中。在形成金属凸块50之后，移除掩模46，且也例如借由蚀刻而移除先前被掩模46所覆盖的部分的凸块下金属层(40/42)。最终结构显示于图4中。
图5显示将助熔剂层(flux)52披覆至金属凸块50之上，其中助熔剂层52可使用旋转涂布或浸镀而披覆。可将所需的少量元素(其标示为54)添加至助熔剂层52之中。在通篇的叙述中，“少量元素”的用语是指该元素在最终金属凸块(例如，图6及图9中的焊球56)中具有低重量百分率，其中少量元素的重量百分率可例如低于约0.2％。少量元素54例如可选自镍、铁、锰、钛、铈(cerium)、锑(antimony)、及前述的组合，虽然也可添加其他少量元素。在一实施例中，金属凸块50由锡-银焊料、少量元素所形成，除了以上所列少量元素之外，可更进一步选自铋(bismuth)和/或铟、及其相似物。在另一实施例中，金属凸块50是由锡-银-铜焊料所形成，少量元素除了以上所列少量元素之外，可进一步包括锗、锌、和/或钴。取决于金属凸块50的材质，少量元素可具有例如避免氧化、增进润湿度、强化机械行为、增进抗潜变力(creep resistance)、增进抗电迁移力(electro-migrationresistance)、和/或其相似功效的效果。
少量元素54可在披覆前预先混合于助熔剂层之中，其中少量元素54可为粉末类型(例如，包含原子)。在另一实施例中，少量元素54可以化合物的类型而混合于助熔剂层52之中，而可以离子的类型存在。在一实施例中，助熔剂层52中的少量元素的重量百分率大于约0.001％，或大于约0.005％，或介于约0.001％与约0.2％之间。
接着，如图6所示，对金属凸块50进行回焊(re-flow)，因而使金属凸块50变为焊球56(其也可为焊料凸块)。当金属凸块50熔化时，助熔剂层52中的少量元素54可轻易地扩散遍布于焊球56之中。在回焊步骤之后，可移除助熔剂层52的剩余部分。在最终的焊球(焊料凸块)56中，少量元素54的重量百分率可介于约0.001％及约0.2％之间，或介于约0.01％及约0.1％之间，虽然不同的百分率也可能是合用的。在形成焊球56之后，且在切割晶片2之后，可将焊球56及相应芯片接合至另一集成电路构件，例如是封装基底64(或印刷电路板，PCB)，如图9所示。
图7A-图9显示根据本发明各种不同实施例的剖面图。除非特别说明，否则这些实施例中的附图标记代表图1-图6实施例中的相似元件。此实施例的起始步骤可实质上与图1-图5所示的相同。接着，如图7A所示，进行注入以将少量元素54导入金属凸块50之中。相同地，少量元素可包括锗、铋、锌、镍、银、钴、铟、和/或前述的组合。若需要超过一种类型的少量元素，可进行超过一次的注入步骤，其中每一次注入可导入一种类型的少量元素至金属凸块50之中。注入可包括垂直注入(verticalimplantation)，及选择性的倾斜注入(tilted implantation)。在另一实施例中，注入可于形成金属凸块50之后及移除掩模46之前而进行。由于注入步骤，少量元素54可注射至金属凸块50的表面层(surface layer)，该表面层可包括顶表面层50A-1及可能的侧壁表面层50A-2，如图7A所示。
在另一实施例中，取代注入步骤的使用，进行沉积步骤以将少量元素披覆于金属凸块50的表面上。请参照图7B，使用沉积方法形成含少量元素材料层(minor element containing layer)60，沉积方法可包括(但不限于)等离子体离子辅助沉积(plasma ion assisted deposition，PIAD)及化学气相沉积(CVD)，例如等离子体辅助化学气相沉积(PECVD)、或其他适合方法。含少量元素材料层60可包括大抵纯的少量元素，或可为化合物层，其包含有别于所需少量元素的元素。
在金属凸块50为焊料凸块的实施例中，助熔剂层52可披覆于所注入或所沉积的少量元素之上，如图8所示。然而，在此实施例中，助熔剂层52可大抵不含有少量元素，虽然助熔剂层52也可包括少量元素。接着，进行回焊以形成焊球56，其包括少量元素54，接着移除剩余的助熔剂层。最终结构实质上相似于图6所示的结构。
在金属凸块50不能回焊的实施例中，例如当金属凸块50为铜凸块时，不披覆助熔剂，且不进行回焊工艺。更确切地说，进行热退火以驱使少量元素54进入金属凸块50。可发现因为金属凸块50未熔解，金属凸块50中的少量元素的扩散率是低的，因而使少量元素54可能集结于金属凸块50的表面层50A(其显示于图9中)，而金属凸块50的底层和/或内层(区)50B可大抵不具有少量元素54。
在形成金属凸块50之后，且在切割晶片2之后，可将金属凸块50及相应的芯片接合至其他的集成电路构件，例如封装基底64(或印刷电路板)，如图9所示。当金属凸块50连结至位于集成电路构件(封装基底64)上的焊料凸块68时，位于表面层中的少量元素54可扩散进入焊料凸块68，造成所需的性质增进。
图10-图14显示根据本发明各种不同实施例的剖面图。除非特别说明，否则这些实施例中的附图标记代表其他实施例中的相似元件。此实施例的起始步骤可实质上与图1及图2所示的相同。接着，如图10所示，形成掩模46(其由光致抗蚀剂所形成)，并将之图案化，使部分的凸块下金属层(40/42)通过开口45而露出。接着，例如借由镀金属工艺(plating)而于开口45中形成缓冲层70(包括70A及70B)。缓冲层70可包括铜层70A。再者，可于铜层70A之上选择性形成镍层70B。在一实施例中，铜层70A具有介于约1μm及约10μm之间的厚度，且可例如为约5μm。镍层70B具有介于约1μm及约5μm之间的厚度，且可例如为约3μm。接着，例如借由镀金属工艺而于缓冲层70之上形成金属凸块50(或称焊料凸块，solderbump)。
如图11所示，接着移除掩模46。接着，移除凸块下金属层(40/42)的先前由掩模46所覆盖的部分，而形成出如图12所示的结构。图13显示含少量元素材料层60的形成。含少量元素材料层60可包括钴层60A。也可形成附加材料层，例如镍层、铜层、和/或金层(gold layer)，其分别以附图标记60B、60C、及60D标示。应注意的是，含少量元素材料层60可包括钴层60A、镍层60B、铜层60C、及金层60D中的一层或多层，且这些材料层的形成顺序可为任何组合的安排。含少量元素材料层60的厚度T可小于约1000、小于约500、或甚至小于约200。含少量元素材料层60的理想厚度取决于金属凸块50的厚度，以下将更详细地讨论。
含少量元素材料层60可使用无电镀工艺(electroless plating)而形成。因此，含少量元素材料层60(例如，钴层60A、镍层60B、及铜层60C)是选择性(且可相继地)形成于金属凸块50、缓冲层70、及凸块下金属层(40/42)之上，但不会直接电镀在保护层30之上。金层60D可使用浸镀法(immersion)形成。借由使用无电镀工艺，含少量元素材料层60的厚度可准确地控制。
请参照图14，对金属凸块50进行回焊以形成焊球56，可例如通过对晶片2加热或通过快速热工艺(rapid thermal processing，RTP)。含少量元素材料层60被混合进最终的焊球56之中。为了使含少量元素材料层60中的少量元素更均匀地分布于焊球56之中，当回焊进行时可进行超音波处理(以箭头表示)。在回焊工艺之后，可选择性地于低于焊球56的熔化温度的温度下进行附加的退火工艺以更进一步使少量元素扩散进焊球56之中。
在最终的焊球56之中，例如是钴的少量元素的原子百分率(atomicpercentage)可小于约0.7％或小于约0.1％。再者，焊球56中的原子百分率可小于约0.05％或甚至小于约0.01％。因此，假设图13中的焊料凸块的厚度为约80μm，那么含少量元素材料层60的厚度T可为约480，若所需的少量元素原子百分率为0.03％，或者厚度T为约160，若所需的少量元素原子百分率为0.01％。由于添加了钴和/或一些其他的少量元素，过冷效应(under cooling effect)可至少被减轻。因此，在后续接合工艺期间，焊球56可更均匀地固化。
借着采用本发明的实施例，在公知技术中不适合加进金属凸块中的许多类型的少量元素现可被添加。因此，金属凸块的性质可获显著的提升。再者，添加少量元素的成本是低的，因为不包括使用电解质(electrolytes)来并入少量元素。
虽然本发明已以数个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有普通知识的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当以所附的权利要求所界定的范围为准。

Claims (9)

1.一种半导体元件的形成方法，包括：
提供一基底；
于该基底上形成一焊料凸块；
披覆一助熔剂于该焊料凸块的顶表面之上，其中该助熔剂包含一少量元素；
在披覆该助熔剂之后，在该焊料凸块上进行一回焊工艺以驱使该少量元素进入该焊料凸块之中；以及
在进行该回焊工艺后，将包含该少量元素的焊料凸块接合至一封装组件。
2.如权利要求1所述的半导体元件的形成方法，其中该少量元素选自由锗、铋、锌、镍、银、钴、铟、铁、锰、钛、铈、锑、及前述的组合所组成的族群。
3.一种半导体元件的形成方法，包括：
提供一基底；
于该基底上形成一金属凸块；
在形成该金属凸块之后，于该金属凸块的一顶表面层和侧壁表面层的位置形成一含少量元素材料层，其中该含少量元素材料层包括一少量元素，其中该含少量元素材料层实质上未形成在邻近该金属凸块的一底表面的位置，且其中形成该含少量元素材料层的步骤包含选自化学气相沉积或注入的方法；
进行一热工艺以驱使该少量元素进入该金属凸块；以及
在进行该热工艺的步骤之后，将该金属凸块接合至一集成电路构件。
4.如权利要求3所述的半导体元件的形成方法，其中形成该含少量元素材料层的步骤包括进行一无电镀工艺以于该金属凸块的该顶表面层上形成该含少量元素材料层。
5.如权利要求4所述的半导体元件的形成方法，其中进行该无电镀工艺的步骤包括相继地镀上该含少量元素材料层，该含少量元素材料层是选自由一钴层、一镍层、一铜层、及前述的组合所组成的族群。
6.如权利要求5所述的半导体元件的形成方法，还包括进行一浸镀以于该含少量元素材料层上形成一金层。
7.如权利要求3所述的半导体元件的形成方法，其中形成该含少量元素材料层的步骤包括将该少量元素注入至该金属凸块的一顶表面层和侧壁表面层之中。
8.如权利要求7所述的半导体元件的形成方法，其中在形成该含少量元素材料层的步骤之后，及在进行该热工艺之前，还包括于该含少量元素材料层上披覆一助熔剂。
9.一种半导体元件，包括：
一基底；
一金属凸块，位于该基底之上，其中该金属凸块包括一表面层及位于该表面层之下的一内层，其中该表面层包含一顶表面层、一底表面层及一侧表面层，且该侧表面层位于该顶表面层及该底表面层之间；以及
一少量元素，位于该金属凸块的该顶表面层及该侧表面层之中，其中该金属凸块的该内层及该底表面层不具有该少量元素于其中，且其中该少量元素是选自由钴、锗、铋、锌、铟、铁、锰、铈、锑、及前述的组合所组成的族群。
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KR101297486B1 (ko) 2013-08-16
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US20120018878A1 (en) 2012-01-26
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US8227334B2 (en) 2012-07-24
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