CN102239548A - 包含具有邻近于晶体管沟道的能量势垒的晶体管的半导体装置结构及相关联方法 - Google Patents

包含具有邻近于晶体管沟道的能量势垒的晶体管的半导体装置结构及相关联方法 Download PDF

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CN102239548A
CN102239548A CN2009801485473A CN200980148547A CN102239548A CN 102239548 A CN102239548 A CN 102239548A CN 2009801485473 A CN2009801485473 A CN 2009801485473A CN 200980148547 A CN200980148547 A CN 200980148547A CN 102239548 A CN102239548 A CN 102239548A
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energy barrier
semiconductor device
raceway groove
transistor
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钱德拉·V·穆利
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Micron Technology Inc
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Abstract

本发明揭示一种半导体装置结构，其包含在其晶体管沟道下方具有能量势垒的晶体管。所述能量势垒防止所存储的电荷从所述晶体管沟道泄漏到块体衬底中。还揭示用于制作包含能量势垒的半导体装置的方法。

Description

包含具有邻近于晶体管沟道的能量势垒的晶体管的半导体装置结构及相关联方法
相关申请案交叉参考
本申请案主张对2008年12月5日提出申请的名称为“Semiconductor DeviceStructures Including Transistors With Energy Barriers Adjacent to Transistor Channels andAssociated Methods(包含具有邻近于晶体管沟道的能量势垒的晶体管的半导体装置结构及相关联方法)”的第12/329,185号美国专利申请案的申请日期的权益，所述申请案的整体揭示内容以引用的方式并入本文中。
技术领域
本发明的实施例大体来说涉及半导体装置结构，所述半导体装置结构经配置以减少或消除所存储电荷从晶体管沟道的泄漏或从晶体管沟道的“结泄漏”。更具体来说，本发明的实施例涉及其中能量势垒邻近于晶体管沟道安置的半导体装置，且甚到更具体来说，本发明的实施例涉及具有包括碳化硅的能量势垒的半导体装置。
背景技术
在nMOS(n型金属氧化物半导体)晶体管中，晶体管沟道包括n型半导体材料，其中电子构成大多数电荷载流子，且空穴是存储电荷的载流子。有时在包括p型半导体材料的块体衬底中形成此类装置的n型沟道，其中大多数电荷载流子包括空穴。一些nMOS晶体管(例如，基于浮体效应(FBE)的1TOC DRAM单元)的存储器数据保持时间至少部分地取决于空穴可保持于所述n型沟道内的时间长度，所述空穴具有“行进”到所述块体衬底的p型半导体材料中的趋势。
附图说明
在图式中：
图1是在至少一个晶体管下方包含能量势垒的半导体装置结构的实施例的示意性表示；
图2图解说明根据本发明的具有嵌入式有源装置区域的晶体管的实施例；
图3描绘根据本发明的鳍式场效应晶体管(鳍式FET)的实施例；
图4及图4A显示本发明的“假”绝缘体上硅鳍式FET的其它实施例；
图5是本发明的晶体管在“0”条件下的能带图；及
图6是本发明的晶体管在“1”条件下的能带图。
具体实施方式
在各种实施例中，本发明包含具有晶体管的半导体装置结构，所述晶体管包含经配置以达成最小结泄漏的沟道。具有物理性质(例如，带隙、低电荷载流子本征浓度等等)的能量势垒抵靠晶体管沟道定位，以防止存储电荷载流子从所述晶体管沟道泄漏到其上已制作有所述半导体装置的块体衬底中。
图1描绘本发明的半导体装置结构10的实施例。半导体装置结构10包含在制作衬底14上制作及/或由制作衬底14承载的一个或一个以上晶体管12。制作衬底14包含基底衬底16、基底衬底16的载流子表面17的至少一些部分上的能量势垒18及能量势垒18的至少若干部分上的半导体膜20。包含源极及漏极区域22、24及源极与漏极区域22、24之间的沟道26的晶体管12的元件由半导体膜20形成，其中晶体管12的栅极28形成于半导体膜20的与能量势垒18相对的侧上。
可用作基底衬底16的衬底的实施例包含(但不限于)全部或部分块体半导体衬底(例如，全部或部分硅芯片等等)，或全部或部分绝缘体上硅(SOI)型衬底(例如，陶瓷上硅(SOC)、玻璃上硅(SOG)、蓝宝石上硅(SOS)等等)。在其它实施例中，基底衬底16可包括诸如石英、陶瓷、蓝宝石等的电介质材料，而无半导体材料上覆层。
能量势垒18或能量势垒18与邻近半导体膜20之间的界面19抑制来自能量势垒18的一个侧上的晶体管12的电荷载流子(例如，空穴)(或更简单地“载流子”)的丢失。在其中能量势垒18抵靠基底衬底16的包括块体形式或作为形成于基底衬底16的支撑结构上的层的半导体材料的载流子表面17安置的实施例中，能量势垒18可防止载流子从晶体管12传递到基底衬底16的所述半导体材料中。
能量势垒18或能量势垒18与上覆半导体膜20之间的界面19的性质可归因于形成能量势垒18的材料的物理性质，包含那些性质与半导体膜20的对应性质之间的差异、能量势垒18的厚度或上述两者的组合。在一些实施例中，能量势垒18包括具有大于硅的带隙能(即，1.12电子伏特)的带隙能(例如，约1.5电子伏特或更大、约3电子伏特或更大等)的材料。此材料可具有低于基底衬底16的半导体材料中的同类型载流子的本征浓度的载流子(例如，空穴)本征浓度。
能量势垒18可具有适于防止载流子从一个侧上的晶体管传递到相对侧上的基底衬底16的半导体材料的任一厚度。在其中能量势垒18包括碳化硅的一些实施例中，能量势垒18可具有约50nm
Figure BPA00001382603600031
到约150nm
Figure BPA00001382603600032
的厚度。当然，其中能量势垒18具有其它厚度的实施例也在本发明的范围内。
碳化硅(SiC)是可形成能量势垒18的材料的具体实施例。碳化硅具有可为单晶硅中的电子载流子本征浓度的约1/1016(或10-16)的电子载流子本征浓度。碳化硅的更具体实施例包含称作“4H-SiC”及“6H-SiC”的SiC的六方(H)多型体及称作“3C-SiC”的立方(C)多型体。下表比较4H-SiC及6H-SiC的各种性质与硅的对应性质：
表
Figure BPA00001382603600033
在其中能量势垒18包括碳化硅(SiC)的实施例中，所述碳化硅可外延生长或通过已知工艺以其它方式安置于载流子表面17上。此类工艺的实施例由缪拉·H.(Miura，H.)等人，“Epitaxial Growth of SiC on Silicon on Insulator Substrates with Ultrathin Top SiLayer by Hot-Mesh Chemical Vapor Deposition(具有通过热丝网化学气相沉积的超薄顶部Si层的绝缘体上硅衬底上SiC的外延生长)，”日本应用物理学报47(1)：569(2008)；斯德泽斯基·J.(Steszewski，J.)等人，“Comparison of 4H-SiC and 6H-SiC MOSFET I-Vcharacteristics simulated with Silvaco Atlas and Crosslight Apsys(用Silvaco Atlas及Crosslight Apsys模拟的4H-SiC与6H-SiC MOSFET I-V特性的比较)，”电信及信息技术学报，2007年3月，第93页；艾克郝夫·M.(Eickhoff，M.)，“Selective growth ofhigh-quality 3C-SiC using a SiO2sacrificial-layer technique(使用SiO2牺牲层技术的高质量3C-SiC的选择性生长)，”固态薄膜345(2)：197-99(1999)；鄂恩斯特(Ernst，T.)等人，“A new Si:C epitaxial channel nMOSFET architecture with improved drivability andshort-channel characteristics(具有经改良的驱动性及短沟道特性的新Si:C外延沟道nMOSFET架构)，”VLSI研讨会2003：51-52(2003)；及鄂恩斯特(Ernst，T.)等人，“Fabrication of a Novel strained SiGe:C-channel planar 55nm nMOSFET forHigh-Pe rformance CMOS(用于高性能CMOS的新颖应变SiGe:C沟道平面55nmnMOSFET的制作)，”VLSI研讨会2002：92-93(2002)描述。碳化硅中的载流子的本征浓度与所述碳化硅沈积时的温度有关。在一些实施例中，碳化硅中的载流子的本征浓度可为低的；例如，约为单晶硅中的载流子的本征浓度的1/1016(或10-16)。
在其它实施例中，能量势垒18可包括所谓的“碳酸硅”或Si:C，其中在结晶结构中多达约1.4％的分子含碳。用于形成碳酸硅能量势垒18的方法揭示于(Ernst，T.)等人，“A new Si:C epitaxial channel nMOSFET architecture with improved drivability andshort-channel characteristics(具有经改良的驱动性及短沟道特性的新Si:C外延沟道nMOSFET架构)，”2003VLSI技术会议技术论文摘要，第51到52页中。
在一些实施例中，可在能量势垒18上方制作半导体膜20。可通过已知工艺制作半导体膜20，例如通过能量势垒18上硅的外延生长。在一些实施例中，半导体膜20可具有约50nm
Figure BPA00001382603600041
到约150nm
Figure BPA00001382603600042
的厚度。
在半导体膜20就位于能量势垒18上的情形下，可使用此项技术中已知的工艺自半导体膜20且在半导体膜20上制作晶体管12。此类工艺包含(但不限于)隔离结构、晶体管沟道、晶体管栅极电介质、晶体管栅极、用于晶体管栅极的间隔件及顶盖(若有)以及源极区域及漏极区域的制作。所得晶体管12的沟道26可包含p型材料，其中载流子为空穴，且源极及漏极22、24可包含n型材料。图2到图4中描绘所得结构的各种实施例。
图2图解说明包含具有源极区域122及漏极区域124以及形成于半导体膜20中的介入沟道126的晶体管112的半导体装置结构110的实施例。栅极电介质127位于沟道126上方。晶体管栅极128由栅极电介质127承载，其中侧壁间隔件130邻近于晶体管栅极128的每一侧且顶盖132在晶体管栅极128的顶上。能量势垒18位于源极122及漏极124下方及基底衬底16的载流子表面17处的半导体材料上方。
在图3中，描绘所谓的“鳍式场效应晶体管”(“鳍式FET”)212的实施例。鳍式FET 212的每一鳍片240从能量势垒18凸出，其中形成每一鳍片240的基底242的能量势垒18的凸出区域及每一鳍片240的顶部244包含硅(例如，从半导体膜20所界定的硅—图1)。可使用已知工艺从包含硅(以从半导体膜20界定每一鳍片240的顶部244)及能量势垒材料(以从能量势垒18形成每一鳍片240的基底242)的膜界定一个或一个以上鳍片240。在一些实施例中，可使用已知掩模及各向异性蚀刻工艺来界定每一鳍片240。
栅极电介质227由每一鳍片240的表面承载，且延伸到能量势垒118的被描绘为水平延伸表面的主表面上。栅极电介质227又承载晶体管栅极228。
在一些鳍式FET实施例中，例如图4中所示的晶体管212′，底切区域250可形成于每一鳍片240′的基底242′的一个或两个侧中且沿所述一个或两个侧延伸。可单独通过已知工艺(例如通过使用各向同性蚀刻剂)或结合用于限制每一底切区域250的位置及大小的已知工艺(例如，选择性地放置的掺杂剂的使用结合合适蚀刻剂、激光烧蚀技术等等的使用)形成每一底切区域250。
在一些实施例中，每一底切区域250可填充有电介质材料(例如，二氧化硅等等)。在图4所描绘的实施例中，所述电介质材料形成膜251。或者，在图4A所描绘的实施例中，可由所述电介质材料形成电介质元件252。所述所描绘的两个实施例的结果是所谓的“假SOI”结构，其中每一鳍片240′的一部分上覆于电介质材料上。
在图4A中所示的实施例中，每一电介质元件252包含与其对应鳍片240′的侧壁241共面或大致共面的表面254。可通过将电介质材料引入(例如，沉积等等)到能量势垒18的曝露表面上以形成电介质膜251(例如，图4中所示的电介质膜)来形成电介质元件252。除位于底切区域250内或鳍片240′的其它区域下方的电介质材料外，然后可移除上覆于能量势垒18上的电介质材料的全部或大致全部。在一些实施例中，此移除可通过各向异性蚀刻工艺来实施。在其中采用以高于制作每一鳍片240′的材料的选择性移除所述电介质材料的蚀刻剂的实施例中，每一鳍片240′在材料移除过程期间可用作掩模。
一旦晶体管12、112、212、212′已经制作，则可如此项技术中已知实施进一步处理，包含(但不限于)层间电介质膜、互连件、导线的形成及后段工序(BEOL)处理。
返回参照图1，在一些实施例中，本发明的半导体装置结构10可包括动态随机存取存储器(DRAM)装置，例如包含1TOC存储器单元的DRAM装置。能量势垒18结合此结构的一个或一个以上晶体管12的使用可增加与晶体管12相关联的存储器单元将保持电荷；即，将空穴保持于所述晶体管沟道中的时间量。
图5及图6的能带图描绘根据本发明的实施例的能量势垒18的防止来自晶体管的载流子的丢失且因此增加所述晶体管内载流子的浮体效应(FBE)的保持以及防止以所述晶体管的方式存储的电荷的丢失的能力。
在其中硅邻近于碳化硅或碳酸硅的结构中，能带偏移发生在这些材料之间的界面处。图5及图6两者图解说明晶体管沟道26的半导体材料的带隙427、427′(例如，硅-约1电子伏特)小于邻近于晶体管沟道26的能量势垒18的材料的带隙419。
在图5中，存储器单元是在“0”条件下，其中带隙的差异由对应于半导体膜20与能量势垒18之间的界面19(图1)的势垒线表示。
图6是同一存储器单元在“1”条件下的能带图。从图5与图6之间的比较显而易见，当所述存储器单元在两个状态下时，晶体管沟道26及能量势垒18的分别带隙427、427′及419是相同的。图6中也描绘界面19将载流子450保持于晶体管沟道26内的能力，其中将增高的能量状态表示为对应于晶体管沟道26的能带427′的部分的升高峰值。
当能量势垒并入到晶体管中时，可减少或消除结泄漏或空穴从晶体管沟道到基底衬底中的泄漏。
尽管上述说明含有许多具体细节，然而不应将这些具体细节解释为限定本发明的范围，而应仅解释为提供对一些实施例的图解说明。类似地，也可设计在本发明的范围内的其它实施例。可组合采用来自不同实施例的特征。因此，本发明的范围仅由以上权利要求书及其合法等效内容而非由上述说明来指示及限制。由此，将涵盖对本文所揭示的发明作出的归属于权利要求书的含义及范围内的所有添加、删除及修改。

Claims (15)

1.一种半导体装置，其包括：
基底衬底；
形成在所述基底衬底上的能量势垒；及
形成在所述基底衬底上方的至少一个晶体管，所述至少一个晶体管包含包括位于邻近于所述能量势垒处的沟道的半导体材料，所述沟道与所述能量势垒之间的界面防止存储电荷载流子从所述沟道泄漏。
2.根据权利要求1所述的半导体装置，其中所述能量势垒包括所述基底衬底上的外延膜。
3.根据权利要求1所述的半导体装置，其中：
所述沟道的所述半导体材料包括p型半导体材料；且
所述沟道与所述能量势垒之间的所述界面防止包括空穴的存储电荷载流子泄漏出所述沟道。
4.根据权利要求1所述的半导体装置，其中邻近于所述能量势垒的所述半导体材料包含所述沟道、源极及漏极。
5.根据权利要求1所述的半导体装置，其中所述至少一个晶体管包含：
鳍片，其包含：
包括所述能量势垒的基底；
包括邻近于所述能量势垒的所述半导体材料的顶部；
栅极电介质，其涂布所述鳍片的至少一部分；及
栅极电极，其位于所述栅极电介质上。
6.根据权利要求5所述的半导体装置，其中底切区域沿所述鳍片的所述基底的至少一个侧延伸。
7.根据权利要求6所述的半导体装置，其进一步包括：
位于所述底切区域内的电介质材料。
8.根据权利要求1到7中任一权利要求所述的半导体装置，其中所述能量势垒具有低于所述沟道的材料的电荷载流子本征浓度。
9.根据权利要求8所述的半导体装置，其中所述能量势垒中的电荷载流子本征浓度为所述沟道的所述材料中的电荷载流子本征浓度的约10-16。
10.根据权利要求8所述的半导体装置，其中所述能量势垒包括碳化硅。
11.根据权利要求8所述的半导体装置，其中所述能量势垒包括碳酸硅。
12.根据权利要求11所述的半导体装置，其中所述碳酸硅包含高达约1.4％的碳原子。
13.一种用于制作根据权利要求1到12中任一权利要求所述的半导体装置的方法，其包括：
在基底衬底上形成能量势垒；
在所述能量势垒上形成晶体管的沟道；及
制作所述晶体管的剩余部分。
14.一种用于增加电荷存储于根据权利要求1到12中任一权利要求所述的晶体管的沟道内的持续时间的方法，其包括：
邻近于晶体管的沟道形成能量势垒；及
向所述沟道施加电荷。
15.根据权利要求14所述的方法，其进一步包括：
存取由所述沟道存储的所述电荷。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934472A (zh) * 2014-03-17 2015-09-23 台湾积体电路制造股份有限公司 Finfet结构及其制造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8330170B2 (en) 2008-12-05 2012-12-11 Micron Technology, Inc. Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods
US10008212B2 (en) * 2009-04-17 2018-06-26 The Nielsen Company (Us), Llc System and method for utilizing audio encoding for measuring media exposure with environmental masking
JP6046514B2 (ja) * 2012-03-01 2016-12-14 株式会社半導体エネルギー研究所 半導体装置
US9214557B2 (en) * 2014-02-06 2015-12-15 Globalfoundries Singapore Pte. Ltd. Device with isolation buffer
KR102269228B1 (ko) * 2014-07-31 2021-06-25 삼성전자주식회사 반도체 장치의 제조 방법
KR102621649B1 (ko) * 2017-02-08 2024-01-05 삼성전자주식회사 사용자의 활동 패턴과 관련된 타인의 활동 정보를 제공하는 방법 및 그 전자 장치
US10930738B2 (en) 2017-06-29 2021-02-23 Intel Corporation Sub-fin leakage control in semicondcutor devices
US10446681B2 (en) 2017-07-10 2019-10-15 Micron Technology, Inc. NAND memory arrays, and devices comprising semiconductor channel material and nitrogen
US11538919B2 (en) * 2021-02-23 2022-12-27 Micron Technology, Inc. Transistors and arrays of elevationally-extending strings of memory cells

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543637A (en) * 1994-11-14 1996-08-06 North Carolina State University Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein
US20040079989A1 (en) * 2002-10-11 2004-04-29 Nissan Motor Co., Ltd. Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same
US20050224786A1 (en) * 2004-04-06 2005-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic device with depth adjustable sill and method of fabrication thereof
CN1705077A (zh) * 2004-06-03 2005-12-07 国际商业机器公司 半导体材料和形成半导体材料的方法
US20060255364A1 (en) * 2004-02-05 2006-11-16 Saxler Adam W Heterojunction transistors including energy barriers and related methods
US20060284236A1 (en) * 2005-06-21 2006-12-21 Micron Technology, Inc. Back-side trapped non-volatile memory device
US20070200142A1 (en) * 2006-02-24 2007-08-30 Ching-Sung Lee High linear enhancement-mode heterostructure field-effect transistor
US20070290212A1 (en) * 2006-06-19 2007-12-20 Mazzola Michael S Silicon carbide and related wide-bandgap transistors on semi insulating epitaxy

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7000A (en) * 1850-01-08 Smut-machine
US4015A (en) * 1845-04-26 Hand-loom for weaving figured fabrics
US5115289A (en) 1988-11-21 1992-05-19 Hitachi, Ltd. Semiconductor device and semiconductor memory device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
JP2768719B2 (ja) * 1988-11-21 1998-06-25 株式会社日立製作所 半導体装置及び半導体記憶装置
US6746893B1 (en) * 1997-07-29 2004-06-08 Micron Technology, Inc. Transistor with variable electron affinity gate and methods of fabrication and use
JPH11177082A (ja) * 1997-12-15 1999-07-02 Matsushita Electron Corp Ｍｉｓ型電界効果トランジスタおよびその製造方法
US7494901B2 (en) * 2002-04-05 2009-02-24 Microng Technology, Inc. Methods of forming semiconductor-on-insulator constructions
US6770516B2 (en) * 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
US7728360B2 (en) * 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US7042052B2 (en) 2003-02-10 2006-05-09 Micron Technology, Inc. Transistor constructions and electronic devices
JP2004273551A (ja) * 2003-03-05 2004-09-30 Renesas Technology Corp 半導体集積回路装置およびその製造方法
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
KR100626372B1 (ko) 2004-04-09 2006-09-20 삼성전자주식회사 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
US7132751B2 (en) 2004-06-22 2006-11-07 Intel Corporation Memory cell using silicon carbide
US7491988B2 (en) * 2004-06-28 2009-02-17 Intel Corporation Transistors with increased mobility in the channel zone and method of fabrication
US7633110B2 (en) 2004-09-21 2009-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell
JP2006120852A (ja) * 2004-10-21 2006-05-11 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP5011681B2 (ja) 2004-12-02 2012-08-29 日産自動車株式会社 半導体装置
KR100663359B1 (ko) 2005-03-31 2007-01-02 삼성전자주식회사 리세스 채널 트랜지스터 구조를 갖는 단일 트랜지스터플로팅 바디 디램 셀 및 그 제조방법
US7238555B2 (en) 2005-06-30 2007-07-03 Freescale Semiconductor, Inc. Single transistor memory cell with reduced programming voltages
US7517741B2 (en) 2005-06-30 2009-04-14 Freescale Semiconductor, Inc. Single transistor memory cell with reduced recombination rates
US8188551B2 (en) * 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
JP5003043B2 (ja) * 2005-10-26 2012-08-15 株式会社デンソー 半導体装置
KR100653711B1 (ko) * 2005-11-14 2006-12-05 삼성전자주식회사 쇼트키 배리어 핀 펫 소자 및 그 제조방법
US20080079060A1 (en) * 2006-01-31 2008-04-03 International Business Machines Corporation Dual function finfet structure and method for fabrication thereof
US7696000B2 (en) * 2006-12-01 2010-04-13 International Business Machines Corporation Low defect Si:C layer with retrograde carbon profile
US7893475B2 (en) 2007-01-24 2011-02-22 Macronix International Co., Ltd. Dynamic random access memory cell and manufacturing method thereof
JP5292716B2 (ja) * 2007-03-30 2013-09-18 富士通株式会社 化合物半導体装置
KR101505494B1 (ko) 2008-04-30 2015-03-24 한양대학교 산학협력단 무 커패시터 메모리 소자
US8330170B2 (en) 2008-12-05 2012-12-11 Micron Technology, Inc. Semiconductor device structures including transistors with energy barriers adjacent to transistor channels and associated methods
US9726143B2 (en) * 2014-04-07 2017-08-08 University Of Manitoba Ocean wave energy harvesting with a piezoelectric coupled buoy

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543637A (en) * 1994-11-14 1996-08-06 North Carolina State University Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein
US20040079989A1 (en) * 2002-10-11 2004-04-29 Nissan Motor Co., Ltd. Insulated gate tunnel-injection device having heterojunction and method for manufacturing the same
US20060255364A1 (en) * 2004-02-05 2006-11-16 Saxler Adam W Heterojunction transistors including energy barriers and related methods
US20050224786A1 (en) * 2004-04-06 2005-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic device with depth adjustable sill and method of fabrication thereof
CN1705077A (zh) * 2004-06-03 2005-12-07 国际商业机器公司 半导体材料和形成半导体材料的方法
US20060284236A1 (en) * 2005-06-21 2006-12-21 Micron Technology, Inc. Back-side trapped non-volatile memory device
US20070200142A1 (en) * 2006-02-24 2007-08-30 Ching-Sung Lee High linear enhancement-mode heterostructure field-effect transistor
US20070290212A1 (en) * 2006-06-19 2007-12-20 Mazzola Michael S Silicon carbide and related wide-bandgap transistors on semi insulating epitaxy

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104934472A (zh) * 2014-03-17 2015-09-23 台湾积体电路制造股份有限公司 Finfet结构及其制造方法
CN104934472B (zh) * 2014-03-17 2018-01-26 台湾积体电路制造股份有限公司 Finfet结构及其制造方法

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