CN102099862B - 门电平可重配置的磁性逻辑 - Google Patents
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Abstract
一种可再编程门逻辑(400)包括并联的多个非易失性可重配置的基于电阻状态的存储器电路(I),其中所述电路可重配置以实施或改变选定门逻辑,且所述多个非易失性可重配置的基于电阻状态的存储器电路每一者适于接收逻辑输入信号(A、B)。与所述多个并联非易失性可重配置的基于电阻状态的存储器电路串联的评估开关(418)经配置以基于所述存储器电路的编程状态而提供输出信号(420)。传感器(430)经配置以接收所述输出信号,且基于所述输出信号和提供到所述传感器的参考信号而提供逻辑输出信号。可基于将自旋力矩转移(STT)磁性隧道结(MTJ)磁阻随机存取存储器(MRAM)用作可再编程存储器元件来实施可重配置逻辑。逻辑配置在无电力的情况下得以保持。
Description
技术领域
本发明涉及可编程逻辑,且更具体来说涉及使用自旋转移力矩磁阻随机存取存储器(STT MRAM)的可再编程逻辑。
背景技术
可编程逻辑阵列(PLA)为用以实施组合逻辑电路的可编程装置。所述PLA具有一组可编程“与”平面,所述组可编程“与”平面链接到一组可编程“或”平面,可接着有条件地对所述“或”平面求反以产生输出。此布局允许合成大量逻辑功能,包括“异或”或更复杂的组合功能。在制造期间以与ROM相同的方式对许多PLA进行掩模编程。此情形对于嵌入在较复杂和众多集成电路(例如,微处理器)中的PLA尤其适用。可在制造后经编程的PLA称为FPLA(现场可编程PLA)或FPGA(现场可编程门阵列)。在制造了FPGA之后,FPGA互连件仅可由消费者或设计者编程(即,“预烧”)一次以实施任何逻辑功能-因此称为“现场可编程”。FPGA通常进行较缓慢且与其专用集成电路(ASIC)对等物相比可能汲取(draw)较多电力。
对于FPGA,存在芯片空间的专用于额外开销或未使用的相当大的部分。举例来说,为了适应需要“与”门逻辑和“或”门逻辑的特定选择或混合的特定应用,所述两者必须可用于一般芯片中,且仅所述应用所需要的那些组件为有线的,或在编程时间经“预烧”。
磁阻随机存取存储器(MRAM)为基于夹在两个磁性层之间的氧化物的穿隧电阻的存储器元件。当所述两个层中的磁化平行时,穿隧电阻为“低”,且此称作状态0。当所述两个层中的磁化反平行时,穿隧电阻为“高”,且此称作状态1。在MRAM中,一个层在装置寿命期间为固定的,且另一层为“自由”层,所述“自由”层可通过可寻址写入线改变以产生能够重新对准或“翻转”极化方向的磁场。状态0或状态1可通过用分压器电路相对于已知参考电阻测量MRAM的电阻而确定。尽管所述MRAM可重新写入,但其状态为非易失性的,且因此不需要持续电力。
然而,MRAM存储器需要切换与电池供电的便携式装置不兼容的功率电平,且无法如越来越高的装置间距密度的情况下当前所需进行良好缩放。
目前,不存在在依赖于非易失性磁性存储器类型元件的单元的固定拓扑配置内提供可再编程逻辑的逻辑电路。基于前文,所属领域的技术人员将了解,需要提供可针对较高装置间距密度缩放的非易失性且可重配置(即,可再编程)的逻辑的系统。
发明内容
揭示一种可再编程逻辑装置及其形成方法,其基于使用自旋力矩转移(STT)MRAM元件来实施逻辑功能。STT MRAM用以替代常规FPGA或PLA装置来实施例如“或”门、“与”门、“非或”门和“与非”门函数等逻辑。所述逻辑的配置可通过在无需改变拓扑的情况下再编程STT MRAM元件的状态来改变以提供不同组的逻辑操作。此外,当断电时保持所述逻辑配置,且当通电时在同一配置中恢复。
STT MRAM元件为一结,其包含磁性膜、氧化物膜和磁性膜的夹层,所述夹层类似于常规MRAM呈椭圆状结构,但可缩放到更小尺寸。与常规MRAM类似,STT MRAM具有磁性膜的固定层和自由(可写入编程)层。所述自由层借助于直接通过所述结的写入电流的电子自旋极化的自旋力矩转移来编程,而非通过由外部电流诱发的磁场来编程。STT MRAM优于常规MRAM的另一优点由较小尺寸的装置中所需要的较低写入电流提供,同时实现通过结的较高电流密度,从而使写入编程步骤更有效且更可靠地产生所要状态(“1”或“0”)。
尽管关于磁性随机存取存储器(且更特定来说为自旋力矩转移磁阻隧道结磁性随机存取存储器)描述本文中所呈现的实施例,但可预期所描述的特征也被应用于包括以下各项的此类装置:相变随机存取存储器(PCRAM)、基于电阻的随机存取存储器(R-RAM),或可以非易失性方式存储基于电阻的电可编程存储器状态的任何装置(即,在无持续电力的情况下,其可通过电效应、磁效应、电磁(例如,光学)效应或此类物理效应的组合再编程到多个状态)。
前文已颇为广泛地概述了本发明的特征和技术优点,以便可更好地理解以下的本发明的具体实施方式。下文将描述形成本发明的权利要求书的主题的本发明的额外特征和优点。所属领域的技术人员应了解,所揭示的概念和特定实施例可易于用作修改或设计用于实行本发明的相同目的的其它结构的基础。所属领域的技术人员还应认识到,此类等效构造并不背离在所附权利要求书中所阐述的本发明的精神和范围。当结合附图考虑时,从以下描述将更好地理解据信为本发明所特有的新颖特征(关于其组织和操作方法两者)以及其它目的和优点。然而,应明确地理解,仅出于说明和描述的目的而提供各图中的每一者,且并不希望将其作为本发明的限制的定义。
附图说明
为了获得对本发明的更完整理解,现结合附图来参看以下描述,附图中:
图1展示其中可有利地使用本发明的实施例的示范性无线通信系统;
图2A展示处于平行磁化低电阻状态的常规磁性隧道结MTJ的基本元件;
图2B展示处于反平行磁化高电阻状态的常规磁性隧道结MTJ的基本元件;
图3A展示根据本发明的一实施例的处于1-晶体管/1-MTJ(1-T/1-MTJ)配置中的STTMTJ MRAM单元;
图3B说明根据图3A的架构的用于针对低电阻平行极化状态而编程MTJ的示范性电路配置;
图3C说明根据图3A的架构的用于针对高电阻反平行极化状态而编程MTJ的示范性电路配置;
图4A为根据本发明的一实施例的使用四个STT MTJ单元的四输入逻辑电路的实例;
图4B为图4A的示范性逻辑电路的等效电路;
图5A为针对图3到图4的四个STT MTJ单元设定的示范性[1,0,1,0]状态的电压输出;
图5B为针对图3到图4的四个STT MTJ单元设定的示范性[0,1,0,1]状态的电压输出;
图7为根据本发明的一实施例的以可编程方式配置门逻辑的方法的流程图。
图8为根据本发明的一实施例的操作可重配置门逻辑的方法的流程图。
具体实施方式
揭示一种逻辑门阵列,其基于可以可编程方式重配置以提供非易失性“与”、“与非”、“或”和“非或”逻辑功能性的STT MTJ MRAM单元。类似的可再编程逻辑功能性可使用如以上所指示的可再编程存储器元件的其它形式来实现,且在本发明的既定精神内。然而,出于描述简易的目的,本文中将STT MTJ MRAM描述为示范性实施例,且并非限制性的。
MTJ具有如下特性:可通过改变一个(“自由”)磁性层(通过薄的非导电氧化物层使其与第二“固定”磁性层分离)的相对磁化方向来更改通过结的电子电流(electroncurrent flow)的电阻。所述电阻由电子穿隧通过所述氧化物的能力来确定。当所述两个磁性层经平行磁化时,所述电阻为“低”(状态0)。当所述两个磁性层经反平行磁化时,所述电阻为“高”(状态1)。在STT MTJ中,可通过经由发送自旋极化电子的足够密度的高电流直接通过结来将所要磁化方向写入到自由层而切换结的电阻状态。所述电流足以影响自由层但不影响固定层。
图1展示其中可有利地使用本发明的实施例的示范性无线通信系统100。出于说明的目的,图1展示三个远程单元120、130和150以及两个基站140。将认识到,典型无线通信系统可具有更多远程单元和基站。远程单元120、130和150包括STT MTJ MRAM存储器芯片125A、125B和125C,其为如以下所进一步论述的本发明的实施例。图1展示从基站140到远程单元120、130和150的前向链路信号180,以及从远程单元120、130和150到基站140的反向链路信号190。
在图1中,将远程单元120展示为移动电话,将远程单元130展示为便携式计算机,且将远程单元150展示为无线区域回路系统中的固定位置远程单元。举例来说,所述远程单元可为手机、手持式个人通信系统(PCS)单元、例如个人数据助理等便携式数据单元,或例如仪表读数设备等固定位置数据单元。尽管图1说明根据本发明的教示的远程单元,但本发明并不限于这些示范性说明的单元。本发明的实施例可适当地用于包括存储器芯片的任何装置中。
图2展示磁性隧道结MTJ 200的基本元件。图2A展示处于平行磁化低电阻状态的常规磁性隧道结MTJ的基本元件。图2B展示处于反平行磁化高电阻状态的常规磁性隧道结MTJ的基本元件。MTJ 200包含固定磁化层(即,固定层210)、自由层211和势垒层212。固定层210为在装置寿命期间具有固定磁化方向的磁性层。自由层211为磁化方向可由所施加的穿隧写入电流的方向更改的磁性层。势垒层212为足够薄以准许视以下所描述的条件而定的来自固定层210或自由层211的电子的穿隧的电介质层。势垒层212可为例如氧化物(例如,MgO)等若干绝缘体材料中的一者或一者以上。通常,可使固定层210、势垒层212和自由层211的堆叠成形为平坦椭圆体的形式,其中极化方向优先地且大体上沿所述椭圆体的主轴,且平行于其上形成所述堆叠的衬底的表面。
可大体上将此配置应用于常规MRAM以及STT MTJ MRAM,差别在于,对于STTMTJ MRAM来说无需外部磁场来将极化状态写入到MTJ 201。
图3A展示处于1-晶体管/1-MTJ(1-T/1-MTJ)配置中的MRAM电路300(例如,STT MTJ),其包括结MTJ 301。MTJ 301具有邻近于反铁磁体313的固定层210,所述固定层210为导电的且在装置寿命期间保持其磁化。反铁磁体313确定固定层210的磁性极化的对准。另外,MTJ 301具有邻近于反铁磁体313的电极318和用于连接到外部电路的邻近于自由层211的电极315。经由电极318,MTJ 301连接到晶体管317的漏极电极。晶体管317的源极电极连接到源极线316。晶体管317的栅极电极连接到字线314。字线314控制晶体管317的栅极。位线335和源极线316设定电子流的方向。MTJ 301的自由层211连接到位线335。在位线335与源极线316之间施加(任一极性的)电压VDD。晶体管317充当开关。当经由字线314将电压施加到晶体管317的栅极时,电流将在位线335与源极线316之间流动(如由势垒212上的穿隧电阻所调节,其视自由层211的STT诱发的极化而定)。
在写入模式中,使VDD足够大以产生足够电流密度的自旋极化电子流从而切换自由层211的磁化。通过MTJ 301的电子电流方向确定自由层211中的诱发极化方向。在读取模式中,VDD较小,且电流密度不足以更改自由层211中的极化。
在图3B中,将位线335电压设定为VDD(假设为正)且源极线316接地,使得在字线314提供栅极电压VG以接通晶体管317的导电路径时常规电流从位线335流动到源极线316(即,电子从源极线316流动到位线335)。当VDD足够大时,此方向上的电流写入自由层211使其极化平行于固定层210,从而将MTJ 301置于低电阻状态(0)(具有电阻RMTJ(0))。在图3C中,当通过以电压VG断言(assert)字线314、通过以VDD将源极线316设定为高以及通过将位线335电压设定为较低来接通晶体管317的栅极时,电子在从位线335到源极线316(即,从自由层211到固定层210)的相反方向上流动,将自由层211切换到反平行极化状态,从而将MTJ 301置于高电阻状态(1)(其中电阻RMTJ(1)>RMTJ(0))。
如以下所描述,STT MRAM MTJ可用作门逻辑元件,门逻辑元件(例如)可用于每个此类门逻辑元件均可经再编程的门逻辑中。因此,可响应于写入指令而动态地重配置包括此种可再编程逻辑的装置以支持特定应用的要求。可编程逻辑空间的此可再用性准许芯片空间的非常有效的使用。此外,逻辑程式为非易失性的,即不需要备用电力。
图4A为根据本发明的一实施例的使用四个STT MTJ结J-1到J-4的四输入门逻辑400的实例。图4A仅展示结J-1到J-4,但每一者还可包括可通过到晶体管栅极的字线信号以图3A中所指示的方式切换的单独晶体管(未图示)。其类似于常规FPGA四输入逻辑块,只是每一单元的状态和对应电阻可被重配置(如以上所描述)。实际上,可能仅需要两个输入,例如A和B。额外反相器(未图示)可提供两个额外并列输入A_和B_。
在读取模式中(即,在逻辑操作期间),可分别地将可识别为A、A_、B和B_的输入施加到结J-1到J-4,其中,如果A=1,那么A_=0,等等。这些逻辑输入的电压电平小于写入电压,使得不改变结J-1到J-4的磁化电阻状态。每一结可处于0状态或1状态中。因此,结J-N(0)处于“0”状态,且J-N′(1)处于“1”状态。
当将输入[A、A_、B和B_]分别施加到J-1到J-4且将EVAL信号电压VE施加到晶体管开关417的栅极时,适量电流将流经晶体管开关417。电流量由输入信号[A、A_、B和B_]的电压(出于示范性目的,此处假设其为VDD或0,其中VDD处于只读电平且不引起极化改变,如以上所指示)、结J-1到J-4的有效电阻和晶体管417的有效电阻RT确定。结J-1到J-4的有效电阻为并联的,且结J-1到J-4的有效净并联电阻与晶体管417的RT串联。到A和/或B=1的输入可为高(例如,电压=VDD),或所述输入可为A和/或B=0(例如,电压=0)。将在晶体管开关417上所测量的电压VT(在求和线420处测量)输入到可包含(例如)两个饱和放大反相器430和440的传感器电路,其可用以针对所施加信号确定逻辑输出F和F_的真值表(truth table),如以下所描述。
图4B为图4A的示范性逻辑电路的等效电路。当EVAL电压VE将晶体管开关417接通到导电状态时,结J-1到J-4可由其相应等效电阻RJ-1-RJ-4表示,且晶体管开关417由等效电阻RT(418)表示。流经结J-1到J-4的所有电流的总和(例如,IT)流经求和线420到达晶体管开关418,且接着到达接地。求和线420处的电压VT根据VT=IT×RT来确定总电流。
对应于每一状态,结J-1到J-4可具有有效电阻RJ-1到RJ-4,其中RJ-N(0)为处于0状态的结J-N的电阻(其为“低”电阻)且RJ-N′(1)为处于1状态中的结J-N′的电阻(其为“高”电阻)。为了说明可如何使用图4A的拓扑以可重配置的方式来实施各种逻辑功能,借助于参看图4B的等效电路而呈现实例。为简单起见,关于RJ-N(0)、RJ-N′(1)和RT的值以及输入A和B的电压电平作出以下假设:
假设RJ-N(0)=R0,RJ-N′(1)=5*R0且RT(418)=R0/10。这些电阻值可包括寄生电阻(例如,线电阻和结开关电阻),且可有效地将其视为确定元件的电响应的复合电阻值。
假设:当将A和/或B设定为=1时,VA和/或VB=VDD,其中VDD为读取电平电压。
假设:当将A和/或B设定为=0时,VA和/或VB=0。
实例1
假设将MTJ结J1-J4设定为状态[1,0,1,0]。因此,相应电阻为RJ-1(1)=5R0,RJ-2(0)=R0,RJ-3(1)=5R0且RJ-4(0)=R0。对于A、B的所有四个可能组合和量值VDD的所得四个输入电压[A,_A,B,_B],在表1中展示所测量电压VT。
表1
针对结状态[1,0,1,0]的晶体管电压VT对输入A、B
A | A_ | B | B_ | VT/VDD |
1 | 0 | 1 | 0 | 0.18 |
1 | 0 | 0 | 1 | 0.42 |
0 | 1 | 1 | 0 | 0.42 |
0 | 1 | 0 | 1 | 0.67 |
图5A为关于表1中所展示的输入的可能组合的电压输出VT(A,B)的代表性曲线,给定四个STT MTJ结J-1到J-4的状态设定为[1,0,1,0]。可相对于输入状态A、B来指示输出电压(即,指示为VT(A,B))。反相器430接收来自求和线420的电压VT(A,B)。如果VT(A,B)超过阈值电压,那么反相器430可经设定以触发输出。反相器430接着可放大所述输入以视所述输入而输出逻辑1电平或逻辑0电平(例如,VDD或0)。第二反相器440使反相器430的输出反相。F为来自反相器440的输出且F_为来自反相器430的输出。如果反相器430经设定以基于在VT(1,0)与VT(0,0)之间的阈值电压而触发,那么得到表2中的真值表。如表1中所展示,VT(1,0)=VT(0,1)。可见,F等同于逻辑“非或”且F_等同于逻辑“或”。
表2
结状态[1,0,1,0]对输入A、B的真值表
阈值电压设定于VT(1,0)与VT(0,0)之间
A | B | F | _F |
1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
0 | 1 | 0 | 1 |
0 | 0 | 1 | 0 |
“非或” | “或” |
或者,如果反相器430经设定以基于在VT(1,1)与VT(1,0)之间的阈值电压触发,那么得到表3中的真值表。通过检验可见,F遵照“与非”逻辑且F_遵照“与”逻辑。
因此可见,通过设定为[1,0,1,0]的MTJ结的组合和控制关于反相器430的阈值电压,可实现四个逻辑功能“与”、“与非”、“或”和“非或”。在下一实例中,可将MTJ结重配置为不同电阻状态且通过检验而确定所得逻辑。
表3
结状态[1,0,1,0]对输入A、B的真值表
阈值电压设定于VT(1,1)与VT(1,0)之间
A | B | F | _F |
1 | 1 | 0 | 1 |
1 | 0 | 1 | 0 |
0 | 1 | 1 | 0 |
0 | 0 | 1 | 0 |
“与非” | “与” |
实例2
假设将MTJ结J-1到J-4设定为状态[0,1,0,1]。因此,相应电阻为RJ-1(0)=R0,RJ-2(1)=5R0,RJ-3(0)=R0且RJ-4(1)=5R0。使用与以上相同的分析,图5B为关于输入的可能组合的电压输出VT(A,B)的代表性曲线,给定四个STTMTJ结J-1到J-4的状态设定为[0,1,0,1]。注意,与VT(0,0)为最高的第一实例相比,VT(1,1)为最高输出。如果反相器430经设定以在VT(1,1)与VT(1,0)之间触发且相应地输出VDD或0,那么得到表4中的真值表。可见,F等同于逻辑“与”且F_等同于逻辑“与非”。
表4
结状态[0,1,0,1]对输入A、B的真值表
阈值电压设定于VT(1,1)与VT(1,0)之间
A | B | F | F_ |
1 | 1 | 1 | 0 |
1 | 0 | 0 | 1 |
0 | 1 | 0 | 1 |
0 | 0 | 0 | 1 |
“与” | “与非” |
类似地,如果反相器430经设定以基于在VT(1,0)与VT(0,0)之间的阈值电压触发,那么得到表5中的真值表。可见,F等同于逻辑“或”且F_等同于逻辑“非或”。
表5
结状态[0,1,0,1]对输入A、B的真值表
阈值电压设定于VT(1,0)与VT(0,0)之间
A | B | F | F_ |
1 | 1 | 1 | 0 |
1 | 0 | 1 | 0 |
0 | 1 | 1 | 0 |
0 | 0 | 0 | 1 |
“或” | “非或” |
可使用MTJ结布置额外配置以实现可再编程的非易失性逻辑。举例来说,晶体管417可由与MTJ结J-1到J-4的平行阵列串联的MTJ结替代。MTJ结可大体上与参看图3A所描述的结相同,但在此处充当具有可编程电阻的开关。如以上所描述,反相器430和440充当传感器,其基于提供到反相器430的阈值电压电平和大体上以如以上所描述在晶体管417的漏极处获得VT的相同方式在对应于MTJ开关的位线335处获得的经检测电压VT而触发逻辑输出。可接着将MTJ开关编程为两个不同电阻状态,其具有使电压VT(A,B)移位和缩放电压VT(A,B)的效应。因此,可进一步通过经由使用MTJ开关使输出电压电平和缩放范围相对于阈值电压电平移位来控制所述逻辑输出。
或者,可将晶体管开关与MTJ开关的组合布置为串联和/或并联配置以相对于触发阈值电平而提供对输出电压的更精细程度的控制。可了解,此组合实现逻辑电路之间的性能调平,所述逻辑电路可能归因于制造公差而具有(例如)元件的有效电阻的变化。
图6为根据本发明的实施例的以可编程方式配置门逻辑的方法的流程图。方法600以选择门逻辑400中的每一MTJ结(例如,J1-J4)的对应于门逻辑400需要遵照的选定逻辑功能行为的电阻状态的第一步骤(P601)开始。接着将用以设定MTJ的电阻状态的足够量值的适当写入信号电平VDD施加到每一MTJ J1-J4(P602)。VDD的极性和因此电流的方向可相应地确定电阻状态。
图7为根据本发明的一实施例的操作可重配置门逻辑的方法的流程图。方法700以指定待施加到门逻辑400中的每一MTJ(例如,J1-J4)的输入的逻辑(即,0或1)输入信号(步骤P701)开始。所述逻辑输入信号电平的量值不足以改变MTJ J1-J4的电阻状态。将所述逻辑输入信号施加到相应结输入(P702)。根据图4B的等效电路分析,流经MTJ J1-J4的电流的总和在流经评估开关418期间产生在评估开关418的输入处出现的电压信号输出(P703)。经检测的电压信号输出被输入到包含反相器430和440的传感器电路。反相器还接收电压参考信号(P704),其视反相器430的输入处出现的经检测电压信号而定来确定反相器430的逻辑输出。反相器430和440基于经检测电压信号和电压参考信号而输出相应逻辑输出信号(P705)。因此,MTJ J1-J4的配置状态与提供到反相器430的参考电压的组合确定逻辑输入的逻辑输出。
如可编程逻辑阵列设计领域的一般技术人员将认识到,当适当地将MTJ结的单元编程时,通过组合由图4A的逻辑电路提供的基本逻辑操作可实现较复杂的逻辑功能(例如,“异或”、“异或非”,等等)。可进一步了解,可实现更复杂的逻辑功能。举例来说,可通过四个以上STT MTJ单元来配置相同数目个输入,以视每一单元的状态和触发电平而定获得逻辑功能行为。
因此,可编程逻辑阵列设计领域的一般技术人员可了解,可将以上所描述的STTMTJ结组合到包含用以实施与FPGA和相关PLA相同的功能性的具有高可再编程性控制程度的门逻辑的单元阵列中。为以上所描述的真值表的等效物的查找表(LUT)是此种实施方案的一实例。此外,可了解,出于执行复杂逻辑操作的目的,此类门逻辑阵列还可在需要时经再编程,即多个单元中的结中的每一者可以可重配置方式在两个状态之间切换,使得由相同阵列可实现不同逻辑处理。
虽然已详细描述本发明及其优点,但应理解,在不脱离由所附权利要求书所界定的本发明的精神和范围的情况下,可在本文中进行各种改变、替代和更改。此外,本申请案的范围并不希望限于说明书中所描述的过程、机器、制造、物质组成、手段、方法和步骤的特定实施例。如所属领域的一般技术人员将易于从本发明的揭示内容了解,根据本发明,可利用目前存在或日后将开发的执行与本文中所描述的对应实施例大体上相同功能或实现大体上相同结果的过程、机器、制造、物质组成、手段、方法或步骤。因此,所附权利要求书希望在其范围内包括此类过程、机器、制造、物质组成、手段、方法或步骤。
Claims (16)
1.一种非易失性可再编程门逻辑电路,其包含非易失性的基于电阻的存储器单元,其中所述非易失性的基于电阻的存储器单元包含:
并联的多个可重配置的非易失性的基于电阻的结电路,每一可重配置的非易失性的基于电阻的结电路经配置以接收输入逻辑信号;
评估开关,其与所述多个可重配置的非易失性的基于电阻的结电路串联,其中所述评估开关经配置以基于所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的配置而提供输出信号;以及
传感器电路,其配置以接收所述输出信号和阈值电压作为输入,并基于所述输出信号和所述阈值电压来输出一个或多个逻辑信号,所述一个或多个逻辑信号代表施加到所述输入逻辑信号的逻辑功能,所述逻辑功能由所述阈值电压和所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的所述配置来决定,其中,所述阈值电压可受控制来改变所述逻辑功能。
2.根据权利要求1所述的非易失性可再编程门逻辑电路,其中所述评估开关为选定串联和/或并联组合中的一个或多个晶体管。
3.根据权利要求1所述的非易失性可再编程门逻辑电路,其中所述评估开关为选定串联和/或并联组合中的一个或多个可重配置的非易失性的基于电阻的结电路。
4.根据权利要求1所述的非易失性可再编程门逻辑电路,其中所述评估开关为选定串联和/或并联组合中的一个或多个晶体管和/或一个或多个可重配置的非易失性的基于电阻的结电路。
5.根据权利要求1所述的非易失性可再编程门逻辑电路,其中所述可重配置的非易失性的基于电阻的结电路包含以下各项中的一者或一者以上:相变随机存取存储器(PC-RAM)电路、基于电阻的随机存取存储器(R-RAM)电路、磁阻随机存取存储器电路,和自旋转移力矩磁阻隧道结磁阻随机存取存储器电路。
6.根据权利要求5所述的非易失性可再编程门逻辑电路,其中所述自旋转移力矩磁阻隧道结磁阻随机存取存储器电路包含:
磁性隧道结;以及
第一金属互连件,其经配置以将位线写入信号和/或输入读取信号提供到所述磁性隧道结,其中所述位线写入信号配置所述磁性隧道结的电阻状态,且所述输入读取信号经施加以确定所述电阻状态。
7.根据权利要求6所述的非易失性可再编程门逻辑电路,其中,所述评估开关操作地耦合到所述磁性隧道结和源极线,以针对读取和/或写入操作而准许电流流经所述磁性隧道结。
8.根据权利要求6所述的非易失性可再编程门逻辑电路,其中所述磁性隧道结包含:
顶部电极,其与所述金属互连件通信;
自由磁化层,其邻近于所述顶部电极;
隧道势垒层,其邻近于所述自由磁化层;
固定磁化层,其邻近于所述隧道势垒;以及
底部电极,其邻近于所述固定磁化层并与所述评估开关通信。
9.根据权利要求1所述的非易失性可再编程门逻辑电路,其中,所述评估开关包含:
第二金属互连件,其与所述多个并联的可重配置的非易失性的基于电阻的结电路串联通信;以及
开关元件,其具有与所述第二金属互连件通信的源极电极、经配置以接收控制信号从而改变所述开关元件的导电路径的电阻状态的栅极电极,以及源极电极,其中所述开关元件选自至少晶体管、磁阻随机存取存储器单元和自旋转移力矩磁阻隧道结磁阻随机存取存储器单元。
10.根据权利要求9所述的非易失性可再编程门逻辑电路,其中所述传感器电路的所述输出信号包含逻辑1和/或逻辑0。
11.一种重配置非易失性可再编程门逻辑电路的写入方法,所述门逻辑电路包含非易失性的基于电阻的存储器单元,其中所述方法包含:
将输入逻辑信号施加到并联的多个可重配置的非易失性的基于电阻的结电路,及
使用评估开关,其与所述多个可重配置的非易失性的基于电阻的结电路串联以基于所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的配置而提供输出信号;
接收所述输出信号和阈值电压作为传感器电路处的输入;
在所述传感器电路处基于所述输出信号和所述阈值电压来输出一个或多个逻辑信号,所述一个或多个逻辑信号代表施加到所述输入逻辑信号的逻辑功能,所述逻辑功能由所述阈值电压和所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的所述配置来决定,其中,所述阈值电压可受控制来改变所述逻辑功能,其中所述输入逻辑信号的电流方向确定所述非易失性的基于电阻的结电路的电阻状态。
12.根据权利要求11所述的写入方法,其进一步包含选择所述输入逻辑信号中的每一输入逻辑信号的所述电流方向以确定每一可重配置的非易失性的基于电阻的结电路的一组电阻状态,所述电阻状态对应于选定逻辑功能。
13.一种操作非易失性可再编程门逻辑电路的方法,所述门逻辑电路包含非易失性的基于电阻的存储器单元,其中方法包含:
将输入逻辑信号施加到并联的多个可重配置的非易失性的基于电阻的结电路;
使用评估开关,其与所述多个可重配置的非易失性的基于电阻的结电路串联以基于所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的配置而提供输出信号;
接收所述输出信号和阈值电压作为传感器电路处的输入;
在所述传感器电路处基于所述输出信号和所述阈值电压来输出一个或多个逻辑信号,所述一个或多个逻辑信号代表施加到所述输入逻辑信号的逻辑功能,所述逻辑功能由所述阈值电压和所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的所述配置来决定,其中,所述阈值电压可受控制来改变所述逻辑功能;以及
将读取输入信号施加到所述多个可重配置的非易失性的基于电阻的结电路中的每一者,其中所述读取输入信号小于写入输入信号的量值,且太小以致无法改变所述非易失性的基于电阻的结电路的电阻状态。
14.根据权利要求13所述的方法,其进一步包含:
在所述多个可重配置的非易失性的基于电阻的结电路与评估开关之间的互连件处,基于所述多个可重配置的非易失性的基于电阻的结电路的电阻状态的配置而读取输出信号。
15.根据权利要求14所述的方法,其进一步包含:
由所述传感器电路来检测所述输出信号,该传感器电路以操作方式耦合到所述互连件;以及
基于经检测的输出信号和所述阈值电压而输出选定的一个或多个逻辑信号。
16.根据权利要求15所述的方法,其中所述传感器电路的所述输出信号包含逻辑1和/或逻辑0。
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US12/192,386 US8295082B2 (en) | 2008-08-15 | 2008-08-15 | Gate level reconfigurable magnetic logic |
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CN110971217B (zh) * | 2019-11-12 | 2023-08-29 | 杭州电子科技大学 | 一种基于mtj的非易失可编程开关 |
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JP5485272B2 (ja) | 2014-05-07 |
KR20110044910A (ko) | 2011-05-02 |
WO2010019881A1 (en) | 2010-02-18 |
KR101308579B1 (ko) | 2013-09-13 |
JP2014099237A (ja) | 2014-05-29 |
US8295082B2 (en) | 2012-10-23 |
TW201030744A (en) | 2010-08-16 |
EP2313892B1 (en) | 2014-04-30 |
JP5735091B2 (ja) | 2015-06-17 |
EP2313892A1 (en) | 2011-04-27 |
US20100039136A1 (en) | 2010-02-18 |
JP2012500446A (ja) | 2012-01-05 |
CN102099862A (zh) | 2011-06-15 |
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