CN101999168A - 为小直径、高密度晶片贯通孔裸片堆叠形成对准/对心导引件的方法 - Google Patents

为小直径、高密度晶片贯通孔裸片堆叠形成对准/对心导引件的方法 Download PDF

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CN101999168A
CN101999168A CN2009801127740A CN200980112774A CN101999168A CN 101999168 A CN101999168 A CN 101999168A CN 2009801127740 A CN2009801127740 A CN 2009801127740A CN 200980112774 A CN200980112774 A CN 200980112774A CN 101999168 A CN101999168 A CN 101999168A
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nude film
wafer
die stack
alignment
alignment characteristics
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CN101999168B (zh
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戴维·普拉特
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Micron Technology Inc
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Abstract

本发明提供一种形成裸片堆叠的方法。所述方法包括在第一裸片中形成多个晶片贯通孔(105)和第一多个对准特征(104)。在第二裸片中形成第二多个对准特征(116)，且将所述第一裸片堆叠在所述第二裸片上，使得所述第一多个对准特征啮合所述第二多个对准特征。还提供一种制造裸片堆叠的方法，其包括：在第一裸片上形成多个晶片贯通孔；在第一裸片上形成多个凹座(104)；以及在第二裸片上形成多个突起(116)。还提供一种裸片堆叠和一种系统。

Description

为小直径、高密度晶片贯通孔裸片堆叠形成对准/对心导引件的方法
技术领域
本发明大体上涉及半导体装置，且更明确地说，涉及使用晶片贯通孔的可堆叠裸片。
背景技术
微处理器控制的电路用于各种各样的应用中。此些应用包括个人计算机、蜂窝式电话、数字相机、控制系统以及其它消费类产品的主机。个人计算机、数字相机等一般包括为系统处置不同功能的各种组件，例如微处理器。通过组合这些组件，可将各种消费类产品和系统设计成满足特定需要。微处理器本质上是在软件程序的控制下执行特定功能的通用装置。这些软件程序一般存储在耦合到微处理器和/或其它外围设备的一个或一个以上存储器装置中。
例如微处理器和存储器装置等电子组件常常包括制造于半导体衬底上且一起耦合在封装中的众多集成电路。为增加所述电路的密度，所述电路可经垂直堆叠，从而减少电路的“占用面积”。为进一步减少电路的占用面积并改进裸片之间的电连接性，裸片可通过晶片贯通孔(例如，硅贯通孔或TSV)而互连，其中通孔穿过裸片的硅，以提供垂直互连。通过用TSV代替通常位于裸片的边缘上的条带、焊线或其它连接技术，可减小电路的长度和宽度。另外，使用TSV进行互连可消除对裸片之间的插入件的需要。然而，因为TSV必须贯穿电路的整个经堆叠裸片而对准，所以裸片在制造期间的对准可能存在挑战性，尤其是相对于直径小且/或密度较高的TSV来说。
附图说明
图1说明根据本发明实施例的基于处理器的装置的框图；
图2A到图2D说明根据本发明实施例的对准凹座和突起的形成；
图3A到图3B说明根据本发明另一实施例的对准凹座和突起的形成；
图4A到图4C说明根据本发明另一实施例的对准凹座和突起的形成；
图5A到图5B说明根据本发明另一实施例的对准凹座和突起的形成；
图6说明根据本发明另一实施例的对准突起的形成；
图7描绘根据本发明实施例的用于形成对准特征的工艺；
图8描绘根据本发明另一实施例的用于在钝化处理期间形成对准特征的工艺；以及
图9描绘根据本发明另一实施例的用于在钝化处理期间形成对准特征的工艺。
具体实施方式
图1是含有可使用本发明的实施例的集成电路装置的电子系统的框图。由参考标号10概括指示的所述电子装置或系统可为多种类型中的任一者，例如计算机、数字相机、蜂窝式电话、个人备忘记事本等。在典型的基于处理器的装置中，处理器12(例如微处理器)控制系统功能和请求的操作。
依据系统10所执行的功能，各种装置可耦合到处理器12。举例来说，输入装置14可耦合到处理器12以接收来自用户的输入。输入装置14可包含用户接口，且可包括按钮、开关、键盘、光笔、鼠标、数字转换器、语音识别系统或许多其它输入装置中的任一者。音频或视频显示器16也可耦合到处理器12以将信息提供给用户。显示器16可包括(例如)LCD显示器、CRT显示器或LED。另外，系统10可包括电源18，其可包含(例如)电池、电池接受器、交流电源适配器或直流电源适配器。电源18可将电力提供给系统10的一个或一个以上组件。
射频(RF)子系统/基带处理器20可耦合到处理器12，以提供无线通信能力。RF子系统/基带处理器20可包括天线，其耦合到RF接收器且耦合到RF发射器(未图示)。此外，通信端口22可适合于提供电子系统10与外围装置24之间的通信接口。外围装置24可包括笔记型计算机扩展坞(docking station)、扩充坞(expansion bay)或其它外部组件。
处理器12可耦合到各种类型的存储器装置以便利其操作。举例来说，处理器12可连接到存储器26，存储器26可包括易失性存储器、非易失性存储器或两者。存储器26的易失性存储器可包含多种存储器类型，例如静态随机存取存储器(“SRAM”)；动态随机存取存储器(“DRAM”)；第一代、第二代或第三代双数据速率存储器(分别为“DDR1”、“DDR2”或“DDR3”)等。存储器26的非易失性存储器可包含各种类型的存储器，例如电可编程只读存储器(“EPROM”)或快闪存储器。另外，非易失性存储器可包括高容量存储器，例如磁带或磁盘驱动器存储器。
系统10可包括多个半导体装置。举例来说，除处理器12和存储器26之外，系统10还可包括耦合到处理器12以提供数字成像功能性的图像传感器或成像器28。成像器28可包括电荷耦合装置(CCD)传感器或互补金属氧化物半导体(CMOS)传感器，其具有经配置以受光子冲击且经由光电效应将此冲击转换成电流的光感受器或像素单元的阵列。虽然成像器28可(例如借助于电路板)从处理器12远程耦合，但成像器28和处理器12可改为一体成形(例如)于共用衬底上。
系统10的处理器12、存储器26、成像器28和任何其它装置或组件可为根据下文进一步描述的技术而制造的集成电路或封装。举例来说，处理器12可为具有以垂直布置堆叠的两个或两个以上裸片的集成电路。如上文所论述，裸片可借助穿过每一裸片的晶片贯通孔而电互连。然而，随着间距和直径的大小减小以适应较小裸片和集成电路的较小占用面积，裸片在裸片堆叠处理期间的对准对于晶片贯通孔的对准和集成电路的恰当操作来说是至关重要的。
图2到图6说明根据本发明实施例的对准凹座和突起的形成以促进裸片堆叠期间晶片贯通孔的对准。如将了解，晶片可包括可根据下文所描述的技术来处理的任何数目的裸片。举例来说，尽管本文中所揭示的技术是在例如底部裸片和顶部裸片等一个或一个以上裸片的情形中加以论述，但是所述处理可对一个或一个以上晶片，对从晶片切除之后的一个或一个以上个别裸片，或其任何组合执行。
转向图2A到图2D，图2A说明可放置在集成电路的裸片堆叠的“底部”上的裸片100。裸片100包括背侧表面101。裸片100可具有蚀刻到裸片100中且延伸穿过衬底的多个晶片贯通孔102，且还可包括接合衬垫103。举例来说，在例如光刻和蚀刻等深通孔图案化处理期间，可能已形成晶片贯通孔102。另外，在通孔图案化处理期间，多个对准凹座104可经图案化且蚀刻到裸片100的衬底中。可用选定的特殊布置来图案化对准凹座104。举例来说，在一个实施例中，可在晶片上的裸片街(die street)和交叉处或附近图案化和蚀刻对准凹座104。对准凹座104可为任何大小、形状或深度。然而，为确保对准凹座104在裸片100的后续处理期间保持开放，在一实施例中，对准凹座104可被蚀刻至少或大于晶片贯通孔102的深度。
现在转向图2B，一旦已图案化和蚀刻了晶片贯通孔102和对准凹座104，就可用铜或例如多晶硅或钨等其它互连材料来填充通孔102。填充有铜的通孔105和裸片100可经由例如载体附接、背研磨、硅凸版蚀刻等各种工艺来处理。举例来说，可通过背研磨裸片100的背侧来使TSV在表面101上暴露。另外，可在未蚀刻TSV的情况下蚀刻裸片100的表面101，使得TSV延伸超过裸片100的表面101。为促进裸片堆叠中的堆叠，裸片100可首先经翻转，使得背侧表面101现在暴露以供处理。也可将裸片100放置到例如硅载体等载体106上，且借助粘合剂108而紧固。在形成TSV的背研磨步骤期间，对准凹座104可在裸片100的背侧110上暴露。
图2C说明可耦合到集成电路中的“底部”裸片100的例如“顶部”裸片的另一裸片112。裸片112可包括多个接合衬垫114，其经配置以耦合到第二或底部裸片(例如裸片100)的晶片贯通孔。为促进顶部裸片112的接合衬垫114与底部裸片100的经填充的通孔105的对准，顶部裸片可包括从裸片112的衬底延伸的多个对准突起116。对准突起116可通过例如光刻、立体平版印刷等任何合适处理来形成。举例来说，突起可为有角度的结构，且可具有任何斜度或垂直度，如由平版印刷处理期间的光致抗蚀剂图案化决定。另外，对准突起116可具有任何形状、大小或形貌，例如锥形、矩形、四面体等。另外，可将对准突起116的形状、大小或形貌选择为较好地匹配底部裸片100上的对准凹座104。
为形成裸片堆叠，顶部裸片112可如图2D中所说明那样堆叠在底部裸片100上。在堆叠处理之前，顶部裸片112和底部裸片100可经历钝化处理。举例来说，钝化层118可形成于底部裸片上，且钝化层120也可形成于顶部裸片上。钝化层118和120还可分别安置于对准凹座104上和对准突起116的顶部上。有利的是，在钝化步骤期间无需额外的处理来适应对准凹座104和突起116。
如图2D中所说明，底部裸片100可首先已放置到例如硅载体等载体106上，且借助于粘合剂层108而紧固。如上文所论述，为确保顶部裸片112与底部裸片100之间的电互连，顶部裸片112的接合衬垫114应与底部裸片100的经填充的晶片贯通孔105对准。为确保顶部裸片112的接合衬垫114与底部裸片100的晶片贯通孔105对准，顶部裸片的对准突起116可啮合底部裸片100上的凹座104。因此，在裸片堆叠处理期间，接合衬垫114与晶片贯通孔102的对准并不受限于执行堆叠操作的工具的准确度。代替的是，在更准确的平版印刷和蚀刻处理期间形成的对准突起116和凹座104提供较好的对准准确度，且确保底部裸片100与顶部裸片112以特定对准堆叠。
一旦裸片已堆叠，就可接着移动经堆叠的裸片以进行进一步处理，例如接合衬垫与晶片贯通孔连接的回焊、底部填充等。可通过任何合适的技术来促进接合衬垫与晶片贯通孔之间的电连接。举例来说，可将焊球安置在接合衬垫114上以接触经填充的通孔105。对于较小间距的通孔和接合衬垫，可通过任何其它合适的技术来促进所述接触，例如：在通孔105和接合衬垫114上沉积例如镍/钯/金金属等凸块底部金属层(UBM)材料；在接合衬垫114和/或通孔105上沉积例如锡、铟/金或其它金属等金属；热超声波接合；和/或在接合衬垫114上镀焊接掩模。
接着必须将裸片堆叠从堆叠位置(例如，取放工具)移到工艺中的下一步骤。底部裸片100相对顶部裸片112的任何移动都可能影响接合衬垫114与晶片贯通孔102之间的接触，从而导致连接不佳或无连接，且影响裸片堆叠的良率。对准凹座104和突起116可提供额外的“互锁”功能，以防止底部裸片100和顶部裸片112在裸片堆叠的重定位期间的移动。举例来说，顶部裸片112的对准突起116与底部裸片100的对准凹座104之间的接触防止裸片100和112的移动，以及提供堆叠期间的对准功能。
图3A和图3B说明根据本发明另一实施例的对准凹座和突起的形成。图3A描绘第一裸片200(例如底部裸片)，其具有多个晶片贯通孔202，安置于硅载体204上且由粘合层206紧固。如图3A中所说明，裸片200已经受必要处理以形成和填充晶片贯通孔202。在此实施例中，多个对准凹座208可在背侧钝化处理期间形成，例如在晶片贯通孔的形成和填充之后形成。钝化层210可在对准凹座208形成之前已形成。在钝化层210形成之后，对准凹座208可例如通过干式或湿式蚀刻或任何合适的工艺而图案化和蚀刻。可以任何所要深度或角度来蚀刻对准凹座208，且对准凹座208可为任何大小、形状或形貌。举例来说，可使用各向同性(无方向性)或各向异性(方向性)来蚀刻凹座208，以控制凹座208的形状和角度。各向同性蚀刻可提供具有倾斜或有角度侧面的凹座208，而各向异性蚀刻可提供具有垂直侧面的凹座208。
在图3B中，展示裸片堆叠212，其包括具有多个接合衬垫215和多个对准突起216的顶部裸片214，以及具有如上文所论述而形成的对准凹座208的底部裸片200。顶部裸片214上的对准突起216可通过任何合适工艺而形成，例如通过如上文在图2C中所描述的光刻或立体平版印刷而形成。为确保顶部裸片214的接合衬垫215与底部裸片200的晶片贯通孔202对准，顶部裸片214的对准突起216可与底部裸片200的凹座208耦合。如上文所论述，这些对准特征216和208可提供优于堆叠工具的对准准确度，从而确保顶部裸片214的接合衬垫215与晶片贯通孔202的充分对准。类似地，如上文所论述，对准凹座208与对准突起216的啮合也可防止顶部裸片214和底部裸片200在裸片堆叠212重定位到下游处理区域期间移位。
图4A到图4C说明本发明的又一实施例。如图4A中所说明，多个对准突起300可形成于底部裸片302上。如图4A中所说明，底部裸片302已经历众多处理步骤，例如用以形成晶片贯通孔304的光刻和蚀刻，以及使经填充的晶片贯通孔304外露的背研磨。另外，将底部裸片302展示为准备好进行堆叠，且借助粘合层308紧固到硅载体306。对准突起300可在底部裸片302的背侧钝化处理期间或之后图案化，因为裸片302可包括钝化层310。举例来说，对准突起300可在此处理期间使用光刻和掩模(例如衰减式铬掩模)来形成。有利的是，在此实施例中，对准突起300的形成在平版印刷和蚀刻期间未添加额外处理步骤，因为对准突起300是在背侧钝化处理期间或之后形成。
图4B说明顶部裸片312，其具有经配置以耦合到底部裸片302的晶片贯通孔304的接合衬垫314。顶部裸片312还包括多个对准凹座316，其经配置以啮合底部裸片302的对准突起300。在图4B中所描绘的实施例中，在钝化处理之后图案化和蚀刻顶部裸片312的对准凹座316，如由钝化层318的描绘所说明。在一实施例中，可在钝化处理期间或之后图案化和蚀刻对准凹座316，如上文所描述。
图4C说明包括底部裸片302和顶部裸片312的裸片堆叠320。如上文所论述，底部裸片302的晶片贯通孔304与顶部裸片312的接合衬垫314的对准可由对准特征300和316的啮合来促进。举例来说，底部裸片302的对准突起300可啮合顶部裸片312的对准凹座316。另外，对准突起300与对准凹座316的啮合可防止裸片302和312在裸片堆叠320重定位到另一区域以供进一步处理期间滑动或移动。
图5A和图5B描绘底部裸片400和顶部裸片402，其具有与图4A和图4B中所描述相类似的对准特征。在图5A中，将底部裸片400展示为具有多个晶片贯通孔404，且展示为借助于粘合层408紧固到硅载体406。底部裸片400可包括多个对准突起410，其是通过上文所描述的技术中的任一者而形成，例如在光刻处理期间、在前侧或背侧钝化期间等通过图案化和蚀刻而形成。在所说明的实施例中，对准突起可在背侧钝化处理期间或之后形成，如由钝化层412的存在所说明。
图5B描绘顶部裸片402，其具有经配置以耦合到底部裸片400的多个晶片贯通孔404的多个接合衬垫414。另外，顶部裸片402包括在顶部裸片402的钝化期间或之后形成的多个对准凹座416，如由钝化层418的描绘所说明。与上文在图4B中所描绘的实施例形成对比，对准凹座416经蚀刻以使得其仅延伸到顶部裸片402的钝化层418中，且不延伸到硅中。有利的是，将对准凹座416蚀刻到钝化层418中防止对顶部裸片402的硅的任何意外损伤，且可降低将凹座蚀刻到裸片402的通孔或其它关键区域中的可能性。底部裸片400和顶部裸片402可一起堆叠在(例如)图4C所描绘的裸片堆叠中。底部裸片400的对准突起410可啮合顶部裸片402的钝化层418中的对准凹座416，从而提供如上文所描述的对准优势。
图6描绘用于对准经堆叠的裸片的对准特征的又一实施例。图中所说明的裸片堆叠500可包括顶部裸片502和底部裸片504，底部裸片504借助粘合层508紧固到硅载体506。在所说明的实施例中，多个对准突起510可形成于底部裸片504中，且第二多个对准突起512可形成于顶部裸片502中。对准突起510和512可促进底部裸片504的多个晶片贯通孔511与顶部裸片502的接合衬垫513的对准。
举例来说，如图5中所示，底部裸片504上的对准突起510可经布置以使得顶部裸片502上的对准突起512在对准突起510之间滑动。如上文所论述，顶部裸片502的对准突起512和底部裸片504的对准突起510可在形成钝化层514和516的钝化处理期间或之后形成。对准突起510和512可为任何大小、形状和形貌，且底部裸片504上的对准突起510可为与顶部裸片502上的对准突起512相同或不同的大小、形状和形貌。有利的是，底部裸片504或顶部裸片502上的对准突起510和512的形成无需蚀刻到顶部裸片502或底部裸片504的硅中。
如上文所论述，根据本发明的实施例，各种对准特征可形成于两个或两个以上裸片上以促进裸片堆叠的形成期间的对准。如下文进一步更详细地描述，这些对准特征的形成可在裸片的处理期间在额外步骤中执行，或对准特征的形成可整合到已有处理步骤中。用以形成对准特征的技术的选择可视对准特征的大小、形状和类型以及处理晶片时所需的额外成本或时间而定。举例来说，与特别针对对准特征的形成而添加新的处理步骤相对比，通过将对准特征的形成整合于裸片的已有处理步骤中来使成本减到最小可能是有利的。另外，为对准特征的形成而选择的处理步骤对于堆叠中的每一裸片可为不同的，且此些技术可应用于具有两个、三个、四个或任何数目的裸片的多裸片堆叠。
图7到图9说明根据本发明实施例的形成各种对准特征的工艺。应了解，图7到图9中所说明的工艺可包括在对准特征的形成之前或之后进行的任何额外处理步骤，且裸片的处理不限于所示的处理步骤。另外，所说明的工艺可应用于任何数目的裸片，且在一些实施例中，可使用不同工艺来形成不同裸片或裸片的组合。
现在转到图7，展示根据本发明实施例的用于形成对准特征的工艺600。在图7中，可在用以形成晶片贯通孔的平版印刷和蚀刻处理期间形成对准凹座，例如图2A到图2D中所说明。起初，可通过光刻、蚀刻和/或任何其它合适的工艺将晶片贯通孔图案化到底部裸片中(步骤602)。还可在晶片贯通孔的图案化和蚀刻期间图案化和蚀刻对准凹座(步骤604)。在其它实施例中，可在晶片贯通孔的图案化和蚀刻之后图案化和蚀刻对准凹座。在已图案化和蚀刻晶片贯通孔和对准凹座之后，底部裸片可经历例如载体附接、背研磨、硅凸版等进一步处理。在例如用铜、聚合物或其它合适的材料填充晶片贯通孔之后，裸片可经历背研磨处理以使通孔暴露且使对准凹座暴露(步骤606)。
为啮合对准凹座，可将对准突起图案化到第二或顶部裸片中(步骤608)。在对准特征形成之后，可对顶部和底部裸片执行钝化处理以形成钝化层(步骤610)。因此，在此实施例中，钝化层形成于底部裸片和顶部裸片的对准凹座和对准突起上。底部裸片和顶部裸片可经堆叠，从而依靠对准突起的啮合来使顶部裸片与底部裸片准确地对准(步骤612)。一旦形成裸片堆叠，就可移动裸片堆叠以供进一步处理(步骤614)。如上文所论述，当移动堆叠时，对准特征还防止裸片堆叠中的裸片移位或移动，从而确保任何接合衬垫和通孔在处理的持续时间内保持对准。
图8描绘根据本发明另一实施例的用于在钝化处理期间形成对准特征的工艺700，例如图3A到图3B以及图4A到图4C中所说明。如上文所论述，可通过光刻、蚀刻和/或任何其它合适的工艺将晶片贯通孔图案化和蚀刻到底部裸片中(步骤702)。裸片可经历例如背研磨处理等进一步处理，以使晶片贯通孔打开(步骤704)。为促进裸片堆叠的对准，可将对准插入件图案化到顶部裸片中(步骤706)。接下来，可对底部和顶部裸片执行钝化处理(步骤708)。为在底部裸片中形成对准特征，可在钝化处理期间将对准凹座图案化和蚀刻到底部裸片中(步骤710)。一旦两个裸片都具有对准特征，就可使用对准特征的啮合以使裸片的接合衬垫与晶片贯通孔准确地对准来堆叠裸片以形成裸片堆叠(步骤712)。也可继续移动裸片堆叠以供进一步处理，其中经啮合的对准特征防止裸片在堆叠的移动期间移位(步骤714)。
现在转向图9，说明根据本发明另一实施例的用于在钝化处理期间形成对准特征的工艺800，例如图3A到图3B以及图4A到图4C中所描绘。起初，可将晶片贯通孔图案化和蚀刻到底部裸片中(步骤802)，且裸片可经历例如背研磨处理等进一步处理以使晶片贯通孔暴露(步骤804)。接下来，底部裸片和顶部裸片两者都可经历钝化处理(步骤806)。在底部裸片的背侧钝化期间或之后，可将对准突起图案化和蚀刻到底部裸片上(步骤808)。类似地，在顶部裸片的前侧钝化期间或之后，可将对准凹座图案化和蚀刻到顶部裸片上(步骤810)。在钝化处理期间相应对准特征的形成之后，可使用对准突起与对准凹座的啮合以使裸片准确地对准来堆叠顶部和底部裸片以形成裸片堆叠(步骤812)。可接着移动裸片堆叠以供进一步处理，其中经啮合的对准特征使堆叠进一步稳定(步骤814)。
虽然本发明可容易存在各种修改和替代形式，但已在图式中作为实例展示了特定实施例，且本文中已详细描述了所述特定实施例。然而，应理解，本发明无意限于所揭示的特定形式。相反，本发明将覆盖属于由所附权利要求书所界定的本发明的精神和范围内的所有修改、均等物和替代方案。

Claims (24)

1.一种形成裸片堆叠的方法，其包含：
在第一裸片中形成多个晶片贯通孔；以及
在第一裸片中形成一个或一个以上对准特征。
2.根据权利要求1所述的方法，其包含在第二裸片中形成一个或一个以上对准特征。
3.根据权利要求1所述的方法，其包含将所述第二裸片堆叠在所述第一裸片上。
4.根据权利要求1所述的方法，其中所述对准特征包含多个开口。
5.根据权利要求1所述的方法，其中所述多个开口延伸至少与所述多个晶片贯通孔离所述裸片的表面一样远的距离。
6.根据权利要求1所述的方法，其中所述对准特征包含从所述裸片延伸的多个突起。
7.根据权利要求1所述的方法，其中形成所述一个或一个以上对准特征包含通过光刻、立体平版印刷、湿式蚀刻、干式蚀刻、钝化或其组合来形成所述对准特征。
8.根据权利要求1所述的方法，其包含拾取所述第一裸片和将所述第一裸片放置到所述第二裸片上，使得所述第一裸片的所述对准特征啮合所述第二裸片的所述对准特征。
9.根据权利要求1所述的方法，其包含将所述裸片堆叠放置在固化炉中。
10.一种制造裸片堆叠的方法，其包含：
在第一裸片上形成多个晶片贯通孔；
在第一裸片上形成多个凹座；以及
在第二裸片上形成多个突起，其中所述多个突起经配置以啮合所述多个凹座，以
使所述第二裸片的多个接合衬垫与所述第一裸片的所述多个晶片贯通孔对准。
11.根据权利要求9所述的方法，其包含将所述第一裸片堆叠到所述第二裸片上，使得所述多个凹座啮合所述多个突起。
12.根据权利要求9所述的方法，其包含将所述第二裸片堆叠到所述第一裸片上，使得所述多个突起啮合所述多个凹座。
13.根据权利要求9所述的方法，其中在第一裸片上形成所述多个凹座包含在安置于第一天上的层中形成多个凹座。
14.根据权利要求12所述的方法，其中所述层包含钝化层。
15.一种制造半导体装置的方法，其包含：
在晶片中形成多个对准特征；
将所述晶片切割成多个裸片，使得每一裸片包含所述多个对准特征中的一者或一者以上；
在所述多个裸片中的第一裸片中形成多个晶片贯通孔。
16.根据权利要求15所述的方法，其中形成多个对准特征包含在所述晶片的多个裸片街处形成所述多个对准特征。
17.一种裸片堆叠，其包含：
第一裸片，其具有第一多个对准特征和多个晶片贯通孔；以及
第二裸片，其具有第二多个对准特征和多个接合衬垫，其中所述第二裸片的所述第二多个对准特征经配置以啮合所述第一裸片的所述第一多个对准特征，使得所述第二裸片的所述多个接合衬垫与所述第一裸片的所述多个晶片贯通孔对准。
18.根据权利要求9所述的裸片堆叠，其中所述第二裸片的所述多个接合衬垫经配置以啮合所述第一裸片的所述多个晶片贯通孔。
19.根据权利要求15所述的裸片堆叠，其中所述第一多个对准特征包含多个凹座。
20.根据权利要求17所述的裸片堆叠，其中所述第二多个对准特征包含从所述裸片的表面延伸的多个突起。
21.根据权利要求15所述的裸片堆叠，其中所述第一多个对准特征和所述第二多个对准特征包含多个突起。
22.一种系统，其包含：
电子装置，其包含：
处理器；
一个或一个以上半导体装置，其中所述一个或一个以上半导体装置包含裸片堆叠，其中所述裸片堆叠包含第一裸片，其具有第一多个对准特征和晶片贯通孔。
23.根据权利要求21所述的系统，其中根据权利要求21所述的裸片堆叠，其中所述裸片堆叠包含第二裸片，其具有第二多个对准特征。
24.一种裸片堆叠，其包含：
第一裸片，其具有第一多个突起和多个晶片贯通孔；以及
第二裸片，其具有第二多个突起，其中所述第二多个突起经配置以啮合所述第一多个突起。
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CN113169078B (zh) * 2018-10-18 2024-05-24 欧司朗光电半导体有限公司 制造电子元件的方法、电子元件和制造半导体芯片的方法

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KR101617900B1 (ko) 2016-05-03
TWI483379B (zh) 2015-05-01
TW201419492A (zh) 2014-05-16
WO2009126412A1 (en) 2009-10-15
KR20100132545A (ko) 2010-12-17
CN101999168B (zh) 2013-05-22
US20090255705A1 (en) 2009-10-15
TWI499029B (zh) 2015-09-01
JP2011517114A (ja) 2011-05-26
US9136259B2 (en) 2015-09-15
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