TWI499029B - 用於小直徑、高密度晶圓貫通孔的晶片堆疊時建立對準／對心導引的方法 - Google Patents

用於小直徑、高密度晶圓貫通孔的晶片堆疊時建立對準／對心導引的方法 Download PDF

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TWI499029B
TWI499029B TW098109935A TW98109935A TWI499029B TW I499029 B TWI499029 B TW I499029B TW 098109935 A TW098109935 A TW 098109935A TW 98109935 A TW98109935 A TW 98109935A TW I499029 B TWI499029 B TW I499029B
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wafer
alignment
protrusions
alignment features
vias
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TW200950056A (en
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Dave Pratt
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Micron Technology Inc
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Description

用於小直徑、高密度晶圓貫通孔的晶片堆疊時建立對準/對心導引的方法
本發明大體上係關於半導體器件，且更特定言之，係關於使用晶圓貫通孔之可堆疊晶片。
微處理器控制之電路用於廣泛種類之應用中。此等應用包括個人電腦、蜂巢式電話、數位攝影機、控制系統及其他消費者產品之主機。個人電腦、數位攝影機或其類似物一般包括處理系統之不同功能之各種組件，諸如微處理器。藉由組合此等組件，各種消費者產品及系統可經設計以滿足特定需要。微處理器本質上為在軟體程式之控制下執行特定功能之通用器件。此等軟體程式一般儲存於耦接至微處理器及/或其他周邊設備之一或多個記憶體器件中。
諸如微處理器及記憶體器件之電子組件常常包括製造於半導體基板上且一起耦接於封裝中之眾多積體電路。為增加電路之密度，電路可經垂直堆疊，從而減少電路之「佔據面積」。為進一步減少電路之佔據面積及改良晶片之間的電連接性，晶片可由晶圓貫通孔(例如，矽貫通孔或TSV)互連，其中孔通過晶片之矽以提供垂直互連。藉由以TSV替換通常位於晶片之邊緣上之條帶、焊線或其他連接技術，可減少電路的長度及寬度。另外，使用TSV進行互連可消除對晶片之間的插入物之需要。然而，因為TSV必須貫穿電路之整個經堆疊晶片而對準，所以晶片在製造期間的對準可能存在挑戰性，尤其關於直徑小及/或密度較高之TSV而言。
圖1為含有可使用本發明之實施例之積體電路器件之電子系統的方塊圖。一般由參考數字10指示，該電子器件或系統可為各種類型中之任一者，諸如電腦、數位攝影機、蜂巢式電話、個人行事曆或其類似物。在典型基於處理器之器件中，諸如微處理器之處理器12控制系統功能及請求的操作。
視系統10執行之功能，各種器件可耦接至處理器12。舉例而言，輸入器件14可耦接至處理器12以接收使用者之輸入。輸入器件14可包含使用者介面且可包括按鈕、開關、鍵盤、光筆、滑鼠、數位轉換器、語音識別系統或許多其他任何輸入器件。音訊或視訊顯示器16亦可耦接至處理器12以將資訊提供至使用者。顯示器16可包括，(例如)，LCD顯示器、CRT顯示器或LED。另外，系統10可包括電源18，其可包含，(例如)，電池、電池容納器、交流電配接器或直流電配接器。電源18可將電力提供至系統10之一或多個組件。
射頻(RF)子系統/基頻處理器20可耦接至處理器12以提供無線通信能力。RF子系統/基頻處理器20可包括天線，其耦接至RF接收器及RF傳輸器(未圖示)。此外，通信埠22可經調適以提供電子系統10與周邊器件24之間的通信介面。周邊器件24可包括筆記型電腦擴展塢(docking station)、擴充塢(expansion bay)或其他外部組件。
處理器12可耦接至各種類型之記憶體器件以便利其操作。舉例而言，處理器12可連接至記憶體26，其可包括揮發性記憶體、非揮發性記憶體或兩者。記憶體26之揮發性記憶體可包含各種記憶體類型，諸如靜態隨機存取記憶體(「SRAM」)、動態隨機存取記憶體(「DRAM」)、第一代、第二代或第三代雙倍資料速率記憶體(分別為「DDR1」、「DDR2」或「DDR3」)或其類似物。記憶體26之非揮發性記憶體可包含各種類型之記憶體，諸如電可程式化唯讀記憶體(「EPROM」)或快閃記憶體。另外，非揮發性記憶體可包括高容量記憶體，諸如磁帶或磁碟驅動機記憶體。
系統10可包括多個半導體器件。舉例而言，除處理器12及記憶體26之外，系統10亦可包括耦接至處理器12以提供數位成像功能性之影像感測器或成像器28。成像器28可包括電荷耦合器件(CCD)感測器或互補金屬氧化物半導體(CMOS)感測器，其具有經組態以受光子衝擊且經由光電效應將此衝擊轉換為電流之光感受器或像素單元之陣列。雖然成像器28可(諸如借助於電路板)自處理器12遠端耦接，但是成像器28及處理器12可替而(諸如於共同基板上)經一體成形。
處理器12、記憶體26、成像器28及系統10之任何其他器件或組件可為根據下文進一步描述之技術製造的積體電路或封裝。舉例而言，處理器12可為具有以垂直配置堆疊之兩個或兩個以上晶片之積體電路。如上文所論述，晶片可由通過每一晶片之晶圓貫通孔電互連。然而，隨著間距及直徑在尺寸上減小以適應較小晶片及積體電路之較小佔據面積，晶片堆疊處理期間的晶片之對準對於晶圓貫通孔之對準及積體電路的恰當操作為至關重要的。
圖2至圖6說明根據本發明之實施例對準凹座及突起之形成以促進晶片堆疊期間晶圓貫通孔的對準。如將所瞭解，晶圓可包括可根據以下描述之技術處理之任何數目的晶片。舉例而言，儘管本文中所揭示之技術係在諸如底部晶片及頂部晶片之一或多個晶片的情形中加以論述，但是該處理可對一或多個晶圓，對自晶圓切除之後的一或多個個別晶片，或其任何組合執行。
轉至圖2A至圖2D，圖2A說明可置於積體電路之晶片堆疊之「底部」上的晶片100。晶片100包括背表面101。晶片100可具有經蝕刻至晶片100中且延伸通過基板之複數個晶圓貫通孔102且亦可包括結合襯墊103。舉例而言，在諸如光微影及蝕刻之深孔圖案化處理期間，可能已建立晶圓貫通孔102。另外，在孔圖案化處理期間，複數個對準凹座104可經圖案化及蝕刻至晶片100之基板中。可以選定之特定配置圖案化對準凹座104。舉例而言，在一實施例中，可在晶圓上之晶片街(die street)及交叉處或接近晶片街及交叉處圖案化及蝕刻對準凹座104。對準凹座104可為任何尺寸、形狀或深度。然而，為確保對準凹座104在晶片100之後續處理期間保持開放，在一實施例中，對準凹座104可經蝕刻至少或大於晶圓貫通孔102之深度。
現轉至圖2B，一旦已圖案化及蝕刻晶圓貫通孔102及對準凹座104，就可以銅或諸如多晶矽或鎢之其他互連材料填充孔102。銅填充之孔105及晶片100可經由諸如載體附接、背研磨、矽凸版蝕刻等各種製程處理。舉例而言，TSV可藉由背研磨晶片100之背面而曝露於表面101上。另外，可在未蝕刻TSV之情形下蝕刻晶片100之表面101，使得TSV延伸超出晶片100的表面101。為促進晶片堆疊中之堆疊，晶片100可首先經翻轉使得背表面101現經曝露以進行處理。晶片100亦可置於諸如矽載體之載體106上，且藉由黏著劑108緊固。在建立TSV之背研磨步驟期間，對準凹座104可曝露於晶片100之背面110上。
圖2C說明可耦接至積體電路中之「底部」晶片100之諸如「頂部」晶片之另一晶片112。晶片112可包括複數個結合襯墊114，其經組態以耦接至諸如晶片100之第二或底部晶片之晶圓貫通孔。為促進頂部晶片112之結合襯墊114與底部晶片100之經填充的孔105之對準，頂部晶片可包括自晶片112之基板延伸之複數個對準突起116。對準突起116可由諸如光微影、立體微影等之任何合適之製程建立。舉例而言，突起可為有角度之結構，且可具有任何程度之斜度或垂直度，如微影處理期間的光阻圖案化所確定。另外，對準突起116可具有任何形狀、尺寸或形貌，諸如錐形、矩形、四面體等。另外，對準突起116之形狀、尺寸或形貌可經選擇以更好地匹配底部晶片100上之對準凹座104。
為形成晶片堆疊，頂部晶片112可如圖2D中所說明堆疊於底部晶片100上。在堆疊處理之前，頂部晶片112及底部晶片100可經歷鈍化處理。舉例而言，鈍化層118可建立於底部晶片上，且鈍化層120亦可建立於頂部晶片上。鈍化層118及120亦可分別安置於對準凹座104上及對準突起116之頂部上。有利地，在鈍化步驟期間無需額外之處理來適應對準凹座104及突起116。
如圖2D中所說明，底部晶片100可首先置於諸如矽載體之載體106上，且由黏著劑之層108緊固。如上文所論述，為確保頂部晶片112與底部晶片100之間的電互連，頂部晶片112之結合襯墊114應與底部晶片100之經填充之晶圓貫通孔105對準。為確保頂部晶片112之結合襯墊114與底部晶片100之晶圓貫通孔105對準，頂部晶片的對準突起116可嚙合底部晶片100上之凹座104。因此，在晶片堆疊處理期間，結合襯墊114與晶圓貫通孔102之對準並不受限於執行堆疊操作之工具的精確度。而替代地，在更精確之微影及蝕刻處理期間所建立之對準突起116及凹座104，提供更佳之對準精確度且確保底部晶片100與頂部晶片112以特定對準堆疊。
一旦已堆疊晶片，就可接著移動經堆疊之晶片以進行進一步處理，諸如結合襯墊與晶圓貫通孔連接之回焊(reflow)、底部填充(underfilling)等。結合襯墊與晶圓貫通孔之間的電連接可由任何合適之技術促進。舉例而言，焊球可安置於結合襯墊114上以接觸經填充之孔105。對於較小間距之孔及結合襯墊，接觸可藉由任何其他合適之技術促進，諸如：在孔105及結合襯墊114上沈積諸如鎳/鈀/金金屬之凸塊底層金屬(UBM)材料；在結合襯墊114及/或孔105上沈積諸如錫、銦/金或其他金屬之金屬；熱超音波結合，及/或於結合襯墊114上鍍覆阻焊劑。
晶片堆疊接著必須自堆疊位置(例如，取放工具)移動至製程中之下一步驟。底部晶片100相對頂部晶片112之任何移動均可能影響結合襯墊114與晶圓貫通孔102之間的接觸，導致連接不佳或無連接及影響晶片堆疊之良率。對準凹座104及突起116可提供額外之「互鎖」功能以防止晶片堆疊之重定位期間底部晶片100及頂部晶片112的移動。舉例而言，頂部晶片112之對準突起116與底部晶片100之對準凹座104之間的接觸防止晶片100及112之移動，以及提供堆疊期間的對準功能。
圖3A及圖3B說明根據本發明之另一實施例之對準凹座及突起的形成。圖3A描繪諸如底部晶片之第一晶片200，其具有複數個晶圓貫通孔202，安置於矽載體204上且由黏著層206緊固。如圖3A中所說明，晶片200已經受必要處理以建立及填充晶圓貫通孔202。在此實施例中，複數個對準凹座208可在背面鈍化處理期間形成，例如，在晶圓貫通孔之形成及填充之後。在對準凹座208之形成之前可已形成鈍化層210。在鈍化層210之形成之後，對準凹座208可諸如藉由乾式或濕式蝕刻或任何合適之製程來圖案化及蝕刻。對準凹座208可蝕刻於任何所要深度或角度，且可為任何尺寸、形狀或形貌。舉例而言，凹座208可使用各向同性(無方向性)或各向異性(方向性)來蝕刻以控制凹座208之形狀及角度。各向同性蝕刻可提供具有傾斜或有角度側面之凹座208，而各向異性蝕刻可提供具有垂直側面之凹座208。
在圖3B中，展示晶片堆疊212，其包括具有複數個結合襯墊215及複數個對準突起216之頂部晶片214，及具有如上文所論述形成之對準凹座208的底部晶片200。頂部晶片214上之對準突起216可藉由任何合適之製程形成，諸如藉由如上文在圖2C中所描述之光微影或立體微影。為確保頂部晶片214之結合襯墊215與底部晶片200之晶圓貫通孔202對準，頂部晶片214的對準突起216可與底部晶片200之凹座208耦接。如上文所論述，此等對準特徵216及208可提供佳於堆疊工具之對準精確度，因而確保頂部晶片214之結合襯墊215與晶圓貫通孔202的充分對準。類似地，如上文所論述，對準凹座208與對準突起216之嚙合亦可防止頂部晶片214及底部晶片200在晶片堆疊212之重定位至下游處理區域期間移位。
圖4A至圖4C說明本發明之又一實施例。如圖4A中所說明，複數個對準突起300可形成於底部晶片302上。如圖4A中所說明，底部晶片302已經歷眾多處理步驟，諸如建立晶圓貫通孔304之光微影及蝕刻，及揭露經填充之晶圓貫通孔304的背研磨。另外，底部晶片302展示為準備好進行堆疊且由黏著層308緊固至矽載體306。對準突起300可在底部晶片302之背面鈍化處理期間或之後經圖案化，因為晶片302可包括鈍化層310。舉例而言，對準突起300可在此處理期間使用光微影及遮罩(諸如衰減式鉻遮罩)來建立。有利地，在此實施例中，對準突起300之建立在微影及蝕刻期間未添加額外處理步驟，因為對準突起300係在背面鈍化處理期間或之後建立。
圖4B說明頂部晶片312，其具有經組態以耦接至底部晶片302之晶圓貫通孔304之結合襯墊314。頂部晶片312亦包括複數個對準凹座316，其經組態以嚙合底部晶片302之對準突起300。在圖4B中所描繪之實施例中，頂部晶片312之對準凹座316係在鈍化處理之後經圖案化及蝕刻，如由鈍化層318之描繪所說明。在一實施例中，對準凹座316可在鈍化處理期間或之後經圖案化及蝕刻，如上文所描述。
圖4C說明包括底部晶片302及頂部晶片312之晶片堆疊320。如上文所論述，底部晶片302之晶圓貫通孔304與頂部晶片312之結合襯墊314的對準可由對準特徵300及316的嚙合促進。舉例而言，底部晶片302之對準突起300可嚙合頂部晶片312之對準凹座316。另外，對準突起300與對準凹座316之嚙合可防止晶片302及312在晶片堆疊320之重定位至另一區域進行進一步處理期間滑動或移動。
圖5A及圖5B描繪底部晶片400及頂部晶片402，其具有與圖4A及圖4B中所描述相類似之對準特徵。在圖5A中，底部晶片400經展示具有複數個晶圓貫通孔404且經展示由黏著層408緊固至矽載體406。底部晶片400可包括複數個對準突起410，其係藉由上文所描述之任一技術形成，諸如藉由在光微影處理期間的圖案化及蝕刻，在正面或背面鈍化期間等。在所說明之實施例中，對準突起可在背面鈍化處理期間或之後形成，如由鈍化層412之存在所說明。
圖5B描繪頂部晶片402，其具有經組態以耦接至底部晶片400之複數個晶圓貫通孔404之複數個結合襯墊414。另外，頂部晶片402包括在頂部晶片402之鈍化期間或之後形成之複數個對準凹座416，如由鈍化層418的描繪所說明。與圖4B中在上文所描繪之實施例中，對準凹座416經蝕刻使得其僅延伸至頂部晶片402之鈍化層418中，且未延伸至矽中。有利地，將對準凹座416蝕刻至鈍化層418中防止對頂部晶片402之矽之任何意外損傷，且可降低將凹座蝕刻至晶片402之孔或其他關鍵區域中的可能性。底部晶片400及頂部晶片402可一起堆疊於(諸如)圖4C所描繪之晶片堆疊中。底部晶片400之對準突起410可嚙合頂部晶片402之鈍化層418中的對準凹座416，從而提供如上文所描述之對準優勢。
圖6描繪用於對準經堆疊之晶片之對準特徵的又一實施例。圖式中所說明之晶片堆疊500可包括頂部晶片502及底部晶片504，底部晶片504由黏著層508緊固至矽載體506。在所說明之實施例中，複數個對準突起510可形成於底部晶片504中，且第二複數個對準突起512可形成於頂部晶片502中。對準突起510及512可促進底部晶片504之複數個晶圓貫通孔511與頂部晶片502之結合襯墊513的對準。
舉例而言，如圖5中所示，底部晶片504上之對準突起510可經配置使得頂部晶片502上之對準突起512在對準突起510之間滑動。如上文所論述，頂部晶片502之對準突起512及底部晶片504之對準突起510可在建立鈍化層514及516的鈍化處理期間或之後形成。對準突起510及512可為任何尺寸、形狀及形貌，且底部晶片504上之對準突起510與頂部晶片502上之對準突起512可具有相同或不同的尺寸、形狀及形貌。有利地，底部晶片504或頂部晶片502上之對準突起510及512之建立無需蝕刻至頂部晶片502或底部晶片504的矽中。
如上文所論述，根據本發明之實施例，各種對準特徵可建立於兩個或兩個以上晶片上以促進晶片堆疊之建立期間的對準。如下文進一步更詳細地描述，此等對準特徵之建立可在晶片之處理期間在額外步驟中執行，或對準特徵的建立可整合於已有處理步驟中。用以建立對準特徵之技術之選擇可視對準特徵的尺寸、形狀及類型以及處理晶圓時需要之額外成本或時間而定。舉例而言，藉由將對準特徵之建立整合於晶片之已有處理步驟中可有利於最小化成本，與特別針對對準特徵之形成而添加新的處理步驟相反。另外，針對對準特徵之形成所選擇之處理步驟對於堆疊中的每一晶片可為不同的，且此等技術可應用於具有兩個、三個、四個或任何數目之晶片之多晶片堆疊。
圖7至圖9說明根據本發明之實施例之形成各種對準特徵的製程。應瞭解，圖7至圖9中所說明之製程可包括對準特徵之形成之前或之後進行的任何額外處理步驟，且晶片之處理不限於所示之處理步驟。另外，所說明之製程可應用於任何數目之晶片，且在一些實施例中，可使用不同製程形成不同晶片或晶片的組合。
現轉至圖7，展示根據本發明之實施例之形成對準特徵的製程600。在圖7中，可在用以建立晶圓貫通孔之微影及蝕刻處理期間形成對準凹座，諸如圖2A至圖2D中所說明。起初，可藉由光微影、蝕刻及/或任何其他合適之製程將晶圓貫通孔圖案化至底部晶片中(步驟602)。亦可在晶圓貫通孔之圖案化及蝕刻期間圖案化及蝕刻對準凹座(步驟604)。在其他實施例中，可在晶圓貫通孔之圖案化及蝕刻之後圖案化及蝕刻對準凹座。在已圖案化及蝕刻晶圓貫通孔及對準凹座之後，底部晶片可經歷諸如載體附接、背研磨、矽凸版等之進一步處理。在諸如以銅、聚合物或其他合適之材料填充晶圓貫通孔之後，晶片可經歷背研磨處理以曝露孔且曝露對準凹座(步驟606)。
為嚙合對準凹座，可將對準突起圖案化至第二或頂部晶片中(步驟608)。在對準特徵之形成之後，可對頂部及底部晶片執行鈍化處理以形成鈍化層(步驟610)。因此，在此實施例中，鈍化層形成於底部晶片及頂部晶片之對準凹座及對準突起上。底部晶片及頂部晶片可經堆疊，從而依賴於對準突起之嚙合將頂部晶片與底部晶片精確地對準(步驟612)。一旦形成晶片堆疊，就可移動晶片堆疊以進行進一步處理(步驟614)。如上文所論述，當移動堆疊時，對準特徵亦防止晶片堆疊中之晶片移位或移動，從而確保任何結合襯墊及孔在處理的持續時間內保持對準。
圖8描繪根據本發明之另一實施例之在鈍化處理期間形成對準特徵的製程700，諸如圖3A至圖3B及圖4A至圖4C中所說明。如上文所論述，可藉由光微影、蝕刻及/或任何其他合適之製程將晶圓貫通孔圖案化及蝕刻至底部晶片中(步驟702)。晶片可經歷諸如背研磨處理之進一步處理以顯現晶圓貫通孔(步驟704)。為促進晶片堆疊之對準，可將對準插入物圖案化至頂部晶片中(步驟704)。接著，可對底部及頂部晶片執行鈍化處理(步驟708)。為在底部晶片中建立對準特徵，可在鈍化處理期間將對準凹座圖案化及蝕刻至底部晶片中(步驟710)。一旦兩個晶片皆具有對準特徵，即可使用對準特徵之嚙合以精確地對準晶片之結合襯墊與晶圓貫通孔來堆疊晶片以形成晶片堆疊(步驟712)。亦可繼續移動晶片堆疊以進行進一步處理，其中經嚙合之對準特徵防止晶片在堆疊之移動期間移位(步驟714)。
現轉至圖9，說明根據本發明之另一實施例之在鈍化處理期間形成對準特徵的製程800，諸如圖3A至圖3B及圖4A至圖4C中所描繪。起初，可將晶圓貫通孔圖案化及蝕刻至底部晶片中(步驟802)，且晶片可經歷諸如背研磨處理之進一步處理以曝露晶圓貫通孔(步驟804)。接著，底部晶片及頂部晶片兩者皆可經歷鈍化處理(步驟806)。在底部晶片之背面鈍化期間或之後，可將對準突起圖案化及蝕刻至底部晶片上(步驟808)。類似地，在頂部晶片之正面鈍化期間或之後，可將對準凹座圖案化及蝕刻至頂部晶片上(步驟810)。在鈍化處理期間各別對準特徵之形成之後，頂部及底部晶片可使用對準突起與對準凹座之嚙合以精確地對準晶片來堆疊以形成晶片堆疊(步驟812)。可接著移動晶片堆疊以進行進一步處理，其中經嚙合之對準特徵進一步穩定堆疊(步驟814)。
雖然本發明可容易存在各種修改及替代形式，但是藉由實例在圖式中已展示特定實施例且本文中已詳細描述該等特定實施例。然而，應理解，本發明並不意欲限於所揭示之特定形式。相反，本發明將覆蓋屬於以下附隨申請專利範圍所界定之本發明之精神及範疇內的所有修改、均等物及替代形式。
10．．．電子器件/系統
12．．．處理器
14．．．輸入器件
16．．．音訊或視訊顯示器
18．．．電源
20．．．射頻(RF)子系統/基頻處理器
22．．．通信埠
24．．．周邊器件
26．．．記憶體
28．．．影像感測器/成像器
100．．．第一晶片/第二晶片/底部晶片
101．．．表面/背表面
102．．．晶圓貫通孔
103．．．結合襯墊
104．．．對準凹座/對準特徵
105．．．經填充之孔
106．．．載體
108．．．黏著劑/層
112．．．第一晶片/第二晶片/頂部晶片
114．．．結合襯墊
116．．．對準突起/對準特徵
118．．．鈍化層
120．．．鈍化層
200．．．第一晶片/第二晶片/底部晶片
202．．．晶圓貫通孔
204．．．矽載體
206．．．黏著層
208．．．對準凹座/對準特徵
210．．．鈍化層
212．．．晶片堆疊
214．．．第一晶片/第二晶片/頂部晶片
215．．．結合襯墊
216．．．對準突起/對準特徵
300．．．對準突起/對準特徵
302．．．第一晶片/第二晶片/底部晶片
304．．．晶圓貫通孔
306．．．矽載體
308．．．黏著層
310．．．鈍化層
312．．．第一晶片/第二晶片/頂部晶片
314．．．結合襯墊
316．．．對準凹座/對準特徵
318．．．鈍化層
320．．．晶片堆疊
400．．．第一晶片/第二晶片/底部晶片
402．．．第一晶片/第二晶片/頂部晶片
404．．．晶圓貫通孔
406．．．矽載體
408．．．黏著層
410．．．對準突起/對準特徵
412．．．鈍化層
414．．．結合襯墊
416．．．對準凹座/對準特徵
418．．．鈍化層
500．．．晶片堆疊
502．．．第一晶片/第二晶片/頂部晶片
504．．．第一晶片/第二晶片/底部晶片
506．．．矽載體
508．．．黏著層
510．．．對準突起/對準特徵
511．．．晶圓貫通孔
512．．．對準突起/對準特徵
513．．．結合襯墊
514．．．鈍化層
516．．．鈍化層
圖1說明根據本發明之實施例之基於處理器之器件的方塊圖；
圖2A至圖2D說明根據本發明之實施例之對準凹座及突起的形成；
圖3A至圖3B說明根據本發明之另一實施例之對準凹座及突起的形成；
圖4A至圖4C說明根據本發明之另一實施例之對準凹座及突起的形成；
圖5A至圖5B說明根據本發明之另一實施例之對準凹座及突起的形成；
圖6說明根據本發明之另一實施例之對準突起的形成；
圖7描繪根據本發明之實施例之形成對準特徵的製程；
圖8描繪根據本發明之另一實施例之在鈍化處理期間形成對準特徵的製程；及
圖9描繪根據本發明之另一實施例之在鈍化處理期間形成對準特徵的製程。
(無元件符號說明)

Claims (17)

  1. 一種形成一晶片堆疊之方法，其包含：在一第一晶片中形成複數個晶圓貫通孔；及在該第一晶片之一第一表面上形成一或多個對準特徵，其中該一或多個對準特徵包含至少一自該第一晶片延伸之突起；及在一第二晶片處建立一或多個第二對準特徵，其中該一或多個第二對準特徵包含自該第二晶片延伸之複數個突起，其中該第二對準特徵係經形成為用以嚙合該第一晶片之該一或多個對準特徵。
  2. 如請求項1之方法，其包含在該第一晶片上堆疊該第二晶片。
  3. 如請求項1之方法，其中形成該一或多個對準特徵包含藉由光微影、立體微影、濕式蝕刻、乾式蝕刻、鈍化或其組合形成該一或多個對準特徵。
  4. 如請求項1之方法，其包含拾取該第一晶片及將該第一晶片置於該第二晶片上使得該第一晶片之該等對準特徵嚙合該第二晶片的該等對準特徵。
  5. 如請求項1之方法，其包含將該晶片堆疊置於一固化爐中。
  6. 一種製造一晶片堆疊之方法，其包含：在一第一晶片上形成複數個晶圓貫通孔；在該第一晶片之一第一表面上形成複數個凹座；在一第二晶片之一第二表面上形成複數個突起，其中 該複數個突起係經形成為用以嚙合該複數個凹座以將在該第二晶片之該第二表面上之複數個結合襯墊與該第一晶片之該複數個晶圓貫通孔對準；及形成該第二晶片之複數個結合襯墊，其中該第二晶片之該複數個結合襯墊係與該複數個晶圓貫通孔之導電材料對準，其中當該複數個突起嚙合該複數個凹座時，一間隔係形成於各個該複數個結合襯墊與該複數個晶圓貫通孔之導電材料之間。
  7. 如請求項6之方法，其包含將該第一晶片堆疊至該第二晶片上使得該複數個凹座嚙合該複數個突起。
  8. 如請求項6之方法，其包含將該第二晶片堆疊至該第一晶片上使得該複數個突起嚙合該複數個凹座。
  9. 如請求項6之方法，其中在該第一晶片上形成該複數個凹座包含在一安置於該第一晶片上之層中形成複數個凹座。
  10. 如請求項9之方法，其中該層包含一鈍化層。
  11. 一種製造一半導體器件之方法，其包含：藉由一光微影處理、一鈍化處理或一以上之組合在一晶圓中形成複數個對準特徵，將該晶圓切割為複數個晶片，使得每一晶片包含該複數個對準特徵中之一或多者，其中該複數個對準特徵中之一或多者包含至少一自每一晶片延伸之突起以嚙合該複數個晶片之其他晶片之至少一突起；及在該複數個晶片之一第一晶片中形成複數個晶圓貫通 孔。
  12. 如請求項11之方法，其中形成複數個對準特徵包含在該晶圓之複數個晶片街(die street)處形成該複數個對準特徵。
  13. 一種晶片堆疊，其包含：一第一晶片，其具有第一複數個對準特徵及複數個晶圓貫通孔；及一第二晶片，其在該第二晶片之一表面上具有第二複數個對準特徵及複數個結合襯墊，其中該第二晶片之該第二複數個對準特徵係經形成為用以嚙合該第一晶片之該第一複數個對準特徵，使得該第二晶片的該複數個結合襯墊與該第一晶片之該複數個晶圓貫通孔對準。
  14. 如請求項13之晶片堆疊，其中該第二晶片之該複數個結合襯墊係經形成為用以嚙合該第一晶片的該複數個晶圓貫通孔。
  15. 如請求項13之晶片堆疊，其中該第二複數個對準特徵包含自該晶片之表面延伸的複數個突起。
  16. 一種系統，其包含：一電子器件，其包含：一處理器；及一或多個半導體器件，其中該一或多個半導體器件包含一晶片堆疊，其中該晶片堆疊包含：一第一晶片，其在該第一晶片之一第一表面上具有複數個對準突起，且該等對準突起係藉由光微影所形成；及 複數個晶圓貫通孔；及一第二晶片，其具有一第二複數個對準突起，該第二複數個對準突起經形成為用以嚙合該第一晶片之該一或多的對準突起。
  17. 一種晶片堆疊，其包含：一第一晶片，其具有第一複數個自該第一晶片之一第一表面延伸之突起及複數個晶圓貫通孔；及一第二晶片，其具有第二複數個自該第二晶片之一第二表面延伸之突起，其中該第二複數個突起係經組態以嚙合該第一複數個突起。
TW098109935A 2008-04-11 2009-03-26 用於小直徑、高密度晶圓貫通孔的晶片堆疊時建立對準／對心導引的方法 TWI499029B (zh)

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US20090255705A1 (en) 2009-10-15
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US9136259B2 (en) 2015-09-15
EP2281305A1 (en) 2011-02-09
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JP2011517114A (ja) 2011-05-26
TWI483379B (zh) 2015-05-01
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