JP6195995B2 - ブリッジ貫通導電ビア信号接続を有する埋込マルチデバイスブリッジ - Google Patents
ブリッジ貫通導電ビア信号接続を有する埋込マルチデバイスブリッジ Download PDFInfo
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- JP6195995B2 JP6195995B2 JP2016546503A JP2016546503A JP6195995B2 JP 6195995 B2 JP6195995 B2 JP 6195995B2 JP 2016546503 A JP2016546503 A JP 2016546503A JP 2016546503 A JP2016546503 A JP 2016546503A JP 6195995 B2 JP6195995 B2 JP 6195995B2
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
Claims (25)
- キャビティが中に画成されたマイクロエレクトロニクス基板であり、前記キャビティは、当該マイクロエレクトロニクス基板の第1表面から延在し、前記キャビティは、少なくとも1つの側壁と底面とを含み、当該マイクロエレクトロニクス基板は、当該マイクロエレクトロニクス基板の前記第1表面から延在する複数の導電経路と、前記キャビティの前記底面から延在する複数の導電経路とを含む、マイクロエレクトロニクス基板と、
前記マイクロエレクトロニクス基板の前記キャビティの中に配置されたブリッジであり、当該ブリッジは、当該ブリッジの第1表面の上又は中に形成された複数の信号ラインと、当該ブリッジの前記第1表面から、反対側の当該ブリッジの第2表面まで延在する複数のブリッジ貫通導電ビアとを有し、前記複数のブリッジ貫通導電ビアは、前記マイクロエレクトロニクス基板の前記キャビティの前記底面から延在する前記複数の導電経路に電気的に接続されている、ブリッジと、
複数のマイクロエレクトロニクスデバイスであり、当該複数のマイクロエレクトロニクスデバイスの各々が、前記マイクロエレクトロニクス基板の前記第1表面から延在する前記複数の導電経路のうちの少なくとも1つと、前記複数の信号ラインのうちの少なくとも1つと、前記複数のブリッジ貫通導電ビアのうちの少なくとも1つとに電気的に接続されている、複数のマイクロエレクトロニクスデバイスと、
を有するマイクロエレクトロニクス構造。 - 前記ブリッジはシリコン含有コンポーネントを有する、請求項1に記載のマイクロエレクトロニクス構造。
- 前記ブリッジは受動構造を有する、請求項1又は2に記載のマイクロエレクトロニクス構造。
- 前記ブリッジは能動構造を有する、請求項1又は2に記載のマイクロエレクトロニクス構造。
- 前記ブリッジは、相互接続層をその第1表面上に有するシリコン基板を有し、前記相互接続層は、前記シリコン基板の前記第1表面上に形成された少なくとも1つの誘電体層を有し、該誘電体層の中又は上に複数のブリッジ第1表面ボンドパッドと前記複数の信号ラインとが形成されており、前記ブリッジは更に、前記ブリッジ貫通導電ビアと前記シリコン基板との間に配置された誘電体ライナーを有する、請求項1乃至4の何れかに記載のマイクロエレクトロニクス構造。
- 前記マイクロエレクトロニクス基板は、前記複数の導電経路が中に形成された複数の誘電体層を有する、請求項1乃至5の何れかに記載のマイクロエレクトロニクス構造。
- 前記導電経路は、前記複数の誘電体層のうちの少なくとも1つの上に形成された少なくとも1つの導電配線と、前記複数の誘電体層のうちの少なくとも1つを貫いて延在する少なくとも1つの導電ビアとを有する、請求項6に記載のマイクロエレクトロニクス構造。
- 前記複数のマイクロエレクトロニクスデバイスのうちの少なくとも1つは、複数のインターコネクトを介して、前記マイクロエレクトロニクス基板と前記ブリッジとに取り付けられている、請求項1乃至6の何れかに記載のマイクロエレクトロニクス構造。
- 前記複数のインターコネクトのうちの少なくとも1つは、1つのマイクロエレクトロニクスデバイスのアクティブ面上の複数のボンドパッドのうちの1つと前記マイクロエレクトロニクス基板の対応するボンドパッドとの間を延在しており、前記複数のインターコネクトのうちの他の1つは、該マイクロエレクトロニクスデバイスの前記複数のボンドパッドのうちの他の1つと前記ブリッジの前記第1表面上の複数のボンドパッドのうちの対応するボンドパッドとの間を延在している、請求項8に記載のマイクロエレクトロニクス構造。
- 対応するブリッジ貫通導電ビアと接触するように前記ブリッジの前記第2表面の中又は上に形成され、且つ、複数のブリッジ−基板間インターコネクトを介して、前記マイクロエレクトロニクス基板の前記キャビティの前記底面の中又は上に形成された対応する基板キャビティボンドパッドに取り付けられた、複数のボンドパッド、を更に含む請求項1乃至8の何れかに記載のマイクロエレクトロニクス構造。
- キャビティが中に画成されたマイクロエレクトロニクス基板を形成するステップであり、前記キャビティは、当該マイクロエレクトロニクス基板の第1表面から延在し、前記キャビティは、少なくとも1つの側壁と底面とを含み、当該マイクロエレクトロニクス基板は、当該マイクロエレクトロニクス基板の前記第1表面から延在する複数の導電経路と、前記キャビティの前記底面から延在する複数の導電経路とを含む、ステップと、
ブリッジを形成するステップであり、
当該ブリッジの第1表面の上又は中に複数の信号ラインを形成することと、
当該ブリッジの前記第1表面から、反対側の当該ブリッジの第2表面まで延在する複数のブリッジ貫通導電ビアを形成することと
を含むステップと、
前記ブリッジを前記マイクロエレクトロニクス基板の前記キャビティ内に配置し、且つ前記複数のブリッジ貫通導電ビアを、前記マイクロエレクトロニクス基板の前記キャビティの前記底面から延在する前記複数の導電経路に電気的に接続するステップと、
前記マイクロエレクトロニクス基板及び前記ブリッジに複数のマイクロエレクトロニクスデバイスを取り付けるステップであり、当該複数のマイクロエレクトロニクスデバイスの各々が、前記マイクロエレクトロニクス基板の前記第1表面から延在する前記複数の導電経路のうちの少なくとも1つと、前記複数の信号ラインのうちの少なくとも1つと、前記複数のブリッジ貫通導電ビアのうちの少なくとも1つとに電気的に接続される、ステップと、
を有する方法。 - 前記ブリッジを形成することは、少なくとも1つのシリコン含有コンポーネントから前記ブリッジを形成することを有する、請求項11に記載の方法。
- 前記ブリッジを形成することは、受動構造を形成することを有する、請求項11又は12に記載の方法。
- 前記ブリッジを形成することは、能動構造を形成することを有する、請求項11又は12に記載の方法。
- 前記ブリッジを形成することは、
相互接続層をその第1表面上に有するシリコン基板を形成し、前記相互接続層は、前記シリコン基板の前記第1表面上に形成された少なくとも1つの誘電体層を有することと、
該誘電体層の中又は上に複数のブリッジ第1表面ボンドパッドと前記複数の信号ラインとを形成することと、
前記ブリッジ貫通導電ビアと前記シリコン基板との間に誘電体ライナーを配設することと
を有する、請求項11乃至14の何れかに記載の方法。 - 前記マイクロエレクトロニクス基板を形成することは、前記複数の導電経路を中に有する複数の誘電体層を形成することを有する、請求項12乃至15の何れかに記載の方法。
- 前記導電経路を形成することは、前記複数の誘電体層のうちの少なくとも1つの上に少なくとも1つの導電配線を形成することと、前記複数の誘電体層のうちの少なくとも1つを貫く少なくとも1つの導電ビアを形成することとを有する、請求項16に記載の方法。
- 前記複数のマイクロエレクトロニクスデバイスを取り付けることは、複数のインターコネクトを介して前記複数のマイクロエレクトロニクスデバイスを前記マイクロエレクトロニクス基板と前記ブリッジとに取り付けることを有する、請求項11乃至17の何れかに記載の方法。
- 前記複数のインターコネクトを介して前記複数のマイクロエレクトロニクスデバイスを前記マイクロエレクトロニクス基板と前記ブリッジとに取り付けることは、前記複数のインターコネクトのうちの少なくとも1つを、1つのマイクロエレクトロニクスデバイスのアクティブ面上の複数のボンドパッドのうちの1つと前記マイクロエレクトロニクス基板の対応するボンドパッドとの間に延在させ、且つ、前記複数のインターコネクトのうちの他の1つを、該マイクロエレクトロニクスデバイスの前記複数のボンドパッドのうちの他の1つと前記ブリッジの前記第1表面上の複数のボンドパッドのうちの対応するボンドパッドとの間に延在させて、前記複数のマイクロエレクトロニクスデバイスを前記マイクロエレクトロニクス基板と前記ブリッジとに取り付けることを有する、請求項18に記載の方法。
- 対応するブリッジ貫通導電ビアと接触するように前記ブリッジの前記第2表面の中又は上に複数のボンドパッドを形成することと、該複数のボンドパッドを、複数のブリッジ−基板間インターコネクトを用いて、前記マイクロエレクトロニクス基板の前記キャビティの前記底面の中又は上に形成された対応する基板キャビティボンドパッドに取り付けることと、を更に含む請求項11乃至19の何れかに記載の方法。
- 前記複数のブリッジ貫通導電ビアのうちの少なくとも1つを介して少なくとも1つのマイクロエレクトロニクスデバイスに電力を送り届けるステップ、を更に有する請求項11乃至20の何れかに記載の方法。
- ボードと、
前記ボードに取り付けられたマイクロエレクトロニクス装置と、
前記マイクロエレクトロニクス装置内に配置されたマイクロエレクトロニクス構造であり、
キャビティが中に画成されたマイクロエレクトロニクス基板であり、前記キャビティは、当該マイクロエレクトロニクス基板の第1表面から延在し、前記キャビティは、少なくとも1つの側壁と底面とを含み、当該マイクロエレクトロニクス基板は、当該マイクロエレクトロニクス基板の前記第1表面から延在する複数の導電経路と、前記キャビティの前記底面から延在する複数の導電経路とを含む、マイクロエレクトロニクス基板と、
前記マイクロエレクトロニクス基板の前記キャビティの中に配置されたブリッジであり、当該ブリッジは、当該ブリッジの第1表面の上又は中に形成された複数の信号ラインと、当該ブリッジの前記第1表面から、反対側の当該ブリッジの第2表面まで延在する複数のブリッジ貫通導電ビアとを有し、前記複数のブリッジ貫通導電ビアは、前記マイクロエレクトロニクス基板の前記キャビティの前記底面から延在する前記複数の導電経路に電気的に接続されている、ブリッジと、
複数のマイクロエレクトロニクスデバイスであり、当該複数のマイクロエレクトロニクスデバイスの各々が、前記マイクロエレクトロニクス基板の前記第1表面から延在する前記複数の導電経路のうちの少なくとも1つと、前記複数の信号ラインのうちの少なくとも1つと、前記複数のブリッジ貫通導電ビアのうちの少なくとも1つとに電気的に接続されている、複数のマイクロエレクトロニクスデバイスと
を有するマイクロエレクトロニクス構造と、
を有するコンピューティング装置。 - 前記ブリッジは、相互接続層をその第1表面上に有するシリコン基板を有し、前記相互接続層は、前記シリコン基板の前記第1表面上に形成された少なくとも1つの誘電体層を有し、該誘電体層の中又は上に複数のブリッジ第1表面ボンドパッドと前記複数の信号ラインとが形成されており、前記ブリッジは更に、前記ブリッジ貫通導電ビアと前記シリコン基板との間に配置された誘電体ライナーを有する、請求項22に記載のコンピューティング装置。
- 前記複数のマイクロエレクトロニクスデバイスのうちの少なくとも1つは、複数のインターコネクトを介して、前記マイクロエレクトロニクス基板と前記ブリッジとに取り付けられており、前記複数のインターコネクトのうちの少なくとも1つは、1つのマイクロエレクトロニクスデバイスのアクティブ面上の複数のボンドパッドのうちの1つと前記マイクロエレクトロニクス基板の対応するボンドパッドとの間を延在しており、前記複数のインターコネクトのうちの他の1つは、該マイクロエレクトロニクスデバイスの前記複数のボンドパッドのうちの他の1つと前記ブリッジの前記第1表面上の複数のボンドパッドのうちの対応するボンドパッドとの間を延在している、請求項22又は23に記載のコンピューティング装置。
- 対応するブリッジ貫通導電ビアと接触するように前記ブリッジの前記第2表面の中又は上に形成され、且つ、複数のブリッジ−基板間インターコネクトを介して、前記マイクロエレクトロニクス基板の前記キャビティの前記底面の中又は上に形成された対応する基板キャビティボンドパッドに取り付けられた、複数のボンドパッド、を更に含む請求項22乃至24の何れかに記載のコンピューティング装置。
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PCT/US2014/018482 WO2015130264A1 (en) | 2014-02-26 | 2014-02-26 | Embedded multi-device bridge with through-bridge conductive via signal connection |
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US (3) | US9754890B2 (ja) |
EP (1) | EP3111475B1 (ja) |
JP (1) | JP6195995B2 (ja) |
KR (1) | KR101815489B1 (ja) |
CN (1) | CN106165092B (ja) |
SG (1) | SG11201606039TA (ja) |
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Families Citing this family (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106165092B (zh) * | 2014-02-26 | 2020-02-18 | 英特尔公司 | 具有穿桥导电过孔信号连接的嵌入式多器件桥 |
US9368450B1 (en) * | 2015-08-21 | 2016-06-14 | Qualcomm Incorporated | Integrated device package comprising bridge in litho-etchable layer |
US10325840B2 (en) * | 2015-09-25 | 2019-06-18 | Intel Corporation | Metal on both sides with power distributed through the silicon |
US9601423B1 (en) | 2015-12-18 | 2017-03-21 | International Business Machines Corporation | Under die surface mounted electrical elements |
DE112015007213B4 (de) * | 2015-12-22 | 2021-08-19 | Intel Corporation | Halbleiter-package mit durchgangsbrücken-die-verbindungen und verfahren zum herstellen eines halbleiter-package |
DE112015007283B3 (de) | 2015-12-22 | 2022-03-31 | Intel Corporation | Halbleiter-package mit durchgangsbrücken-die-verbindungen |
KR101966328B1 (ko) * | 2016-03-29 | 2019-04-05 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR102473408B1 (ko) * | 2016-03-29 | 2022-12-02 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR102632563B1 (ko) * | 2016-08-05 | 2024-02-02 | 삼성전자주식회사 | 반도체 패키지 |
KR102624199B1 (ko) * | 2016-11-17 | 2024-01-15 | 에스케이하이닉스 주식회사 | 관통 실리콘 비아 기술을 적용한 반도체 패키지 |
KR102666151B1 (ko) * | 2016-12-16 | 2024-05-17 | 삼성전자주식회사 | 반도체 패키지 |
US10109616B2 (en) * | 2016-12-22 | 2018-10-23 | Intel Corporation | High bandwidth, low profile multi-die package |
US20220238440A1 (en) * | 2016-12-29 | 2022-07-28 | Intel Corporation | Bare-die smart bridge connected with copper pillars for system-in-package apparatus |
US20180240778A1 (en) * | 2017-02-22 | 2018-08-23 | Intel Corporation | Embedded multi-die interconnect bridge with improved power delivery |
WO2018174869A1 (en) * | 2017-03-22 | 2018-09-27 | Intel Corporation | Multiple die package using an embedded bridge connecting dies |
US10622311B2 (en) | 2017-08-10 | 2020-04-14 | International Business Machines Corporation | High-density interconnecting adhesive tape |
DE112017008031T5 (de) * | 2017-09-13 | 2020-07-02 | Intel Corporation | Aktive silizium-brücke |
CN116666332A (zh) * | 2017-09-28 | 2023-08-29 | 英特尔公司 | 利用沟槽结构的嵌入式桥管芯的电力输送 |
US11393745B2 (en) | 2017-09-29 | 2022-07-19 | Intel Corporation | Semiconductor packages with embedded interconnects |
US11327259B2 (en) * | 2017-12-07 | 2022-05-10 | Intel Corporation | Integrated circuit package with electro-optical interconnect circuitry |
WO2019132971A1 (en) * | 2017-12-29 | 2019-07-04 | Intel Corporation | Microelectronic assemblies |
EP3732712A4 (en) | 2017-12-29 | 2021-09-01 | Intel Corporation | MICROELECTRONIC ARRANGEMENTS WITH COMMUNICATION NETWORKS |
TWI670824B (zh) | 2018-03-09 | 2019-09-01 | 欣興電子股份有限公司 | 封裝結構 |
CN110265384B (zh) * | 2018-03-12 | 2021-07-16 | 欣兴电子股份有限公司 | 封装结构 |
US10580738B2 (en) * | 2018-03-20 | 2020-03-03 | International Business Machines Corporation | Direct bonded heterogeneous integration packaging structures |
KR102066721B1 (ko) * | 2018-03-23 | 2020-01-16 | 주식회사 웨이브피아 | 큐에프엔 알에프 칩 패키지 |
US20190312019A1 (en) * | 2018-04-10 | 2019-10-10 | Intel Corporation | Techniques for die tiling |
US10700051B2 (en) * | 2018-06-04 | 2020-06-30 | Intel Corporation | Multi-chip packaging |
US11251171B2 (en) * | 2018-06-13 | 2022-02-15 | Intel Corporation | Removable interposer |
US10535608B1 (en) | 2018-07-24 | 2020-01-14 | International Business Machines Corporation | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate |
TWI785106B (zh) * | 2018-08-28 | 2022-12-01 | 晶元光電股份有限公司 | 半導體裝置 |
KR102163059B1 (ko) | 2018-09-07 | 2020-10-08 | 삼성전기주식회사 | 연결구조체 내장기판 |
US11114308B2 (en) | 2018-09-25 | 2021-09-07 | International Business Machines Corporation | Controlling of height of high-density interconnection structure on substrate |
US20200098725A1 (en) * | 2018-09-26 | 2020-03-26 | Intel Corporation | Semiconductor package or semiconductor package structure with dual-sided interposer and memory |
KR20200074718A (ko) * | 2018-12-17 | 2020-06-25 | 삼성전기주식회사 | 인쇄회로기판 |
US11488906B2 (en) * | 2019-01-24 | 2022-11-01 | Samsung Electro-Mechanics Co., Ltd. | Bridge embedded interposer, and package substrate and semiconductor package comprising the same |
WO2020154939A1 (en) | 2019-01-30 | 2020-08-06 | Yangtze Memory Technologies Co., Ltd. | Hybrid bonding using dummy bonding contacts |
KR102618755B1 (ko) | 2019-01-30 | 2023-12-27 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 더미 접합 콘택트 및 더미 인터커넥트를 사용한 하이브리드 접합 |
KR102620867B1 (ko) * | 2019-03-15 | 2024-01-04 | 에스케이하이닉스 주식회사 | 브리지 다이를 포함한 반도체 패키지 |
US11043986B2 (en) * | 2019-04-15 | 2021-06-22 | Intel Corporation | Reduction of cross-capacitance and crosstalk between three-dimensionally packed interconnect wires |
US11133256B2 (en) * | 2019-06-20 | 2021-09-28 | Intel Corporation | Embedded bridge substrate having an integral device |
US11133258B2 (en) * | 2019-07-17 | 2021-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with bridge die for interconnection and method forming same |
KR20210019308A (ko) | 2019-08-12 | 2021-02-22 | 삼성전자주식회사 | 반도체 패키지 |
US11164817B2 (en) | 2019-11-01 | 2021-11-02 | International Business Machines Corporation | Multi-chip package structures with discrete redistribution layers |
US11094637B2 (en) | 2019-11-06 | 2021-08-17 | International Business Machines Corporation | Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers |
US11430764B2 (en) * | 2019-12-20 | 2022-08-30 | Intel Corporation | Overhang bridge interconnect |
MY201016A (en) * | 2019-12-20 | 2024-01-30 | Intel Corp | Integrated Bridge for Die-to-Die Interconnects |
US11342244B2 (en) | 2020-01-21 | 2022-05-24 | Sandisk Technologies Llc | Bonded assembly of semiconductor dies containing pad level across-die metal wiring and method of forming the same |
US20210272905A1 (en) * | 2020-02-28 | 2021-09-02 | Intel Corporation | Microelectronic package with substrate cavity for bridge-attach |
US11887962B2 (en) * | 2020-06-16 | 2024-01-30 | Intel Corporation | Microelectronic structures including bridges |
US11923307B2 (en) | 2020-06-16 | 2024-03-05 | Intel Corporation | Microelectronic structures including bridges |
US11804441B2 (en) | 2020-06-16 | 2023-10-31 | Intel Corporation | Microelectronic structures including bridges |
US11373972B2 (en) | 2020-06-16 | 2022-06-28 | Intel Corporation | Microelectronic structures including bridges |
US11791274B2 (en) | 2020-06-16 | 2023-10-17 | Intel Corporation | Multichip semiconductor package including a bridge die disposed in a cavity having non-planar interconnects |
US20210391264A1 (en) * | 2020-06-16 | 2021-12-16 | Intel Corporation | Microelectronic structures including bridges |
KR20220001643A (ko) * | 2020-06-30 | 2022-01-06 | 삼성전자주식회사 | 반도체 패키지 |
KR20220015573A (ko) * | 2020-07-31 | 2022-02-08 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
KR20220019186A (ko) | 2020-08-07 | 2022-02-16 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
US11515234B2 (en) * | 2020-12-03 | 2022-11-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package including promoters and method of manufacturing the same |
US20220181295A1 (en) * | 2020-12-04 | 2022-06-09 | Yibu Semiconductor Co., Ltd. | Method for Forming Chip Packages and a Chip Package |
US20220230991A1 (en) * | 2021-01-21 | 2022-07-21 | Monolithic Power Systems, Inc. | Multi-die package structure and multi-die co-packing method |
US11791270B2 (en) * | 2021-05-10 | 2023-10-17 | International Business Machines Corporation | Direct bonded heterogeneous integration silicon bridge |
US11848273B2 (en) | 2021-11-17 | 2023-12-19 | International Business Machines Corporation | Bridge chip with through via |
US20230402380A1 (en) * | 2022-06-08 | 2023-12-14 | Qualcomm Incorporated | Package comprising a substrate with a bridge configured for a back side power distribution network |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19990069447A (ko) * | 1998-02-09 | 1999-09-06 | 구본준 | 반도체 패키지와 그 제조방법 |
US6369444B1 (en) * | 1998-05-19 | 2002-04-09 | Agere Systems Guardian Corp. | Packaging silicon on silicon multichip modules |
JP3788268B2 (ja) * | 2001-05-14 | 2006-06-21 | ソニー株式会社 | 半導体装置の製造方法 |
KR20060074091A (ko) * | 2004-12-27 | 2006-07-03 | 주식회사 하이닉스반도체 | 칩 스택 패키지 |
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
KR100721353B1 (ko) | 2005-07-08 | 2007-05-25 | 삼성전자주식회사 | 칩 삽입형 매개기판의 구조와 제조 방법, 이를 이용한 이종칩의 웨이퍼 레벨 적층 구조 및 패키지 구조 |
US8064224B2 (en) * | 2008-03-31 | 2011-11-22 | Intel Corporation | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same |
US8227904B2 (en) * | 2009-06-24 | 2012-07-24 | Intel Corporation | Multi-chip package and method of providing die-to-die interconnects in same |
US8288854B2 (en) | 2010-05-19 | 2012-10-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for making the same |
TWI418269B (zh) | 2010-12-14 | 2013-12-01 | Unimicron Technology Corp | 嵌埋穿孔中介層之封裝基板及其製法 |
US9449941B2 (en) * | 2011-07-07 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting function chips to a package to form package-on-package |
US8742576B2 (en) * | 2012-02-15 | 2014-06-03 | Oracle International Corporation | Maintaining alignment in a multi-chip module using a compressible structure |
JP2014011169A (ja) * | 2012-06-27 | 2014-01-20 | Ps4 Luxco S A R L | シリコンインターポーザ及びこれを備える半導体装置 |
US9026872B2 (en) * | 2012-08-16 | 2015-05-05 | Xilinx, Inc. | Flexible sized die for use in multi-die integrated circuit |
US8872349B2 (en) * | 2012-09-11 | 2014-10-28 | Intel Corporation | Bridge interconnect with air gap in package assembly |
CN106165092B (zh) * | 2014-02-26 | 2020-02-18 | 英特尔公司 | 具有穿桥导电过孔信号连接的嵌入式多器件桥 |
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US9754890B2 (en) | 2017-09-05 |
JP2017505539A (ja) | 2017-02-16 |
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