CN113169078B - 制造电子元件的方法、电子元件和制造半导体芯片的方法 - Google Patents

制造电子元件的方法、电子元件和制造半导体芯片的方法 Download PDF

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CN113169078B
CN113169078B CN201980067647.7A CN201980067647A CN113169078B CN 113169078 B CN113169078 B CN 113169078B CN 201980067647 A CN201980067647 A CN 201980067647A CN 113169078 B CN113169078 B CN 113169078B
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alignment
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CN113169078A (zh
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马赛厄斯·文特
西米恩·卡茨
帕斯卡·波尔藤
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Ams Osram International GmbH
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Osram Opto Semiconductors GmbH
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Abstract

一种用于制造电子元件(100)的方法包括：步骤A)，在该步骤中提供了半导体芯片(2)(例如像素化的光电子半导体芯片(2))，其具有底侧(20)、多个接触销(21)和至少一个校准销(25)，所述接触销和校准销从底侧(20)突出。接触销(21)设计用于电接触半导体芯片(2)。校准销(25)在远离底侧(20)的方向上变细并且比接触销(21)从底侧(20)突出得更远。在步骤B)中，提供了连接载体(I)，其具有上侧(10)，多个接触凹部(II)和至少一个校准凹部(15)被引入到所述上侧中。接触凹部(11)分别至少部分地用焊接材料(12)填充。在步骤C)中，将接触凹部(11)中的焊接材料(12)加热到焊接材料(12)至少部分熔化的接合温度。在步骤D)中，将半导体芯片(2)放置到连接载体(1)上，其中，将接触销(21)分别引入到接触凹部(11)中并且将校准销(25)引入到校准凹部(15)中。在此，接触销(21)浸入到熔化的焊接材料(12)中。能够将焊接材料(12)和接触销(21)的材料选择成使得在步骤D)中并且在接合温度下，焊接材料(12)和接触销(21)通过等温固化材料配合地彼此连接。用于制造半导体芯片(2)的方法包括以下步骤：A)提供具有半导体本体(26)和底侧(20)的基体，其中，将多个接触销(21)和至少一个校准销(25)布置在半导体本体(26)上，所述接触销和校准销分别从底侧(20)突出，其中，接触销(21)设计用于电接触半导体本体(26)，校准销(25)比接触销(21)从底侧(20)突出得更远，并且校准销(25)的直径在校准销(25)的整个高度之上基本上是恒定的；B)在校准销(25)旁边的区域中在半导体本体(26)上构成成形体(4)，其中，成形体(4)对校准销(25)侧向地成形；C)通过将蚀刻剂施加到成形体(4)和校准销(25)的背离半导体本体(26)的一侧上来执行蚀刻工艺，其中，蚀刻剂侵蚀成形体(4)和校准销(25)，蚀刻剂对成形体(4)的蚀刻速率高于其对校准销(25)的蚀刻速率，并且执行蚀刻工艺直至校准销(25)的形状改变成使得校准销(25)在远离底侧(20)的方向上变细。步骤C)中的蚀刻工艺能够执行直至将成形体(4)完全移除。接触销(22)和校准销(25)能够在步骤A)之前电镀地施加在半导体本体(26)上，其中，尤其是接触销(21)和校准销(25)的第一部段借助于第一电镀工艺来被共同制造，并且随后在第二电镀工艺中制造完成校准销。

Description

制造电子元件的方法、电子元件和制造半导体芯片的方法
提出一种用于制造电子元件的方法。另外，提出一种电子元件、一种半导体芯片和一种用于制造半导体芯片的方法。
要实现的目的在于：提出一种用于制造电子元件的方法，借助所述方法将半导体芯片校准地放置到连接载体上。其他要实现的目的在于：提出一种用于这种方法的半导体芯片和一种能够借助所述方法制造的电子元件。一个另外要实现的目的在于：提出一种用于制造这种半导体芯片的方法。
所述目的还通过独立权利要求以及权利要求11的主题和方法实现。有利的设计方案和进一步改进是其余从属权利要求的主题。
首先，提出一种用于制造电子元件的方法。电子元件优选是光电子元件。
根据至少一个实施方式，用于制造电子元件的方法包括步骤A)，在该步骤中提供半导体芯片。半导体芯片包括底侧、多个接触销和至少一个校准销。接触销和校准销从底侧突出。接触销设计用于电接触半导体芯片。校准销在远离底侧的方向上变细并且比接触销从底侧突出得更远。
半导体芯片包括例如至少四个或至少16个或至少36个或至少64个或至少100个接触销。接触销尤其用于外部电接触半导体芯片。接触销优选地由金属形成。例如，接触销包括或由以下材料中的一种或多种形成：铂、镍或金。接触销优选一件式或一体地形成。
半导体芯片包括至少一个，优选更多个(例如至少两个或至少四个)校准销。关于校准销的下面做出的说明能够相应地适用于所有其他校准销。
校准销优选不用于接触半导体芯片并且例如与半导体芯片的半导体材料电绝缘。校准销能够由金属形成。例如，校准销包括或由以下材料中的一种或多种形成：铂、镍或金。接触销优选一件式或一体地形成。
接触销和/或校准销从底侧突出例如至少1μm或至少2μm或至少5μm。替选地或附加地，接触销和/或校准销能够从底侧突出最大30μm或最大15μm或最大10μm。接触销和/或校准销的平行于底侧测量的直径例如为至少1μm或至少2μm或至少5μm。替选地或附加地，接触销和/或校准销的直径能够最大为30μm或最大为15μm或最大为10μm。
接触销例如圆柱形地或长方体形地形成。在从底侧突出的区域中，接触销也能够棱锥形或截棱锥形或圆锥形或截锥体形地形成。优选地，接触销的垂直于底侧的扩展大于其平行于底侧的扩展。
校准销在远离底侧的方向上变细。即，校准销的直径至少在从底侧突出的区域中在远离底侧的方向上减小。例如，校准销在制造公差的范围内单调变细。校准销的最窄部位处的直径例如最高为最宽部位处的直径的一半、最高为最宽部位处的直径的1/3、最高为最宽部位处的直径的1/10。例如，校准销在从底侧突出的区域中圆锥形或截锥体形或棱锥形或截棱锥体形地成形。
校准销比接触销从底侧突出得更远，尤其是从每个接触销突出得更远。也就是说，校准销的从底侧开始测量的并且在垂直地远离底侧的方向上测量的高度更大，例如是接触销的高度的至少1.5倍，或者至少两倍，或者至少三倍。校准销的最宽部位处的直径能够是接触销的最大直径的至少1.5倍或至少两倍或至少三倍。
半导体芯片优选是用于发射或吸收电磁辐射的光电子半导体芯片。半导体芯片尤其包括具有用于产生或吸收电磁辐射的有源层的半导体本体。半导体本体例如基于III-V族化合物半导体材料。半导体材料例如是氮化物化合物半导体材料(如AlnIn1-n-mGamN)或也是磷化物化合物半导体材料(如AlnIn1-n-mGamP)或者也为砷化物化合物半导体材料(如AlnIn1-n-mGamAs或者AlnIn1-n-mGamAsP)，其中，分别有0≤n≤1，0≤m≤1并且n+m≤1。在此，半导体本体能够具有掺杂物以及附加的组成部分。然而，为了简单起见，仅说明半导体本体的晶格的主要组成部分，即Al、As、Ga、In、N或P，即使这些主要组成部分能够部分地由少量的其他物质替代和/或补充时也如此。优选地，半导体本体基于AlInGaN。
半导体本体的有源层尤其包含至少一个pn结和/或至少一个量子阱结构，并且例如在正常运行中能够产生或吸收蓝色、绿色或红色光谱范围内或UV范围内的电磁辐射。优选地，半导体芯片包括一个(尤其是恰好一个)连贯的(尤其是简单连贯的)有源层。替选地，有源层也能够被分段。
将半导体芯片在这里和下文中理解为可单独操作的并且可电接触的元件。半导体芯片尤其通过从晶片复合体中分割来形成。例如，这种半导体芯片的侧面于是具有来自晶片复合体的分割工艺的痕迹。半导体芯片优选地包括在晶片复合体中生长的半导体本体的恰好一个原始连贯的区域。半导体芯片的半导体本体优选地连贯地形成。半导体芯片的平行于有源层的主延伸方向测量的横向扩展例如比有源层或半导体本体的横向扩展大最多1％或最多5％或最多10％。
在步骤A)中，半导体芯片例如还包括生长衬底，整个半导体本体生长在所述生长衬底上。
半导体芯片的与半导体芯片的底侧相对置的上侧例如形成为辐射侧。例如，从半导体芯片耦合输出的辐射的或耦合输入到半导体芯片中的辐射的至少50％经由辐射侧耦合输出或耦合输入。
根据至少一个实施方式，该方法包括步骤B)，在该步骤中，提供具有上侧的连接载体。将多个接触凹部和至少一个校准凹部引入到该上侧中。
连接载体尤其是用于电接触半导体芯片的电子的连接载体。例如，连接载体是具有集成电子电路的半导体载体(如硅载体)。连接载体也能够是电路板或基于陶瓷的载体。
优选地，对于每个校准销，连接载体都包括校准凹部。所有在下文中对于校准凹部做出的说明相应地能够适用于所有其他的校准凹部。
将接触凹部和校准凹部引入到连接载体的上侧中。即，凹部分别从上侧延伸进入到连接载体中。例如，接触凹部和/或校准凹部分别具有垂直于上侧测量的至少2μm或至少5μm的深度。替选地或附加地，接触凹部和/或校准凹部能够分别具有最多30μm或最多15μm或最多10μm的深度。优选地，不同的凹部彼此分离。即，凹部不通过引入到上侧中的沟槽彼此连接。
根据至少一个实施方式，接触凹部分别至少部分地用焊接材料填充。例如，焊接材料填充至少50％或至少60％或至少70％的接触凹部。替选地或附加地，焊接材料能够分别填充最大90％或最大80％的接触凹部。优选地，校准凹部中没有焊接材料。
焊接材料优选是金属(尤其是金属合金)，尤其优选是共晶体。例如，焊接材料包括镓、铟、铋、银、铜、金、锌、铅或锡，或者由这些材料之一构成。焊接材料例如包括或由以下材料构成：Galinstan(GalnSn)、Galn、Biln、SnAgCu、SnCu、AuSn、InSn、AgIn、SnZn、AgSn、AuBi、AgBi。
优选地，不同接触凹部的焊接材料不连续。因此，一个接触凹部中的焊接材料与其他的接触凹部中的焊接材料分离。特别地，不同接触凹部的焊接材料彼此电绝缘。
优选地，将接触凹部的直径选择成使得在每一个接触凹部中配合有一个接触销。即，接触凹部的直径大于接触销的直径。在此，凹部的直径是平行于上侧或平行于连接载体的主延伸平面测量的。例如，接触凹部的直径比接触销的直径大至少10％或至少20％或至少50％。替选地或附加地，接触凹部的直径能够比接触销的直径大最多100％或最多75％或最多50％。接触凹部例如是连接载体中的圆柱形或长方体形的凹部。
优选地，校准凹部的直径被选择成使得校准销的背离底侧的至少一个部段配合到校准凹部中。优选地，校准销的从底侧突出的整个区域配合到校准凹部中。校准凹部例如是连接载体中的圆柱形或长方体形的或圆锥形的或截锥体形的或棱锥形的或截棱锥体的凹部。
根据至少一个实施方式，该方法包括步骤C)，在该步骤中，将接触凹部中的的焊接材料加热到焊接材料至少部分熔化的接合温度。因此，接合温度高于焊接材料的固相线温度，优选地高于液相线温度。例如，接合温度在100℃至400℃之间，其中包括边界值。
根据至少一个实施方式，该方法包括步骤D)，在该步骤中，将半导体芯片放置到连接载体上，其中，将接触销分别引入到接触凹部中并且将校准销引入到校准凹部中。在此，接触销浸入到熔化的焊接材料中。优选地，将每个接触销一对一地分配给接触凹部。
因此，接触凹部和校准凹部的在连接载体的上侧中的布置尤其与接触销和校准销的在半导体芯片的底侧上的布置相匹配，使得在将半导体芯片放置到连接载体上时能够将每个接触销分配给一个接触凹部并且将校准销分配给校准凹部。换言之，接触凹部和校准凹部布置成使得在放置半导体芯片时每个接触销都能够被引入到专门分配的接触凹部中并且校准销能够被引入到校准凹部中。在多个校准销和多个校准凹部的情况下，优选地，每个校准销都能够被引入到专门分配的校准凹部中。
例如，接触销以均匀的间距布置在半导体芯片的底侧上，例如布置在矩形网格或六边形网格的网格点上。该一个或更多个校准销例如布置在底侧的边缘处。于是，相应地，接触凹部以相同的间距并且以相同的均匀的样式布置在连接载体中。特别地，连接载体至少包括与半导体芯片所包括接触销或校准销一样多的接触凹部或校准凹部。
在放置时，首先从底侧突出得更远的校准销进入到校准凹部中。在此，由于校准销的变细的形状而进行半导体芯片相对于连接载体的自动对准。然后，接触销进入到相关联的接触凹部中。优选地，每个接触销浸入到熔化的焊接材料中，并在此与焊接材料直接机械接触。
在将接触销浸入到焊接材料中时，接触销分别在朝向连接载体的区域中被焊接材料浸湿。接触销的背离连接载体的区域能够保持没有焊接材料。
在施加半导体芯片之后，能够冷却焊接材料，使得其固化。替选地还可行的是：通过与接触销反应使焊料材料发生等温固化。
优选地，步骤A)至D)以所给出的顺序依次地执行。
在至少一个实施方式中，提出一种用于制造电子元件的方法，其包括：步骤A)，在该步骤中提供具有底侧、多个接触销和至少一个校准销的半导体芯片。接触销和校准销从底侧突出。接触销设计用于电接触半导体芯片。校准销在远离底侧的方向上变细。校准销比接触销从底侧突出得更远。在步骤B)中，提供具有上侧的连接载体，将多个接触凹部和至少一个校准凹部引入到所述上侧中。接触凹部分别至少部分地用焊接材料填充。在步骤C)中，将接触凹部中的焊接材料加热到焊接材料至少部分熔化的接合温度。在步骤D)中，将半导体芯片放置到连接载体上，其中，将接触销分别引入到接触凹部中并且将校准销引入到校准凹部中。在此，接触销浸入到熔化的焊接材料中。
本发明尤其基于以下知识：在高度像素化的光电子半导体芯片的情况下(例如像素尺寸为约10μm且总尺寸为约20mm×20mm)，必须对所述半导体芯片设置最高10μm的校准公差。在此，还应当考虑边界条件，例如半导体芯片的弯曲以及电触点的可靠性和机械稳定性。
借助当前的方法，即使在接触销的间距非常小的情况下，也能够可靠地施加半导体芯片。校准销和校准凹部已经确保在放置期间以及在将接触销引入到所属的接触凹部中之前半导体芯片的正确对准。能够省去昂贵的平坦化，如其在混合直接键合中是这种情况。在校准公差之内能够实现稳定的固定，所述校准公差通过接触凹部的直径与接触销的直径之间的差的一半给定。在非常薄的接触销中，即具有小直径的接触销中能够实现尤其高的校准公差。经由接触销的高度能够使整个器件的高度发生变化。
根据至少一个实施方式，校准凹部的直径大于校准销的直径。特别地，校准凹部的直径大于校准销的最窄的部位处的直径，优选地大于其最宽部位处的直径。例如，校准凹部的直径比校准销的最宽部位处的直径大至少10％或至少20％或至少50％。特别优选地，校准凹部的直径最大为校准销的最宽部位处的直径的两倍或最大1.75倍或最大1.5倍。
根据至少一个实施方式，校准凹部的深度大于接触凹部的深度，尤其是大于每个接触凹部的深度。例如，校准凹部的深度是接触凹部的深度的至少1.5倍，或者至少两倍，或者至少三倍。在此，深度是垂直于连接载体的上侧测量的。
根据至少一个实施方式，焊接材料和接触销的材料选择为使得在步骤D)中并且在接合温度下，焊接材料和接触销通过等温固化材料配合地彼此连接。在步骤D)中，因此，在焊接材料与接触销的材料之间发生反应，通过所述反应使焊接材料等温固化。在这种情况下，将接合温度选择为使得其低于在等温固化中形成的化合物的熔化温度。
例如，焊料材料能够是AuSn。接触销能够由铂制成。于是，焊接材料的熔化温度约为280℃。AuSn与铂反应，由此造成等温固化。在此形成的化合物的熔化温度超过400℃。在基于锡或铟的焊接材料的情况下，基于Ni或Au的接触销也适用于实现等温固化。
在将半导体芯片施加在连接载体上时，能够有利地在等温固化中形成的化合物的熔化温度与焊接材料的熔化温度之间的区域中自由地选择接合温度，使得能够调节半导体芯片的半导体层序列中的应力或去应力。尤其当半导体芯片的半导体层序列布置在生长衬底上时，所述半导体层序列会受到强烈的应力。在放置到连接载体上时并且通过调节相应的接合温度，能够消除所述应力。由此例如能够剥离生长衬底。
根据至少一个实施方式，利用该方法将半导体芯片电连接在连接载体上。换言之，接触销与连接载体的相应的接触元件导电连接。导电连接在此通过焊接材料来提供。在步骤D)之后，然后例如能够经由连接载体向半导体芯片通电并使之正常运行。在正常运行中，校准销例如不用于在半导体芯片与连接载体之间电接触。例如，在正常运行中，没有电流流过校准销。
根据至少一个实施方式，半导体芯片是像素化的光电子半导体芯片。即，半导体芯片包括多个区域(英语Pixel)，所述区域能够优选地被单独地并且彼此独立地操控，进而能够单独地并且彼此独立地发射或吸收电磁辐射。
半导体本体的有源层在此能够连贯地形成并且在所有像素之上延伸。但是，替选地，有源层也能够被划分成各个区段，其中，将每个区段一对一地分配给像素。
每个像素的平行于半导体芯片的底侧测量的横向扩展例如能够最大为250μm或最大为150μm或最大为50μm或最大为10μm。替选地或附加地，像素能够分别具有至少2μm或至少5μm的横向扩展。半导体芯片包括例如至少四个或至少16个或至少36个或至少64个或至少100个这种像素。
根据至少一个实施方式，将像素或区域分配给每个接触销，尤其是将其一对一地分配给每个接触销。但是，也能够将多个像素分配给一个接触销。因此，能够通过经由接触销输送载流子来操作所述被分配的一个或多个像素，优选地仅对所述被分配的一个或多个像素进行操作。
根据至少一个实施方式，连接载体包括多个电子开关。电子开关能够集成在连接载体中。开关例如是晶体管。连接载体尤其是具有集成电路的硅载体。
根据至少一个实施方式，将开关分配给每个接触凹部，尤其是将其一对一地分配给每个接触凹部。在施加半导体芯片之后，优选地将每个接触销与开关导电连接。像素化的半导体芯片的各个像素能够经由开关单独地并且彼此独立地被操控和操作。
根据至少一个实施方式，在步骤D)中，将接触销浸入到熔化的焊接材料中，使得每个接触凹部中置换出的焊接材料的体积为接触凹部中的焊接材料的总体积的至少10％或至少15％或至少20％或至少30％或至少50％或至少70％。替选地或附加地，置换出的焊接材料体积分别是焊接材料的总体积的最多90％或最多80％或最多50％或最多20％。特别地，焊接材料的量、接触凹部的形状和接触销的形状分别选择为使得大量熔化的焊接材料与接触销接触，这有助于等温固化。
根据至少一个实施方式，在接触凹部和校准凹部外部的区域中，连接载体的上侧比接触销更差地通过熔化的焊接材料浸湿。优选地，上侧在接触凹部和校准凹部之外的区域不用熔化的焊接材料浸湿。因此，在施加半导体芯片时减小了相邻的接触凹部的焊接材料彼此连接进而形成短路的风险。
根据至少一个实施方式，各相邻的两个接触销之间的距离为至少1μm或至少2μm或至少5μm。替选地或附加地，各相邻的两个接触销之间的距离能够最大为50μm或最大为20μm或最大为10μm。在此，该距离例如被定义为接触销的重心之间的距离。能够相应地选择接触凹部的重心或中点之间的距离。校准销距最接近的接触销的距离也能够位于上述范围内。
根据至少一个实施方式，在步骤D)之前剥离半导体芯片的生长衬底。半导体芯片因此例如在步骤A)中还包括生长衬底，例如蓝宝石衬底，在所述生长衬底上外延生长半导体层序列。然而，替选地，也能够考虑的是：仅在放置和固定在连接载体上之后才剥离半导体芯片的生长衬底。
接下来，提出一种半导体芯片。该半导体芯片例如能够用作上述方法中的半导体芯片。因此，与之前描述的方法有关的所有被公开的特征也针对该半导体芯片被公开，并且反之亦然。
根据至少一个实施方式，半导体芯片包括半导体本体、底侧、多个接触销和至少一个校准销。接触销和校准销分别从底侧突出。接触销被设置用于电接触半导体本体。校准销在远离底侧的方向上变细。校准销比接触销从底侧突出得更远。
半导体芯片能够是所谓的体积发射器，尤其是倒装芯片。在这种情况下，半导体芯片优选还包括例如由蓝宝石构成的生长衬底。然而，半导体芯片优选是表面发射器，尤其是所谓的薄膜芯片，在该芯片中生长衬底被剥离。
根据至少一个实施方式，校准销与半导体本体电绝缘。例如，在校准销与半导体本体之间形成电绝缘层。电绝缘层例如能够包括或由以下材料构成：氧化硅或氮化硅或氧化铝。
接下来，提出一种电子元件。该电子元件包括例如如上所述的半导体芯片。此外，能够利用上述方法来制造该电子元件。因此，与半导体芯片和上述方法有关的所有被公开的特征也针对该电子元件被公开，并且反之亦然。
根据至少一个实施方式，电子元件包括根据上述实施方式中的至少一个的半导体芯片。此外，电子元件包括具有上侧的连接载体，将多个接触凹部和至少一个校准凹部引入到所述上侧中。接触凹部分别至少部分地用焊接材料填充。不同接触凹部的焊接材料不连续。半导体芯片通过底侧朝前安装在连接载体的上侧上。为每个接触销分配接触凹部，并且为校准销分配校准凹部。接触销分别伸入到接触凹部中。校准销伸入到校准凹部中。接触销分别与接触凹部的焊接材料材料配合地连接。
但是，优选地，接触销不完全布置在接触凹部中，而是局部地布置在接触凹部之外。即，在远离连接载体的上侧并且朝向半导体芯片的底侧的方向上，接触销突出于连接载体的上侧，例如突出至少500nm或至少1μm。
例如，接触销的布置在凹部内的下部区域通过焊接材料浸湿。接触销的背离连接载体且例如位于凹部之外的上部区域优选没有焊接材料。
根据至少一个实施方式，半导体芯片经由接触销和经由焊接材料电连接至连接载体。
接下来，提出一种用于制造半导体芯片的方法。该方法尤其适合于制造如上所述的半导体芯片。因此，与上述半导体芯片有关的所有公开的特征也针对该方法被公开，并且反之亦然。
根据至少一个实施方式，用于制造半导体芯片的方法包括：步骤A)，在该步骤中，提供具有半导体本体和底侧的基体。将多个接触销和至少一个校准销布置在半导体本体上，所述接触销和校准销分别从底侧突出。接触销设计用于电接触半导体本体，例如与其导电连接。校准销比接触销从底侧突出得更远。在校准销的整个高度上，校准销的直径基本上是恒定的。在步骤B)中，在校准销旁边的区域中在半导体本体上形成成形体，其中，该成形体侧向地成形校准销。在步骤C)中，执行蚀刻工艺，其中，将蚀刻剂施加到成形体和校准销的背离半导体本体的一侧上。蚀刻剂侵蚀成形体和校准销，并且其对校准销的蚀刻速率高于其对成形体的蚀刻速率。执行蚀刻工艺直至校准销的形状改变成使得校准销在远离底侧的方向上变细。
校准销的直径在校准销的整个高度上基本上恒定尤其意味着：在制造公差的范围内，校准销在从底侧突出的区域中具有恒定的直径。在步骤A)中，校准销例如具有长方体或圆柱体的形状。校准销的高度是垂直于底侧的扩展。
成形体能够例如具有塑料(例如苯并环丁烯)或光刻胶或硅树脂或环氧树脂或者由所述材料构成。成形体优选地以这样的方式对校准销成形，使得成形体直接邻接于校准销并对其仿形。同样地，成形体能够对接触销侧向地成形。
尤其是湿化学蚀刻剂(例如KOH或由H2O2和H2SO4构成的混合物)适合作为步骤C)中的蚀刻剂。但是也能够考虑干化学蚀刻方法。
蚀刻剂对成形体的蚀刻速率例如是对校准销的蚀刻速率的至少1.5倍，或至少两倍，或至少三倍。例如，蚀刻剂对成形体的蚀刻速率附加地是对校准销的蚀刻速率的最多10倍或最多5倍。其结果是：相比于校准销，成形体被蚀刻剂更快地蚀刻掉。在被蚀刻掉的成形体的区域中，校准销然后从成形体中伸出。由此，蚀刻剂也侧向地侵蚀校准销。其结果是，校准销的形状形成为具有在远离底侧的方向上变小的直径的形状。
在步骤C)之后，例如能够将基体分割成多个半导体芯片。即，在步骤A)至C)期间，基体例如是晶片复合体。但是，替选地，也可行的是：具有接触销和在步骤C)中成形的校准销的基体已经形成了半导体芯片，而不是进一步分割所述半导体芯片。
根据至少一个实施方式，执行步骤C)中的蚀刻工艺直至成形体被完全移除。基体的底侧例如不受蚀刻剂侵蚀，使得蚀刻工艺自动在底侧停止。
根据至少一个实施方式，在步骤A)之前将接触销和校准销电镀地施加在半导体本体上。
根据至少一个实施方式，接触销和校准销的第一部段借助于第一电镀工艺被共同制造。然后，在第一电镀工艺之后，校准销的第一部段的和接触销的垂直于底侧测量的高度在制造公差范围内是相同的。
根据至少一个实施方式，在第一电镀工艺之后，校准销在第二电镀工艺中制成。在第二电镀工艺中，优选仅增加校准销的高度，而不增加接触销的高度。即，第二电镀工艺不应用于接触销。
下面，根据实施例参照附图更详细地阐述在此描述的用于制造电子元件的方法、在此描述的半导体芯片、在此描述的电子元件以及在此描述的用于制造半导体芯片的方法。在此，相同的附图标记说明各个附图中的相同的元件。然而在此，未示出符合比例的关系，更确切地说为了更好地理解能够夸大地示出各个元件。
附图示出：
图1A至图1C示出了用于制造电子元件的方法的一个实施例中的不同的位置以及示出了电子元件的一个实施例和半导体芯片的一个实施例，
图2A至图2K以及图3示出了用于制造半导体芯片的方法的一个实施例中的不同的位置和半导体芯片的一个实施例。
图1A示出了用于制造电子元件的方法的一个实施例中的第一位置。同时，图1A以横截面视图示出了半导体芯片2的一个实施例。
半导体芯片2包括半导体本体26和在半导体本体26上的电绝缘层27。电绝缘层27的背离半导体本体26的一侧形成半导体芯片2的底侧20。半导体本体26例如基于氮化物化合物半导体材料。半导体本体26例如包括用于产生或吸收电磁辐射的有源层。半导体芯片2尤其是光电子半导体芯片2。
半导体芯片2具有接触销21，所述接触销与半导体本体26导电连接。接触销21例如由镍制成。此外，半导体芯片2包括两个校准销25，所述两个校准销例如同样主要由镍形成。接触销21和校准销25从底侧20突出。在此，校准销25比接触销21从底侧突出得更远。
校准销25并且当前还有接触销21分别在远离底侧20的方向上变细。校准销25例如分别具有截锥体或截棱锥体的形状。在校准销25的背离底侧20的一侧，所述校准销分别包括例如由铂制成的覆盖元件250。
在图1A中附加地示出了连接载体1。连接载体1例如是基于硅的具有集成电路的载体。连接载体1具有上侧10，针对每个接触销21将接触凹部11引入到所述上侧中。此外，针对每个校准销25将校准凹部15引入到上侧10中。在此，校准凹部15比接触凹部11更深。在此，校准凹部15之一圆柱形或长方体形地形成。另一校准凹部25棱锥形或圆锥形地形成。分别将电子开关13分配给接触凹部11。开关13例如是晶体管。
每个接触凹部11部分地用焊接材料12填充。焊接材料12例如是AuSn。焊接材料12与开关13导电连接。能够看出的是：不同接触凹部11中的焊接材料12彼此不连续并且彼此电绝缘。特别地，连接载体1的上侧10的在接触凹部11之外的区域没有焊接材料12。
在图1B中示出该方法中的位置，在所述位置中，将半导体芯片2通过接触销21朝前放置到连接载体1的上侧10上。接触凹部11中的焊接材料12事先至少部分地熔化。
在放置时，校准销25首先被引入到校准凹部15中。通过校准销25的变细的形状，所述校准销在引入时经由上侧10的邻接于校准销15的棱边滑动。这又导致：自动地将半导体芯片2横向移动和/或转动并且由此相对于连接载体1对其进行校准(参见箭头)。于是，随后接触销21进入到接触凹部11中并且在此由熔化的焊接材料12浸湿。
在图1C中，半导体芯片2以其相对于连接载体1的最终位置放置在连接载体1上。接触销21在此例如通过等温固化与接触凹部11中的焊接材料形状配合地连接并因此与开关13导电地连接。图1C同时示出了制造完成的电子元件100。
在图2A中示出了用于制造半导体芯片的一个实施例中的第一位置。半导体芯片例如是图1A至图1C的半导体芯片。首先，提供基体(例如晶片复合体)。基体包括半导体本体26以及电绝缘层27。电绝缘层27的背离半导体本体26的一侧形成基体的底侧20。将第一掩膜层41(例如光刻胶层)施加到底侧20上。
在图2B中示出该方法的第二位置，在所述位置中借助于掩膜5使掩膜层41结构化。当前，为此使用光刻方法。通过结构化，在应当形成接触销和校准销的位置处将孔引入到掩膜层41中。
在图2C中示出了该方法的第三位置。在应当形成接触销的区域中，电绝缘层27附加地设有孔。为此，例如使用另一种光刻方法。
在图2D中示出了该方法的第四位置，在该位置中，在第一掩膜层41的孔的区域中形成接触销21和校准销25的第一部段。接触销21和校准销25的第一部段例如经由共同的第一电镀工艺来被施加。接触销21和校准销25的第一部段的垂直于底侧20测量的高度在制造公差的范围内相同。接触销21与半导体本体26导电连接。
另外，在图2D中能够看出：将第二掩膜层41施加到校准销25的第一部段和接触销21上并且将它们覆盖。
在图2E中示出了该方法的第五位置，在该位置中，例如再次借助于光刻方法使第二掩膜层42结构化。在此，露出校准销25的第一部段。接触销21还由第二掩膜层42覆盖。
在图2F中示出了该方法的第六位置，在该位置中，例如借助于第二电镀工艺制成校准销25。在此，增大校准销25的高度，使得现在校准销25比接触销21从底侧20突出得更远。
现在，第一掩膜层41和第二掩膜层42一起形成成形体4，该成形体侧向地成形校准销。校准销25在其整个高度上具有基本上恒定的直径。
在图2G中示出的该方法的第七位置中，分别将例如由铂制成的覆盖元件250施加到校准销25的背离半导体本体26的一侧上。覆盖元件250的直径分别小于校准销25的直径。
在图2H中示出了该方法的第八位置，在该位置中执行蚀刻工艺。在此，将蚀刻剂施加到校准销25和成形体4的背离半导体本体26的一侧上。
在图2I中示出了在蚀刻剂作用于校准销25和成形体4上一定时长之后的第九位置。将蚀刻剂选择成使得相比于校准销25其更加强烈地蚀刻成形体4。选择覆盖元件250，使得其不受蚀刻剂的侵蚀。通过相比于校准销蚀刻剂更加强烈地侵蚀成形体4，使得校准销25的侧面部分地暴露。然后，蚀刻剂同样作用于所述侧面上。
在图2J中示出了蚀刻剂作用更长时间之后的第十位置。
在图2K中示出了蚀刻剂作用还要更长时间之后的第十一位置。蚀刻剂使成形体4完全溶解。由于蚀刻速率不同，现在，校准销25分别具有在远离底侧20的方向上变小的直径。相同的情况适用于接触销21，所述接触销同样侧向地部分地由成形体4成形。图2J同时示出了制造完成的半导体芯片2。事先对基体进行了分割。
在图3中示出了该方法中的基本上对应于图2J的位置的位置。当然，在此，蚀刻剂对成形体4的蚀刻速率不显着大于其对校准销25的蚀刻速率，使得形成几乎针形的校准销25。
本申请要求德国专利申请10 2018 125 901.8的优先权，其公开内容通过参考并入本文。
本发明不受限于根据所述实施例进行的描述。更确切地说，本发明包括各个新的特征以及特征的各个组合，这尤其包含权利要求中的特征的各个组合，即使所述特征或所述组合本身没有在权利要求或实施例中明确地说明时也是如此。
附图标记说明
1连接载体
2半导体芯片
4成形体
5掩膜
10 上侧
11 接触凹部
12 焊接材料
13 开关
15 校准凹部
20 底侧
21 接触销
25 校准销
26 半导体本体
27 电绝缘层
41 第一掩膜层
42 第二掩膜层
100 电子元件
250覆盖元件

Claims (17)

1.一种用于制造电子元件(100)的方法，包括以下步骤：
A)提供半导体芯片(2)，所述半导体芯片具有底侧(20)、多个接触销(21)和至少一个校准销(25)，其中，
-所述接触销(21)和所述校准销(25)分别从所述底侧(20)突出，
-所述接触销(21)设计用于电接触所述半导体芯片(2)，
-所述校准销(25)在远离所述底侧(20)的方向上变细，
-所述校准销(25)比所述接触销(21)从所述底侧(20)突出得更远，
-所述校准销(25)在背离所述底侧(20)的一侧处包括覆盖元件(250)；
B)提供连接载体(1)，所述连接载体具有上侧(10)，多个接触凹部(11)和至少一个校准凹部(15)被引入到所述上侧中，其中，
-所述接触凹部(11)分别至少部分地用焊接材料(12)填充；
C)将所述接触凹部(11)中的焊接材料(12)加热到所述焊接材料(12)至少部分熔化的接合温度；
D)将所述半导体芯片(2)放置到所述连接载体(1)上，其中，
-所述接触销(21)被分别引入到所述接触凹部(11)中并且所述校准销(25)被引入到所述校准凹部(15)中，和
-所述接触销(21)浸入到熔化的焊接材料(12)中。
2.根据权利要求1所述的方法，其中，
-所述校准凹部(15)的直径大于所述校准销(25)的直径，
-所述校准凹部(15)的直径最大为所述校准销(25)的最宽部位处的直径的两倍，
-所述校准凹部(15)的深度大于所述接触凹部(11)的深度。
3.根据权利要求1或2所述的方法，
其中，将所述焊接材料(12)和所述接触销(21)的材料选择成使得在所述步骤D)中并且在所述接合温度下，所述焊接材料(12)和所述接触销(21)通过等温固化材料配合地彼此连接。
4.根据权利要求1或2所述的方法，
其中，借助所述方法将所述半导体芯片(2)电连接在所述连接载体(1)上。
5.根据权利要求1或2所述的方法，其中，
-所述半导体芯片(2)是像素化的光电子半导体芯片(2)，
-将像素化的所述半导体芯片(2)的一个或更多个像素(22)分配给每一个接触销(21)。
6.根据权利要求1或2所述的方法，其中，
-所述连接载体(1)包括多个电子开关(13)，
-每一个接触凹部(11)分配有一个开关(13)。
7.根据权利要求1或2所述的方法，
其中，在所述步骤D)中，将所述接触销(21)浸入到熔化的焊接材料(12)中，使得在每个接触凹部(11)中置换出的所述焊接材料(12)的体积至少为所述接触凹部(11)中的所述焊接材料(12)的总体积的10％。
8.根据权利要求1或2所述的方法，
其中，在所述接触凹部(11)和所述校准凹部(15)之外的区域中，与所述接触销(21)相比，所述连接载体(1)的上侧(10)更差地通过熔化的焊接材料(12)来被浸湿。
9.根据权利要求1所述的方法，
其中，所述覆盖元件(250)由铂制成。
10.一种电子元件(100)，包括：
-半导体芯片(2)，所述半导体芯片具有半导体本体(26)、底侧(20)、多个接触销(21)和至少一个校准销(25)，
-连接载体(1)，所述连接载体具有上侧(10)，将多个接触凹部(11)和至少一个校准凹部(15)引入到所述上侧中，其中，
-所述接触销(21)和所述校准销(25)分别从所述底侧(20)突出，
-所述接触销(21)设计用于电接触所述半导体本体(26)，
-所述校准销(25)在远离所述底侧(20)的方向上变细，
-所述校准销(25)比所述接触销(21)从所述底侧(20)突出得更远，
-所述校准销(25)在背离所述底侧(20)的一侧处包括覆盖元件(250)，
-所述接触凹部(11)分别至少部分地用焊接材料(12)填充，
-不同接触凹部(11)的所述焊接材料(12)不连续，
-所述半导体芯片(2)通过所述底侧(20)朝前安装在所述连接载体(1)的所述上侧(10)上，
-每个接触销(21)分配有一个接触凹部(11)，并且所述校准销(25)分配有校准凹部(15)，
-所述接触销(21)分别伸入到接触凹部(11)中，
-所述校准销(25)伸入到所述校准凹部(15)中，
-所述接触销(21)分别与所述接触凹部(11)的焊接材料(12)材料配合地连接。
11.根据权利要求10所述的电子元件(100)，
其中，所述校准销(25)与所述半导体本体(26)电绝缘。
12.根据权利要求10或11所述的电子元件(100)，
其中，所述半导体芯片(2)经由所述接触销(21)和所述焊接材料(12)电连接到所述连接载体(1)。
13.根据权利要求10所述的电子元件(100)，
其中，所述覆盖元件(250)由铂制成。
14.一种用于制造半导体芯片(2)的方法，包括以下步骤：
A)提供具有半导体本体(26)和底侧(20)的基体，其中，
-将多个接触销(21)和至少一个校准销(25)布置在所述半导体本体(26)上，所述接触销和校准销分别从所述底侧(20)突出，
-所述接触销(21)设计用于电接触所述半导体本体(26)，
-所述校准销(25)比所述接触销(21)从底侧(20)突出得更远，
-所述校准销(25)的直径在所述校准销(25)的整个高度上基本上是恒定的；
B)在所述校准销(25)旁边的区域中，在所述半导体本体(26)上形成成形体(4)，其中，所述成形体(4)侧向地成形所述校准销(25)；
C)通过将蚀刻剂施加到所述成形体(4)和所述校准销(25)的背离所述半导体本体(26)的一侧上来执行蚀刻工艺，其中，
-所述蚀刻剂侵蚀所述成形体(4)和所述校准销(25)，
-所述蚀刻剂对所述成形体(4)的蚀刻速率高于其对所述校准销(25)的蚀刻速率，
-执行所述蚀刻工艺直至所述校准销(25)的形状改变成使得所述校准销(25)在远离所述底侧(20)的方向上变细。
15.根据权利要求14所述的方法，
其中，执行步骤C)中的所述蚀刻工艺直至所述成形体(4)被完全移除。
16.根据权利要求14或15所述的方法，
其中，在所述步骤A)之前将所述接触销(21)和所述校准销(25)电镀地施加在所述半导体本体(26)上。
17.根据权利要求16所述的方法，其中，
-所述接触销(21)和所述校准销(25)的第一部段借助于第一电镀工艺被共同制造，
-然后在第二电镀工艺中制造完成所述校准销(25)。
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