CN101828435A - 具有多个层的凸块结构及其制造方法 - Google Patents

具有多个层的凸块结构及其制造方法 Download PDF

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CN101828435A
CN101828435A CN200880112141A CN200880112141A CN101828435A CN 101828435 A CN101828435 A CN 101828435A CN 200880112141 A CN200880112141 A CN 200880112141A CN 200880112141 A CN200880112141 A CN 200880112141A CN 101828435 A CN101828435 A CN 101828435A
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layer
base substrate
ground floor
substrate
projection cube
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CN101828435B (zh
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李相澈
金成旭
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SML Electronics Inc
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Abstract

本发明涉及一种具有多个层的凸块结构，其可以包括：第一层，电连接到密封封装底部衬底的保护衬底，该第一层允许底部衬底和保护衬底彼此以预定距离隔开；第二层，电连接到所述第一层，该第二层共晶地结合到底部衬底的表面上。第一层的熔点比第二层与底部衬底的共晶温度高。当使用具有多个层的凸块结构时，可以保证一空间，底部衬底上的诸如微机电系统(MEMS)器件的微结构可在该空间中被驱动。此外，可以防止邻近结构或电极之间由于密封封装工艺中的结合材料扩散而产生接触。

Description

具有多个层的凸块结构及其制造方法
技术领域
本发明示例性实施例涉及用于晶片级密封封装的具有多个层的凸块结构(bump structure)及其制造方法。更具体地，本发明示例性实施例涉及具有多个层的凸块结构以及制造该凸块结构的方法，该凸块结构电连接在底部衬底(base substrate)和保护衬底之间从而用作挡块(stopper)和隔离器(spacer)，并且共晶结合到底部衬底以便密封封装保护衬底和底部衬底，该底部衬底具有微结构，如微机电系统(MEMS)器件或半导体芯片。
背景技术
近来，微机电系统(MEMS)技术已经作为创新系统最小化技术引入，其将在将来引领电子器件和半导体技术领域。MEMS技术是这样的技术，其中系统特定部分是通过对诸如硅衬底的衬底使用硅工艺而以微米量级的复杂形状集成和形成。MEMS技术基于半导体器件制造技术，其包括薄膜沉积技术，刻蚀技术，光刻技术，杂质扩散和注入技术，等等。
使用MEMS技术所制造的器件对外部环境是敏感的，该外部环境包括温度、湿气、微粒、振动、冲击(impact)等等。结果，器件可能无法正确操作，或在操作过程中频繁出现错误。因此，要求通过在用于设置MEMS器件的底部衬底上形成保护衬底而允许MEMS器件被保护免受外部环境影响，从而形成密封封装的MEMS封装体。
当形成前述MEMS封装体时，需要预定空间以便MEMS器件(例如加速度传感器)可被正常驱动。这里，微结构，诸如要驱动的加速度传感器的感测电极需要空间。因此，保护衬底和形成有MEMS器件的底部衬底之间需要保持预定的间隔距离，以便MEM器件可在该结构内驱动。
进一步，在现有技术的MEMS封装体中，底部衬底通过由焊料材料或金属材料制成的凸块结构结合到保护衬底，并由保护衬底密封封装。然而，当通过由单种材料制成的凸块结构将底部衬底与保护衬底结合在一起时，由于局部熔融，凸块结构的上表面是水平扩散的，且因此容易出现凸块结构变形。这样的变形凸块结构可导致其靠近另一个凸块结构、或者通过形成在衬底上的结构和互连穿透或接触另一个凸块结构。因此，可出现电气故障。
发明内容
技术问题
因此，提供了用于密封封装的具有多个层的凸块结构，该凸块结构提供用于驱动底部衬底表面上形成的微结构(如MEMS器件)的空间并防止由于结合材料在与底部衬底和保护衬底结合时的扩散导致邻近结构或电极之间形成接触，还提供了制造凸块结构的方法。
技术方案
示例性实施例提供了具有多个层的凸块结构，其包括：电连接到密封封装底部衬底的保护衬底的第一层，第一层允许底部衬底和保护衬底彼此以预定的距离隔开；电连接到第一层的第二层，第二层共晶结合到底部衬底的表面。
另一个示例性实施例提供密封封装的结构，其包括：底部衬底，其具有在其表面上形成的微结构；保护衬底，其密封封装底部衬底；第一层，电连接到保护衬底的底部表面，第一层允许底部衬底和保护衬底彼此以预定距离隔开，以便在底部衬底上形成的微结构可被驱动；第二层，其电连接到第一层，第二层共晶结合到底部衬底表面上。
另一个示例性实施例提供了制造具有多个层的凸块结构的方法，其包括：在密封封装底部衬底的保护衬底上形成第一层，该第一层允许底部衬底和保护衬底彼此以预定距离隔开；在第一层上形成第二层以便共晶结合到底部衬底；以及将第二层和底部衬底共晶地结合。
根据示例性实施例，第一层的熔点可比第二层和底部衬底的共晶温度高。
有益效果
当使用具有多个层的凸块结构时，可以保证一空间，其中，在底部衬底表面上形成的微结构(诸如MEMS器件)可在该空间中被驱动。此外，可以防止由于密封封装工艺中结合材料的扩散导致邻近结构或电极间产生接触。
附图说明
下面参考一些附图中示出的示例性实施例更详细地说明本发明，附图在下面仅以示例方式给出，因此不限制这里公开的示例性实施例，其中：
图1是使用根据示例性实施例的凸块结构的密封封装结构的透视图；
图2是沿图1中的线A-A’截取的密封封装结构的截面透视图；
图3是图2中所示截面的一部分的部分放大截面图；
图4是根据另一个示例性实施例的凸块结构的一部分的截面图；
图5是底部衬底和保护衬底的截面图；
图6是硅层形成后的底部衬底和保护衬底的截面图；
图7是第一层形成后的底部衬底和保护衬底的截面图；
图8是第二层形成后的底部衬底和保护衬底的截面图；
图9是扩散阻挡层形成后的底部衬底和保护衬底的截面图；
应该理解，附图不必按比例，而是给出简化表示。这里所述的特定设计特征(例如包括特定尺寸、取向、位置、和形状)部分地由特定应用和使用环境确定。
在所有附图中，相同或等同部件以相同标号表示。
具体实施方式
下面将详细参考这里公开的不同实施例，实施例中例子在附图中示出并在下面说明。虽然这里公开的实施例将结合示例性实施例说明，但可以理解本说明书不是限制性的。相反，这里公开的实施例不仅涵盖示例性实施例，而且涵盖不同替换、修改、等同实施例和其他实施例，其包括由权利要求限定的精神和范畴内。
图1是使用根据这里公开的示例性实施例的凸块结构的密封封装结构的透视图。
如图1所示，底部衬底11设置在密封封装的凸块结构的下部。底部衬底11可包括不同类型的衬底，如印制电路板(PCB)和半导体衬底。底部衬底11可由硅(Si)形成。保护衬底16设置在底部衬底11上方。底部衬底11由保护衬底16覆盖和密封封装。底部衬底11和保护衬底16通过根据下面将会描述的示例性实施例的凸块结构彼此电连接。
图2是沿图1中线A-A’截取的密封封装结构的截面透视图。在图2中示出了区域10，根据示例性实施例的密封封装结构中的凸块结构位于该区域10中。如图2所示，根据示例性实施例的凸块结构设置在底部衬底11和保护衬底16之间的一部分区域中，以便两个衬底通过凸块结构电连接。底部衬底11和保护衬底16由凸块结构以预定的距离彼此隔开，以便提供一空间，其中在底部衬底11的表面上形成的诸如微机电系统(MEMS)器件的微结构在该空间中被驱动。
图3是图2中所示截面图中区域10的部分放大截面图，根据示例性实施例的凸块结构设置在该区域10。参考图3，凸块结构包括：电连接到保护衬底16的底部表面的第一层15；和第二层14，其电连接到第一层15并共晶结合到底部衬底11的表面上。第一层15和第二层14由具有相对良好导电率的一种或多种金属形成。
微结构12在底部衬底11的表面上形成。在一个示例性实施例中，微结构12可以是MEMS器件，如加速度传感器或惯性传感器。可替换地，微结构可以是半导体芯片。当通过使用根据示例性实施例的凸块结构执行密封封装时，底部衬底11共晶结合到凸块结构的第二层14。共晶结合指结合方法，其中结合层是通过加热到共晶温度的热压金属形成的，然后在低于共晶温度的温度固化金属。为了共晶结合，底部衬底11可由硅(Si)形成。当底部衬底11不是由硅形成时，凸块结构可进一步包括在底部衬底11的表面上形成并共晶结合到第二层14的硅层13。
底部衬底11与保护衬底16结合并由保护衬底16密封封装。保护衬底16是将底部衬底11与外部环境屏蔽的衬底。保护衬底16在底部衬底11上方通过使用根据示例性实施例的凸块结构与底部衬底11结合。在该情形中，凸块结构也用作一路径，底部衬底11和保护衬底16经该路径电连接。
第一层15电连接到保护衬底16的底部表面。第一层15用作底部衬底11和保护衬底16之间的隔离器和挡块。首先，第一层15用作允许底部衬底和保护衬底16彼此以预定距离隔开的隔离器，因此用于驱动微结构12的空间形成在两个衬底之间。MEMS器件，如加速度传感器的正常操作要求一空间。在该空间中，用于加速度感测等的微电极根据加速度上下或左右移动。因此，当底部衬底11与保护衬底16结合并由保护衬底16密封封装时，根据所需空间的尺寸，通过调整第一层15的高度，底部衬底11和保护衬底16可彼此以所需距离隔开。
此外，第一层15用作挡块，该挡块限制第二层14在共晶结合过程中水平扩散到第二层14的厚度上。在示例性实施例中，第一层15的熔点比第二层14和底部衬底11的共晶温度或者第二层14和硅层13的共晶温度高。在该情形中，第一层15在第二程14与硅的共晶结合过程中不熔化。因此，可以防止第一层15的物理形状由于共晶结合而变形。因此，凸块结构的形状可保持牢固。
例如，当第二层14由金(Au)形成并且底部衬底11由硅(Si)形成时，Au-Si的共晶反应是在第二层14和底部衬底11之间的接触表面处发生的。因此，第一层15可由熔点高于363℃(该温度是Au-Si的共晶温度)的材料形成。在示例性实施例中，第一层15可包括从由铜、铜合金、钛、钛合金、铬、铬合金、镍、镍合金、金、金合金、铝、铝合金、钒和钒合金组成的组中所选择的任何一种材料，但不限于这些。也就是说，第一层15可由不同种类的金属制成。
由于第一层15，可以防止凸块结构在共晶结合过程中过度水平扩散。因此，可以防止凸块结构电连接到底部衬底11上的邻近结构或另一个凸块结构上。进一步，因为第一层15连接到第二层14以形成凸块结构，第二层14的厚度可比凸块结构仅由第二层14形成时减小很多。当第二层14由诸如金(Au)的高价金属形成时，凸块结构的大部分可由第一层15形成，以便第一层15的厚度比第二层14的厚度大。因此，第二层14可形成为共晶结合所需的最小厚度，因而节省形成凸块结构所用材料的成本。
共晶结合到底部衬底11的第二层14被电连接到第一层15的底部表面。在示例性实施例中，第二层14可由金(Au)形成并且底部衬底11可由硅(Si)形成。底部衬底11和第二层14通过Au-Si共晶结合来彼此共晶结合。第二层14通过共晶结合而水平扩散。因此，第二层14和底部衬底11之间的接触界面的面积增加。
在图3所示的示例性实施例中，第二层14共晶结合到在底部衬底11的表面上形成的微结构12的顶部，这仅用于说明的目的。可替换地，第二层14可共晶结合到在底部衬底11上没有形成微结构12的区域。
如上所述，具有两个层的凸块结构(即，第一层和第二层)已经在图3所示的实施例描述。另一方面，图4示出了具有三个层的凸块结构，其与图3中所示的示例性实施例不同。
参照图4，进一步在第一层15和第二层14之间形成扩散阻挡层17。扩散阻挡层17是防止构成第二层14的材料由于第二层在共晶结合过程中熔化而扩散到第一层15的层。扩散阻挡层17可由用于扩散阻挡层或结合层的材料制成，该材料包括镍、钛、铬、铜、钒、铝、金、钴、锰、钯或其合金。可替换地，一个或多个层可构成扩散阻挡层17。
图5到9是截面图，其示出了制造根据示例性实施例的具有多个层的凸块结构的方法。首先，底部衬底11和保护衬底16在图5中示出。这里，凸块结构还没有形成在底部衬底11和保护衬底16之间。当底部衬底不是由硅(Si)形成时，用于共晶结合的硅层13在底部衬底11上形成，如图6所示。如下面将会描述的，硅层13、第一层15、第二层14以及扩散阻挡层17可通过沉积、镀覆或其他不同工艺形成。
随后，如图7所示，第一层15在保护衬底16的一部分上形成。这里，第一层用作隔离器和挡块。此时，第一层15形成有足够厚度，以便保证一间隔距离，在底部衬底11表面上形成的微结构12可以在该间隔距离中被充分驱动。随后，如图8所示，第二层14在形成在保护衬底16上的第一层15上形成，因而形成凸块结构。在示例性实施例中，在第二层形成之前，扩散阻挡层17可在第一层15上形成，如图9所示。这里，扩散阻挡层17防止第一层15和第二层14之间的扩散。
一旦形成扩散阻挡层17，底部衬底11和保护衬底16通过共晶结合而彼此结合。为了共晶结合，首先通过对底部衬底11和保护衬底16施加压力使底部衬底11和保护衬底16彼此贴附。然后，凸块结构的第二层14和底部衬底11被加热到第二层14材料和底部衬底11材料的共晶温度。例如，当第二层14由金(Au)形成并且底部衬底11由硅(Si)形成时，Au-Si的共晶温度为363℃。凸块结构和底部衬底11通过加热彼此共晶结合，因而形成参照图3和图4所述的凸块结构。
如上所述，根据示例性实施例的凸块结构可应用于包括MEMS封装体和半导体封装体的不同类型的器件。特别地，根据示例性实施例的凸块结构可有效地应用Au-Si共晶结合。Au-Si共晶结合可广泛应用于晶片级真空封装MEMS器件(其通过振动来驱动)。进一步，除了MEMS器件，根据示例性实施例的凸块结构可用于不同类型的器件，不同类型的器件包括具有金属互连的硅晶片器件和具有由包括硅的不同金属形成的两维或三维结构的电子器件。
工业实用性
示例性实施例涉及用于晶片级密封封装的具有多个层的凸块结构及其制造方法。更具体地，示例性实施例涉及具有多个层的凸块结构，该凸块结构电连接在底部衬底和保护衬底之间以用作挡块和隔离器，并且该凸块结构共晶结合到底部衬底以便密封封装保护衬底和底部衬底，该底部衬底具有微结构，该微结构例如是微机电系统(MEMS)器件或半导体芯片，示例性实施例还涉及凸块结构的制造方法。

Claims (19)

1.一种具有多个层的凸块结构，其包括：
第一层，其电连接到密封封装底部衬底的保护衬底，所述第一层允许所述底部衬底和保护衬底彼此以预定距离隔开；以及
第二层，其电连接到所述第一层，所述第二层共晶地结合到所述底部衬底的表面上，
其中，所述第一层的熔点比所述第二层与所述底部衬底的共晶温度高。
2.根据权利要求1所述的凸块结构，其中，所述第一层的厚度比所述第二层的厚度大。
3.根据权利要求1所述的凸块结构，进一步包括在所述第一层与第二层之间形成的扩散阻挡层，所述扩散阻挡层防止构成所述第二层的材料在所述第二层和所述底部衬底的共晶结合过程中扩散到所述第一层中。
4.根据权利要求3所述的凸块结构，其中，所述扩散阻挡层包含从由镍、钛、铬、铜、钒、铝、金、钴、锰、钯或其合金组成的组中选择的至少一种材料。
5.根据权利要求1所述的凸块结构，其中，所述第二层由金形成。
6.一种密封封装的结构，其包括：
底部衬底，其具有在所述底部衬底的表面上形成的微结构；
保护衬底，其密封封装所述底部衬底；
第一层，其电连接到所述保护衬底的底部表面上，所述第一层允许所述底部衬底和保护衬底彼此以预定距离隔开，以便在所述底部衬底上形成的所述微结构可被驱动；以及
第二层，其电连接到所述第一层，所述第二层共晶地结合到所述底部衬底的表面上，
其中，所述第一层的熔点比所述第二层与所述底部衬底的共晶温度高。
7.根据权利要求6所述的密封封装结构，其中，所述第一层厚度比所述第二层的厚度大。
8.根据权利要求6所述的密封封装结构，进一步包括在所述第一与第二层之间形成的扩散阻挡层，所述扩散阻挡层防止构成所述第二层的材料在所述第二层和所述底部衬底的共晶结合过程中扩散到所述第一层中。
9.根据权利要求8所述的密封封装结构，其中，所述扩散阻挡层包含从由镍、钛、铬、铜、钒、铝、金、钴、锰、钯或其合金组成的组中选择的至少一种材料。
10.根据权利要求6所述的密封封装结构，其中，所述第二层由金形成，所述底部衬底由硅制成。
11.根据权利要求6所述的密封封装结构，其中，所述第二层由金形成，而所述底部衬底包括在所述底部衬底的表面上形成并共晶结合到所述第二层的硅层。
12.根据权利要求6所述的密封封装结构，其中，所述微结构是微机电系统器件。
13.一种制造具有多个层的凸块结构的方法，所述方法包括：
在密封封装底部衬底的保护衬底上形成第一层，所述第一层允许所述底部衬底和所述保护衬底彼此以预定距离隔开；
在所述第一层上形成第二层以便共晶结合到所述底部衬底；以及
将所述第二层和所述底部衬底共晶地结合，
其中，所述第一层的熔点比所述第二层和底部衬底的共晶温度高。
14.根据权利要求13所述的方法，其中，所述共晶结合的步骤包括：
施加预定压力使得所述底部衬底和第二层彼此紧密贴附；以及
以预定温度加热所述底部衬底和所述第二层。
15.根据权利要求13所述的方法，进一步包括在形成所述第一层之前在所述底部衬底上形成硅层。
16.根据权利要求13所述的方法，进一步包括在形成所述第二层之前在所述第一层上形成扩散阻挡层，所述扩散阻挡层防止构成所述第二层的材料在共晶结合过程中扩散到所述第一层中。
17.根据权利要求16所述的方法，其中，所述扩散阻挡层包含从由镍、钛、铬、铜、钒、铝、金、钴、锰、钯或其合金组成的组中选择的至少一种材料。
18.根据权利要求13所述的方法，其中，所述第一层由金形成。
19.根据权利要求13所述的方法，其中，所述第一层的厚度比所述第二层的厚度大。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960833A (zh) * 2016-01-11 2017-07-18 爱思开海力士有限公司 具有凸块接合结构的半导体封装

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8790946B2 (en) 2012-02-02 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of bonding caps for MEMS devices
KR102534735B1 (ko) 2016-09-29 2023-05-19 삼성전자 주식회사 필름형 반도체 패키지 및 그 제조 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613838B2 (ja) * 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
JPH09246273A (ja) * 1996-03-05 1997-09-19 Kokusai Electric Co Ltd バンプ構造
JP3584635B2 (ja) * 1996-10-04 2004-11-04 株式会社デンソー 半導体装置及びその製造方法
US6303986B1 (en) * 1998-07-29 2001-10-16 Silicon Light Machines Method of and apparatus for sealing an hermetic lid to a semiconductor die
JP2001155976A (ja) * 1999-11-26 2001-06-08 Matsushita Electric Works Ltd シリコンウェハの接合方法
JP2002289768A (ja) * 2000-07-17 2002-10-04 Rohm Co Ltd 半導体装置およびその製法
KR100396551B1 (ko) * 2001-02-03 2003-09-03 삼성전자주식회사 웨이퍼 레벨 허메틱 실링 방법
KR100442830B1 (ko) * 2001-12-04 2004-08-02 삼성전자주식회사 저온의 산화방지 허메틱 실링 방법
KR100584972B1 (ko) * 2004-06-11 2006-05-29 삼성전기주식회사 밀봉용 스페이서가 형성된 ｍｅｍｓ 패키지 및 그 제조 방법
US7569926B2 (en) * 2005-08-26 2009-08-04 Innovative Micro Technology Wafer level hermetic bond using metal alloy with raised feature

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960833A (zh) * 2016-01-11 2017-07-18 爱思开海力士有限公司 具有凸块接合结构的半导体封装
CN106960833B (zh) * 2016-01-11 2019-09-06 爱思开海力士有限公司 具有凸块接合结构的半导体封装

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