CN101814519B - 背照式图像感测器及其制造方法 - Google Patents
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Abstract
本发明提供一种背照式图像感测器及其制造方法。该图像感测器包括一半导体基板,一保护环结构,于该基板中,以及至少一像素,为该保护环结构所包围。该保护环结构通过高能量注入形成于该基板中。本发明通过对基板前侧表面进行离子注入形成保护环结构以及对注入保护环的基板进行回火以移除因注入与活化注入掺质造成的损伤,以降低成品元件保护环中硅损伤的量。
Description
技术领域
本发明涉及一种半导体结构,特别涉及一种背照式图像感测器及其制造方法。
背景技术
一图像感测器提供一像素网格,例如感光二极管或光二极管、复位晶体管、源极随耦器晶体管、固定层光二极管及/或转移晶体管,以记录光的强度及亮度。每一像素通过累积电荷载子(例如电子及/或空穴)以对光作出响应。当光进入一硅层时,通过光产生电荷载子。进入的光愈多,产生愈多电荷载子。以感测元件测量电荷载子并供其他电路使用此测量结果,以提供颜色与亮度信息用于适合的应用,例如数码相机。一般型式的像素网格包括电荷耦合元件(CCD)或互补式金属氧化物半导体(CMOS)图像感测器。
在半导体技术中,背照式感测器用来感测投射至基板背侧表面的光量。然而,感测元件形成于基板前侧。因此,光必须穿过基板方能到达感测元件。光可穿过基板到达感测元件,但部分光在穿过基板时,会产生散射。而散射光到达邻近像素及其相对应的感测元件,导致不同感测信号间的串音。
发明内容
本发明的一实施例,提供一种背照式图像感测器的制造方法,包括:提供一半导体基板,具有一前侧表面与一背侧表面;对该半导体基板的该前侧表面实施一离子注入工艺,以于该半导体基板中形成一保护环结构,该保护环结构具有一第一深度,该离子注入工艺具有一能量,大于500keV;以及形成至少一图像感测元件于该半导体基板的该前侧表面上,该至少一图像感测元件为该保护环结构所包围。
本发明的一实施例,提供一种背照式图像感测器的制造方法,包括:提供一半导体基板,具有一像素区与一周边电路区;对该半导体基板实施一离子注入,以于该像素区中形成一保护环结构,其中该保护环结构延伸进入该半导体基板,达到一第一深度;形成至少一图像感测元件于该半导体基板的该像素区上,该至少一图像感测元件为该保护环结构所包围;以及对该半导体基板实施一离子注入,以于该周边电路区中形成一阱,其中该阱延伸进入该半导体基板,达到一第二深度,其中该第一深度不同于该第二深度。
本发明的一实施例,提供一种背照式图像感测器,包括:一半导体基板,具有一像素区与一周边电路区;多个图像感测元件,形成于该像素区内,于该半导体基板的一前侧表面上;一离子注入保护环结构,形成于该像素区中,其中该离子注入保护环结构具有一第一深度,延伸进入该半导体基板并包围每一该图像感测元件;以及一离子注入阱,形成于该周边电路区中,其中该离子注入阱具有一第二深度,延伸进入该半导体基板,其中该第一深度大于该第二深度。
本发明通过对基板前侧表面进行离子注入形成保护环结构以及对注入保护环的基板进行回火以移除因注入与活化注入掺质造成的损伤,以降低成品元件保护环中硅损伤的量。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举一较佳实施例,并配合所附附图,作详细说明如下。
附图说明
图1是根据至少一实施例,一具有多个像素与一保护环结构的感测器背侧平面图。
图2A~2D是根据图1,形成一感测器的剖面示意图,其中根据至少一实施例,于一半导体基板的一前侧表面中,注入一保护环结构;
图3是根据至少一实施例,一改善背照式感测器效能的工艺流程图;
图4是根据至少一实施例,一形成于专用集成电路(ASIC)旁的感测器剖面示意图。
并且,上述附图中的附图标记说明如下:
100、300~(背照式)图像感测器;
110~(半导体)基板;
112~前表面(侧)(前侧表面);
114~后表面(侧)(后侧表面);
120、125~(背照式)像素(电路支援像素);
122~多层内连线;
122a~(第一)金属层;
122b~(第二)金属层;
127~图像感测元件;
128~层间介电层;
129~介层窗;
130~保护环结构;
140~p层;
142~外延层;
150~光;
180~周边电路区;
181~阱;
182~像素区;
184~专用集成电路(区);
202~于半导体基板的前侧中,形成保护环结构(实施保护环结构的前侧高能量注入,以及于基板上形成像素);
204~回火步骤(对具有保护环结构的基板与具有图像感测元件的像素进行回火)(对基板进行回火);
206~于基板的前侧上,形成具有层间介电层的多层内连线(于基板上形成金属层与层间介电层);
208~自背侧缩减基板的厚度至预定厚度(缩减基板的厚度至预定厚度);
D、D1~保护环结构的深度;
D1~阱深度;
T~基板背侧部分(厚度)。
具体实施方式
根据一或多个实施例,本发明提供一种背照式互补式金属氧化物半导体(CMOS)图像感测器(CIS)及改善电子串音、降低白像素及暗电流噪声的制造方法。揭示互补式金属氧化物半导体图像感测器(CIS)的实施例包括一像素或次像素网格,每一像素或次像素以一注入于一基板中的保护环结构包围之。本发明公开的互补式金属氧化物半导体图像感测器(CIS)及其制造方法通过对基板前侧表面进行离子注入形成保护环结构以及对注入保护环的基板进行回火以移除因注入与活化注入掺质造成的损伤,以降低成品元件保护环中硅损伤的量。由于回火步骤的温度须达450度或更高,在某些实施例中,更高达800至900度或更高,而于此高温下,会熔融多层内连线(MLI)层中的任何金属,破坏此层结构,因此,一般会于形成层间介电层(ILD)与多层内连线(MLI)层前,先实施回火步骤。此外,半导体元件中用以隔离多层内连线(MLI)层的许多阻挡层材料也无法承受上述高温,致金属掺质迁移进入硅中,导致半导体元件失效。
图1为根据一实施例,一图像感测器100的一高阶附图。图像感测器100包括一形成于一半导体基板110上或于半导体基板110内的背照式像素120网格。在至少一实施例中,保护环结构130设置成多重例如方形(其他形状亦可适用)的围栏,每一方形围栏包围一像素120或多重像素。本发明公开的方法包括提供具有一前表面112与一背表面114的半导体基板110,其中一前侧注入工艺用来形成注入于前侧112的保护环结构130。由于图1是描绘图像感测器100的背表面114,致前侧112并未见于图1中。
于一无保护环结构的感测器中,来自一光源(未图示)的光150或其他发射信号自背表面114进入形成每一像素120的材料。大部分进入一特定像素例如像素120中的像素125的光150为像素125所吸收。吸收的光于像素125中产生电荷载子。然而,一部分进入像素125的光不为像素125所吸收。一部分未吸收的光穿透像素125至前侧112,而另一部分未吸收的光反射出背侧114。未吸收光的反射与穿透部分的光信号不为像素125所收集而损失,此仅减少光信号为像素125所感测的量。
此外,部分进入像素125的光150会散射,如穿透像素125的光。散射光会以任意方向离开像素125,而可能到达邻近像素125的另一像素。若散射光为邻近像素所吸收,则产生的电荷载子会贡献至邻近像素的信号,导致串音。
以一与背侧表面114垂直的方向自背侧表面114进入像素125的光150仅穿透像素125,假设光150不产生散射。以一与背侧表面114垂直方向倾斜的角度自背侧表面114进入像素125的光150亦可穿透像素125以外的像素,而为像素125以外的像素所吸收。因此,以一与背侧表面114垂直方向倾斜的角度自背侧表面114进入像素125的光150亦会导致像素120之间的串音。
为避免或至少降低上述串音效应,本发明自基板110的前侧表面112形成保护环结构130。由于保护环结构130不为如基板110的透明,因此,保护环结构130可避免任一像素120的光达到任一邻近像素,致可降低或消除上述像素120之间的串音。再者,保护环结构130可避免每一像素(例如像素125)中光产生的电荷载子漂移至其他像素120。因此,保护环结构130可同时降低将一图像发射信号转换为一电子信号的像素其输出信号中光与电子的串音。
图2A公开一图像感测器100的前段(FEOL)制造步骤,其中于半导体基板110中,形成保护环结构130。基板110包括硅,在至少某些实施例中,基板110包括其他基本的半导体材料,例如锗或碳。在至少某些实施例中,基板110亦包括一化合物半导体,例如碳化硅、砷化镓、砷化铟或磷化铟。在至少某些实施例中,基板110包括一合金半导体,例如锗化硅、硅锗碳、镓砷磷或镓铟磷。在至少一实施例中,基板110包括p型硅。在至少某些实施例中,基板110还包括不同p型掺杂区及/或n型掺杂区。在某些实施例中,通过一例如不同步骤及技术的离子注入或扩散工艺进行掺杂。此外,在至少一实施例中,基板110包括隔离结构,其为众所皆知用以分离形成于基板110中的不同元件。此外,在至少一实施例中,基板110包括其他结构,例如一外延层142(例如一掺杂p的硅外延层)、一绝缘层上覆半导体(SOI)结构及/或其组合,以于图像感测器100的背侧114上形成一p层140。上述实施例并未限定p型或掺杂p的硅或层,上述材料或层的其中任一可为n型或掺杂n的硅或层所取代。
在至少某些实施例中,保护环结构130自基板110的前侧表面112延伸至基板110的背侧表面114。在至少一实施例中,通过对基板110的前侧表面112实施例如离子注入或离子金属等离子体注入的高能量注入,以形成保护环结构130。在注入过程中所使用的注入材料包括例如硼、铝或镓的p型掺质其中任一或例如锑、磷或砷的n型掺质其中任一。上述掺质的任意组合亦可作为注入材料。在某些实施例中,保护环结构130为一深的p型阱,其深度大于一形成于一周边电路区的p型阱。在另一实施例中,保护环结构130为一深的n型阱,其深度大于一形成于一周边电路区的n型阱。典型的离子注入以形成保护环结构130的能量大于500keV。在某些实施例中,离子注入能量介于1.0~1.5MeV之间。在至少某些实施例中,保护环结构130,自前侧表面112延伸至基板110中。在某些实施例中,保护环结构130具有一深度D,以于像素120之间提供有效的串音隔离。
一旦注入形成前侧保护环结构130后,即对基板110进行回火,以强化基板110,降低脆度。回火步骤204移除大部分或所有因任何离子注入及/或活化任何注入掺质材料对基板造成的损伤。本发明通过已知的回火技术实施回火,包括激光回火、快速热回火(RTA)与传统炉管回火。与本发明图像感测器100的制造方法不同,公知图像感测器的制造方法于形成一背侧感测隔离结构与进行回火前,于包含基板的晶片前侧上先形成层间介电(ILD)与金属多层内连线(MLI)层。由于激光回火与快速热回火(RTA)须超过450度以上的温度,因此,公知图像感测器制造方法于晶片上形成金属层后进行回火,极易造成金属层熔融,使金属迁移至半导体中,导致原件损伤。换句话说,本发明公开的元件及其制造方法可克服使用一前侧高能量注入工艺于基板110前侧表面112上形成保护环结构130以及于基板110前侧表面112上形成任何金属多层内连线(MLI)122(金属层122a、122b)前对注入保护环基板进行回火所产生的缺点。
图2B公开后段工艺(BEOL)前的图像感测器100。每一像素120为保护环结构130所包围。于半导体基板110的前侧表面112上,形成感测光及/或电荷载子的图像感测元件127。在某些实施例中,图像感测元件127包括通过一例如扩散或离子注入的方法于半导体基板110中形成具有p型及/或n型掺质的掺杂区。
在某些实施例中,形成于像素120中的图像感测元件127包括扩散或形成于基板110中的光二极管、光晶体管、互补式金属氧化物半导体(CMOS)图像感测器、电荷耦合元件(CCD)感测器、有源感测器、无源感测器及/或其他感测器。在不同实施例中,形成于像素120中的图像感测元件127亦包括任何有源或无源元件,例如非用于感测光或电荷的二极管、晶体管、开关、电阻器或电容器。这些额外元件可用于选择像素的读取、放大或对于每一像素120与图像感测器100的功能而言为必要的任何其他功能,如像素120包括已知及/或未来发展的图像感测元件。在某些实施例中,包括多个设置于一感测器阵列或其他适当结构中的像素。再者,在某些实施例中,多个像素120包括不同型式的感测器,例如在一已知结构中,一像素族群包括互补式金属氧化物半导体(CMOS)元件,而另一像素族群包括无源感测器。此外,在至少某些实施例中,像素120包括彩色图像感测器及/或单色图像感测器。背照式图像感测器100可接收自半导体基板110背表面114射入的光(或其他辐射),以消除/及或降低例如栅极结构与金属导线所造成的光路径阻碍,以及增加像素120光感测区的曝光。在至少某些实施例中,对基板110进行薄化,亦即降低基板110的厚度,使得穿透背表面114的光可有效到达像素120。
在某些实施例中,所有形成像素120及/或图像感测元件127及/或保护环结构130的步骤中均须实施离子注入,之后,进行回火。在至少该些实施例其中之一中,于任何注入步骤后,实施一常见的回火步骤,以对像素120、图像感测元件127与保护环结构130其中之一以上同时进行回火。本发明可通过任何已知或未来发展的技术实施注入,包括但不限定于离子注入、高能量离子注入与离子金属等离子体注入。回火步骤可移除因任何注入与活化注入掺质对基板造成的损伤。本发明可通过任何已知或未来发展的技术实施回火,包括但不限定于烤箱回火、激光回火与快速热回火(RTA)。于形成一多层内连线的任一部分前,实施任何注入与回火步骤,以形成像素120、图像感测元件127与保护环结构130。
图2C显示于图2B公开的工艺后,其上形成有多层内连线(MLI)122的图像感测器100。在至少一实施例中,多层内连线(MLI)122包括电性连接至像素120的第一金属层122a与第二金属层122b,使像素120接收电量,以提供信号输出至相关电路。金属层122a、122b与基板110之间彼此以一层间介电层128加以分离。金属层122a与122b之间以及元件与金属层122a、122b之间以介层窗129加以连接。在不同实施例中,多层内连线(MLI)122中金属设置的路径避开像素区。虽于背照式图像感测器100中,金属不会阻挡来自到达像素的光,然金属层122a与122b却会产生额外的寄生电容,使得像素反应时间变差,亦会影响信号-噪声比(SNR)。在某些实施例中,多层内连线(MLI)122中金属设置的路径覆盖像素区。金属会反射光,以使穿透一像素未被吸收的光反射回像素,借此提供更多吸收光的机会。如此,可增强光信号,特别是对于更易穿透像素材料的长波长的光。
在某些实施例中,形成多层内连线(MLI)122的材料包括铝、铜、钨、钛、氮化钛、钽、氮化钽、金属硅化物或其组合。形成多层内连线(MLI)122的方法包括物理气相沉积(或溅镀)、化学气相沉积(CVD)或其组合等工艺。其它用来形成多层内连线(MLI)122的制造技术包括光微影工艺以及通过蚀刻对垂直连接(介层窗与接触窗)与水平连接(导线)的导电材料进行图案化。在某些实施例中,通过例如热回火的其他工艺,以形成金属硅化物。一铜多层内连线所使用的材料包括铜、铜合金、钛、氮化钛、钽、氮化钽、钨、多晶硅、金属硅化物或其组合。在某些实施例中,通过包括化学气相沉积(CVD)、溅镀、电镀或其他适当工艺技术形成铜多层内连线。再者,在某些实施例中,多层内连线中所使用的金属硅化物包括镍硅化物、钴硅化物、钨硅化物、钽硅化物、钛硅化物、铂硅化物、铒硅化物、钯硅化物或其组合。
在不同实施例中,层间介电层128所使用的材料包括氧化硅、氮化硅、氮氧化硅、聚亚酰胺、旋涂式玻璃(SOG)、掺氟硅玻璃(FSG)、掺碳氧化硅、BLACK DIAMONDTM(购自加州圣克拉拉应用材料公司)、XEROGELTM、AEROGELTM、非晶氟化碳、聚对二甲苯、苯并环丁烯(BCB)、SILKTM(购自密西根米德兰陶氏化学公司)及/或其他适合材料。在至少一实施例中,通过包括旋转涂布、化学气相沉积(CVD)、溅镀或其他适当工艺技术形成层间介电层128。在至少某些实施例中,通过一整合工艺形成多层内连线122与层间介电层128,上述整合工艺包括一例如双镶嵌工艺或单镶嵌工艺的镶嵌工艺。
图2D显示图2C经薄化后的图像感测器100。对基板110背侧部分T(如图2C所示)进行薄化,以缩短来自一光源的光150及/或通过光产生于各别像素120中的电荷载子行经穿过基板110到达图像感测元件127的距离。在至少一实施例中,通过第一次研磨基板110的背侧表面114,以薄化基板110,之后,进行多重步骤的湿蚀刻,以降低基板110厚度至一预定厚度。在至少一实施例中,对基板110的T进行薄化,以降低基板110厚度至与保护环结构130高度相同的深度D。因此,在某些实施例中,保护环结构130自基板110的前侧表面112延伸至基板110的背侧表面114,以使像素120之间彼此隔离。
图3根据一实施例,公开上述图像感测器100的制造方法。步骤202请参阅图2A,于半导体基板110的前侧112中,形成保护环结构130。在某些实施例中,通过离子金属等离子体注入形成保护环结构130并使其自基板110的前表面112延伸一预定距离D至基板110的背表面114。于基板110的前侧表面112上或于前侧表面112内,形成至少一具有一图像感测元件127的像素120。据此,保护环结构130包围每一像素120,以避免供特定像素120使用的光能及/或电荷载子分散至邻近像素。
步骤204请参阅图2B,利用至少其中的一种常见已知的回火方法,包括但不限定于烤箱回火、激光回火与快速热回火(RTA),对具有保护环结构130的基板110与具有图像感测元件127的像素120进行回火。在某些实施例中,同时对保护环结构130与具有图像感测元件127的像素120实施一单一常见的回火步骤。
步骤206请参阅图2C,于基板110的前侧112上,形成具有层间介电层128的多层内连线122,以提供至像素120的电性连接。
步骤208请参阅图2D,自背侧114缩减基板110的厚度一厚度T至一预定厚度。在某些实施例中,缩减基板110的厚度至与保护环结构130的深度D相同。
图4根据另一实施例,一图像感测器300的侧视图,其中一周边电路区180(例如一专用集成电路(ASIC)形成区)邻近一像素区182,包括一控制电路(例如一专用集成电路(ASIC)区184),以提供电路支援像素120与至其他元件的外部连接。在至少一实施例中,周边电路区180包括一形成于基板110前侧112中具有一预定深度D2的阱181。根据电路设计需求,阱181为一p阱或一n阱。在某些实施例中,深度D2约为0.2微米。因此,形成的保护环结构130具有一深度D1,大于或等于阱181的深度D2。深度D1小于或等于基板110的厚度。若保护环结构130的深度D1小于阱181的深度D2,则专用集成电路(ASIC)184与邻近像素120之间会产生串音。基于上述理由,即通过一高能量离子注入形成保护环结构130。高能量离子注入的注入离子深入基板110中,其深度大于深度D2。高能量离子注入会对基板造成更大损伤,因此,须对基板进行一有效回火。本发明并未限定于仅包含p阱的专用集成电路(ASIC)。在某些实施例中,于周边电路区180中,通过一离子注入工艺形成阱181,此离子注入工艺与形成保护环结构130的高能量离子注入步骤不同。
本发明一或多个实施例提供一种改善背照式图像感测器灵敏度、避免串音,同时于回火过程中减少或避免可能产生图像感测器损伤的方法。
虽然本发明已以较佳实施例公开如上,然而其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的范围为准。
Claims (14)
1.一种背照式图像感测器的制造方法,包括:
提供一半导体基板,具有一前侧表面与一背侧表面;
对该半导体基板的该前侧表面实施一离子注入工艺,以于该半导体基板中形成一保护环结构,该保护环结构具有一第一深度,该离子注入工艺具有一能量,大于500keV;以及
形成至少一图像感测元件于该半导体基板的该前侧表面上,该至少一图像感测元件为该保护环结构所包围。
2.如权利要求1所述的背照式图像感测器的制造方法,还包括于形成该保护环结构后,对该半导体基板进行一回火,以及于该回火后,于该半导体基板的该前侧表面上形成一多层内连线结构,以与该至少一图像感测元件形成电性连接。
3.如权利要求2所述的背照式图像感测器的制造方法,还包括自该半导体基板的该背侧表面移除材料,以降低该半导体基板的一厚度至一预定厚度。
4.如权利要求3所述的背照式图像感测器的制造方法,其中降低该半导体基板的该厚度直至露出该保护环结构。
5.一种背照式图像感测器的制造方法,包括:
提供一半导体基板,具有一像素区与一周边电路区;
对该半导体基板实施一离子注入,以于该像素区中形成一保护环结构,其中该保护环结构延伸进入该半导体基板,达到一第一深度;
形成至少一图像感测元件于该半导体基板的该像素区上,该至少一图像感测元件为该保护环结构所包围;以及
对该半导体基板实施一离子注入,以于该周边电路区中形成一阱,其中该阱延伸进入该半导体基板,达到一第二深度,其中该第一深度大于该第二深度。
6.如权利要求4所述的背照式图像感测器的制造方法,其中形成该保护环结构的该离子注入具有一能量,大于500keV。
7.如权利要求4所述的背照式图像感测器的制造方法,还包括于形成该保护环结构后,对该半导体基板进行一回火。
8.如权利要求4所述的背照式图像感测器的制造方法,还包括于该半导体基板上形成一多层内连线结构,以与该至少一图像感测元件形成电性连接。
9.如权利要求4所述的背照式图像感测器的制造方法,还包括降低该半导体基板的一厚度至一预定厚度,该预定厚度相等于该保护环结构的该第一深度。
10.一种背照式图像感测器,包括:
一半导体基板,具有一像素区与一周边电路区;
多个图像感测元件,形成于该像素区内,于该半导体基板的一前侧表面上;
一离子注入保护环结构,形成于该像素区中,其中该离子注入保护环结构具有一第一深度,延伸进入该半导体基板并包围每一该图像感测元件;以及
一离子注入阱,形成于该周边电路区中,其中该离子注入阱具有一第二深度,延伸进入该半导体基板,其中该第一深度大于该第二深度。
11.如权利要求10所述的背照式图像感测器,其中该离子注入保护环结构为一p阱。
12.如权利要求10所述的背照式图像感测器,其中该离子注入阱为一p阱。
13.如权利要求10所述的背照式图像感测器,其中该离子注入阱为一n阱。
14.如权利要求10所述的背照式图像感测器,其中该离子注入保护环结构自该半导体基板的该前侧表面延伸至该半导体基板的一背侧表面。
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CN1630090A (zh) * | 2003-12-08 | 2005-06-22 | 台湾积体电路制造股份有限公司 | 具有光导管的影像感测装置及其制造方法 |
CN1819252A (zh) * | 2005-02-01 | 2006-08-16 | 索尼株式会社 | 固态图像拾取装置及其制造方法 |
CN1889270A (zh) * | 2005-07-12 | 2007-01-03 | 北京思比科微电子技术有限公司 | 高填充系数的有源像素图像传感器结构及制造方法 |
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CN101814519A (zh) | 2010-08-25 |
US8810700B2 (en) | 2014-08-19 |
US20130334645A1 (en) | 2013-12-19 |
US20100220226A1 (en) | 2010-09-02 |
US8531565B2 (en) | 2013-09-10 |
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