JP2017108109A - 半導体画像センサデバイス及び構造を形成する方法 - Google Patents
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Abstract
Description
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Claims (5)
- 画像センサデバイスを形成する方法であって、
第1の主面と反対側の第2の主面とを備える半導体基板であって、前記第1の主面に隣接して配置された第1の誘電体領域と、前記第1の誘電体領域に隣接して配置された第1の半導体領域とを更に備える半導体基板を提供することと、
複数のドープ領域を前記第1の半導体領域内に形成することと、
前記第1の半導体領域上に、前記複数のドープ領域の少なくとも一部に隣接する複数の導電構造であって、前記複数のドープ領域及び前記複数の導電構造はピクセル構造として構成された、複数の導電構造を形成することと、
その後、前記第1の半導体領域を通って前記第1の誘電体領域へと延在するトレンチを形成することと、
前記トレンチ内の導電材料であって、前記導電材料は前記第1の半導体領域から電気的に分離され、前記導電材料は金属を含み、前記トレンチ及び前記導電材料は導電トレンチ構造として構成された、導電材料を提供することと、
前記第1の半導体領域を覆う絶縁配線構造であって、前記トレンチ内の前記導電材料に電気的に結合された絶縁配線構造を形成することと、
前記半導体基板を除去し、前記第1の半導体領域に隣接する場所に前記第1の誘電体領域の少なくとも一部を残すことと、
前記第1の誘電体領域上に、前記トレンチ内の前記導電材料に電気的に結合された第1の電極を形成することと、を含む、方法。 - 前記第1の複数の導電構造及び前記第1の半導体領域の上方に第1の誘電体層を形成することを更に含み、前記トレンチを形成することは、前記第1の誘電体層及び前記第1の半導体領域を通って前記第1の誘電体領域へと延在する前記トレンチを形成することを含み、前記絶縁配線構造を形成することは、
前記第1の誘電体層内で、前記複数の導電構造及び前記複数のドープ領域に電気的に結合された複数の導電コンタクト構造を形成することと、
前記第1の誘電体層に隣接した第1の導電配線構造であって、前記第1のトレンチ内の前記導電材料及び前記複数の導電コンタクト構造の少なくとも一部に電気的に結合された第1の導電配線構造を形成することと、
前記第1の導電配線構造及び前記第1の誘電体層を覆う第2の誘電体層を形成することと、
前記第2の誘電体層を覆う上部導電構造であって、前記第1の導電配線構造に電気的に結合された上部導電構造を形成することと、
前記上部導電構造を覆う第3の誘電体層を形成することと、
アラインメント機構として前記導電トレンチ構造を使用して、前記上部導電構造の少なくとも一部を露出させる開口を形成することと、
前記第3の誘電体層を覆う第4の誘電体層であって、実質的に平らな外面を備える第4の誘電体層を形成することと、を含む、請求項1に記載の方法。 - 前記半導体基板を除去する前に、キャリア基板を前記絶縁配線構造の外面に取り付けることと、
前記第1の誘電体領域の一部を除去することにより、前記第1の半導体領域の一部を露出させ、前記第1の半導体領域の別の部分に隣接する場所に前記第1の誘電体領域の別の部分を残すことと、
前記複数のドープ領域を覆う反射防止コーティング層を提供することと、
前記第1の電極の一部を露出させることと、を更に含む、請求項1に記載の方法。 - 裏面照射画像センサデバイスを形成する方法であって、
第1の主面と反対側の第2の主面とを備える半導体基板であって、前記半導体基板は、前記第1の主面に隣接して配置された第1の誘電体領域と、前記第1の誘電体領域に隣接して配置された第1の半導体領域とを更に備え、前記第1の半導体領域は、前記第1の誘電体領域から離れた第1の面を備える、半導体基板を提供することと、
複数のドープ領域を前記第1の半導体領域内に前記第1の面に隣接して形成することと、
前記第1の面に隣接し、かつ前記複数のドープ領域の少なくとも一部に隣接する複数の導電ゲート構造であって、前記複数のドープ領域及び前記複数の導電ゲートは、ピクセル構造を備える、複数の導電ゲート構造を形成することと、
その後、前記第1の半導体領域を通って前記第1の誘電体領域へと延在する導電トレンチ構造であって、前記導電トレンチ構造は、前記第1の半導体領域から電気的に分離された導電材料を含み、前記導電材料は金属を含む、導電トレンチ構造を形成することと、
前記第1の誘電体層を覆う絶縁配線構造であって、前記トレンチ内の前記導電材料の第1の面に電気的に結合された絶縁配線構造を形成することと、
キャリア基板を前記絶縁配線構造の外面に取り付けることと、
前記半導体基板を除去し、前記第1の半導体領域に隣接する場所に前記第1の誘電体領域の少なくとも一部を残すことと、
前記第1の誘電体領域に隣接し、かつ前記トレンチ内の前記導電材料の第2の面に電気的に結合された第1の電極を形成することと、を含む、方法。 - 前記第1の複数の導電ゲート構造及び前記第1の半導体領域の前記第1の面の上方に第1の誘電体層を形成することを更に含み、前記導電トレンチ構造を形成することは、
前記第1の誘電体層及び前記第1の半導体領域を通って前記第1の誘電体領域へと延在するトレンチを形成することと、
前記トレンチの少なくとも側壁面を裏打ちする第2の誘電体層を提供することと、
前記第2の誘電体層に隣接する前記導電材料を提供することと、
前記導電材料を平らにすることと、を含む、請求項4に記載の方法。
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