CN101814474A - 线接合芯片封装结构 - Google Patents

线接合芯片封装结构 Download PDF

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Publication number
CN101814474A
CN101814474A CN200910260366A CN200910260366A CN101814474A CN 101814474 A CN101814474 A CN 101814474A CN 200910260366 A CN200910260366 A CN 200910260366A CN 200910260366 A CN200910260366 A CN 200910260366A CN 101814474 A CN101814474 A CN 101814474A
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China
Prior art keywords
chip
bare chip
wire bond
bond
semiconductor bare
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CN200910260366A
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Chinese (zh)
Inventor
谢东宪
陈南诚
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MediaTek Inc
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MediaTek Inc
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN200910260366A 2009-02-20 2009-12-17 线接合芯片封装结构 Pending CN101814474A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15401909P 2009-02-20 2009-02-20
US61/154,019 2009-02-20
US12/485,923 US20100213588A1 (en) 2009-02-20 2009-06-17 Wire bond chip package
US12/485,923 2009-06-17

Publications (1)

Publication Number Publication Date
CN101814474A true CN101814474A (zh) 2010-08-25

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CN200910260366A Pending CN101814474A (zh) 2009-02-20 2009-12-17 线接合芯片封装结构

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Country Link
US (1) US20100213588A1 (fr)
EP (1) EP2221869A3 (fr)
CN (1) CN101814474A (fr)
DE (1) DE09009506T8 (fr)
TW (1) TW201032308A (fr)

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CN102810507A (zh) * 2011-06-03 2012-12-05 新科金朋有限公司 半导体器件和使用引线框本体形成开口的方法
CN104517930A (zh) * 2013-10-04 2015-04-15 联发科技股份有限公司 半导体封装
CN105845672A (zh) * 2016-06-15 2016-08-10 南通富士通微电子股份有限公司 封装结构
CN105895541A (zh) * 2016-06-15 2016-08-24 南通富士通微电子股份有限公司 封装结构的形成方法
CN108010898A (zh) * 2017-11-02 2018-05-08 上海玮舟微电子科技有限公司 一种芯片封装结构
US10074628B2 (en) 2013-10-04 2018-09-11 Mediatek Inc. System-in-package and fabrication method thereof
US10103128B2 (en) 2013-10-04 2018-10-16 Mediatek Inc. Semiconductor package incorporating redistribution layer interposer

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DE102013202904A1 (de) * 2013-02-22 2014-08-28 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zu seiner Herstellung
US20150054099A1 (en) * 2013-08-25 2015-02-26 Kai Yun Yow Pressure sensor device and assembly method
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
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US9842820B1 (en) * 2015-12-04 2017-12-12 Altera Corporation Wafer-level fan-out wirebond packages
IT201600086488A1 (it) * 2016-08-22 2018-02-22 St Microelectronics Srl Dispositivo a semiconduttore e corrispondente procedimento
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process

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US20100213588A1 (en) 2010-08-26
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DE09009506T1 (de) 2012-09-06
EP2221869A2 (fr) 2010-08-25

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