CN101814474A - 线接合芯片封装结构 - Google Patents

线接合芯片封装结构 Download PDF

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CN101814474A
CN101814474A CN200910260366A CN200910260366A CN101814474A CN 101814474 A CN101814474 A CN 101814474A CN 200910260366 A CN200910260366 A CN 200910260366A CN 200910260366 A CN200910260366 A CN 200910260366A CN 101814474 A CN101814474 A CN 101814474A
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chip
bare chip
wire bond
bond
semiconductor bare
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谢东宪
陈南诚
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MediaTek Inc
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MediaTek Inc
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Abstract

一种线接合芯片封装结构，包含：芯片载体；半导体裸芯片，设置在该芯片载体的裸芯片依附面上，其中，多个输入/输出焊盘位于该半导体裸芯片之内或者之上；重接线层压结构，位于该重接线层压结构之上，该重接线层压结构包含多个重新分配接合焊盘；多个接合线，将该多个重新分配接合焊盘与该芯片载体互连；以及胶体，封装至少该半导体裸芯片以及该多个接合线。本发明提供的线接合芯片封装结构可解决由于裸芯片体积减小而引起的接合焊盘间距限制问题，从而提高芯片效能。

Description

线接合芯片封装结构
技术领域
本发明有关于半导体封装结构，更具体地，有关于一种线接合(wire bonding)芯片封装结构。
背景技术
如现有技术所知，通过在裸芯片(die)以及基板(substrate)上的接合点(bonding points)，而将裸芯片安置在基板上存在各种芯片(chip)封装技术，例如，球栅阵列(Ball Grid Array，BGA)、线接合、倒晶(flip-chip)等等。为了保证电子产品或者通讯装置的小型化以及多功能，半导体封装结构需要体积上尽量小、多引脚连接、高速以及高功能。
由于对更小、更快以及更便宜的电子装置不断增长的需求的驱动，半导体产业连续将价格低廉的线接合技术推进到越来越高的级别。然而，倒晶技术已经成为更高的输入/输出(I/O)焊盘数量以及更高的时钟速率的所选技术。这个趋势不仅仅可以由多数处理器所反映出来，而且，高端特殊应用集成电路(Application-Specific Integrated Circuit，ASIC)以及数字信号处理器(Digital SignalProcessor，DSP)也使用倒晶技术组装。但是，主流(mainstream)封装技术仍然是线接合，因为对于小于500I/O焊盘的装置来说，线接合的价格优势仍然明显。当倒晶装配(assembly)使高效能装置受益时，对于多数的主流应用而言，成本就成为了巨大的挑战。因此，业界仍然将主要的努力放在降低成本上。
产品成本、封装装置效能以及整体的体积决定了(interconnecting)在倒晶与线接合之间进行选择以用于IC互连，当前应用中，线接合的最大的优势在于，制造灵活以及打线机(wire bonder)的绝对数量(sheer quantity)。因此，线接合成为了已经进行了透彻研究以及被深入理解的成熟技术以及产品制造工艺。因此，打线机成为常用品，并不像用于倒晶接合的高级裸芯片依附平台，此外，线接合技术很灵活。高频应用中，新封装设计以及线长度的严格控制已经进一步扩展了线接合封装结构的电效能范围。
尽管如此，最近十年的半导体生产技术的迅速发展情况下，因为裸芯片体的体积已经迅速缩小，相似地，裸芯片上的I/O接合焊盘间距(pitch)已经达到了打线机的极限。因此，有必要在业界提供一种改进的封装结构，以将线接合技术的使用寿命延长到下一代技术节点(例如，55nm以下)，以及解决由于裸芯片体积减小而引起的接合焊盘间距限制问题。
发明内容
有鉴于此，本发明目的之一在于提供一种线接合芯片封装结构，以解决由于裸芯片体积减小而引起的接合焊盘间距限制问题。
本发明提供一种线接合芯片封装结构，包含：芯片载体；半导体裸芯片，设置在该芯片载体的裸芯片依附面上，其中，多个输入/输出焊盘位于该半导体裸芯片之内或者之上；重接线层压结构，位于该半导体裸芯片之上，该重接线层压结构包含多个重新分配接合焊盘，其中，该多个重新分配接合焊盘耦接该多个输入/输出焊盘；以及多个接合线，将该多个重新分配接合焊盘与该芯片载体互连。
本发明再提供一种线接合芯片封装结构，包含：芯片载体；半导体裸芯片，设置在该芯片载体的裸芯片依附面上，其中，多个输入/输出焊盘位于该半导体裸芯片之内或者之上；支撑结构，包围该半导体裸芯片；重接线层压结构，位于该半导体裸芯片之上，该重接线层压结构包含多个重新分配接合焊盘，其中，该多个重新分配接合焊盘耦接该多个输入/输出焊盘；以及多个接合线，将该多个重新分配接合焊盘与该芯片载体互连。
本发明目的之一在于提供一种线接合芯片封装结构，可解决由于裸芯片体积减小而引起的接合焊盘间距限制问题，从而提高芯片效能。
附图说明
图1为根据本发明的一个实施例的示例的扩散型晶圆级封装结构的原理平面图。
图2为图1中，沿着线I-I’的扩散型WLP的截面示意图。
图3为制造如图2所示的扩散型WLP的步骤的示意图。
图4为根据本发明的另一个实施例的，扩散型WLP截面示意图。
图5为根据本发明的再一个实施例的接合芯片封装结构的截面示意图。
图6为根据本发明再一个实施例的线接合芯片封装结构的截面示意图。
图7为根据本发明的再一个实施例的线接合芯片封装结构的截面示意图。
图8为根据本发明的再一个实施例的线接合芯片封装结构的截面示意图。
图9以及图10为根据本发明的截面视图的的重新分配接合焊盘的一些示意变形。
具体实施方式
在说明书及权利要求当中使用了某些词汇来指称特定组件。所属领域中技术人员应可理解，制造商可能会用不同的名词来称呼同一个组件。本说明书及权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在通篇说明书及权利要求当中所提及的“包括”和“包含”为开放式的用语，故应解释成“包含但不限定于”。以外，“耦接”一词在此包含任何直接及间接的电气连接手段。间接的电气连接手段包括通过其它装置进行连接。
相似地，装置实施例的示意图多为半原理性的，不限于图式中描述的尺寸，而且图式尺寸仅用于说明本发明，故将其夸大而显示于图式中。当揭露的多个实施例具有共同特点时，为了说明以及示意，相似的组件具有相同的标号，所属领域技术人员可以了解。所以在后续的图式中，不进行赘述。
请参阅图1以及图2。图1为根据本发明的一个实施例的示例的扩散型(fan-out type)晶圆级封装结构(Wafer Level Package，WLP，下简称其为WLP)1的平面示意图。图2为图1中，沿着线I-I’的扩散型WLP 1的截面示意图。如图1以及图2所示，扩散型WLP 1包含半导体裸芯片10，其中，半导体裸芯片10包含一个主动裸芯片面(active die face)10a以及背面(backside surface)10b。多个输入/输出焊盘12设置在半导体裸芯片10的主动裸芯片面10a上。如图1所示，多个输入/输出焊盘12可以沿着半导体裸芯片10的四边以多行(row)设置，例如，可以为三行。
当然，多个输入/输出焊盘12的行数仅用于说明本发明。例如，其它实施例中，多个输入/输出焊盘12可以排布为两行或者四行。多个输入/输出焊盘12在半导体裸芯片10的主动裸芯片面10a上，以紧密的焊盘间距，彼此接近的排布，而紧密的焊盘间距可以超出高级打线机的限制。本发明的目的之一就在于处理由于裸芯片体积缩小而产生的此问题。
如图2所示，本实施例提供支撑结构(support structure)16包围(encompass)半导体裸芯片10。较优地，支撑结构16包含胶饼(molding compound)。支撑结构16可以具有顶面16a，而顶面16a大致与主动裸芯片面10a齐平(flush)。举例说明，除了形成输入/输出焊盘12的主动裸芯片面10a，支撑结构16包围住半导体裸芯片10的其它表面。
仍然参阅图2，在主动裸芯片面10a上以及在支撑结构16的顶面16a上提供重接线层压结构(rewiring laminate structure)20。重接线层压结构20包含重布金属层(re-routed metal layer)21，而重布金属层21形成于电介质层(dielectriclayer)24中，其中电介质层24可以为例如氧化硅(silicon oxide)、氮化硅(siliconnitride)、聚亚酰胺(polyimide)、基于光敏苯并环丁烯的聚合体电介质(benzocyclobutane，BCB-based polymer dielectric)以及上述几者的组合(combination)，或者任何其它适合的材料。重布金属层21可以由铜、铝或者上述两者的组合而形成，或者其它任何适合的材料。重接线层压结构20中的重布金属层21将半导体裸芯片10之内或者之上的输入/输出焊盘12重新分配(redistribute)以在电介质层24之中或者之上形成重新分配接合焊盘(redistribution band pad)22。根据本发明的一个实施例，重新分配接合焊盘22可以由铜、铝、钛(titanium)、镍(nickel)、钒(vanadium)或者上述几者的组合而形成，或者其它任何合适的材料。输入/输出焊盘12可以由铜、铝或者上述两者的组合而形成，或者其它任何适合的材料。可以理解的是，如图2至图8所描述的重新分配接合焊盘22的截面结构，仅用于说明本发明。重新分配接合焊盘22的其它配置，只要可以耦接到输入/输出焊盘12就可以使用。举例说明，图9以及图10为根据本发明的截面视图的的重新分配接合焊盘22的一些示意变形，如图9以及图10所示的重新分配接合焊盘22的一些示意变形，可以作为如图9所示的重布金属层21的一部分，或者与图10所示其它材料的组合。
根据本发明的一个实施例，多个重新分配接合焊盘22可以排布为多行，例如，两行或者三行，多个重新分配接合焊盘22可以投射(project)在半导体裸芯片10的裸芯片侧面(die edge)10c之外(beyond)。在另一个实施例中，重新分配接合焊盘22仅有一部分投射在裸芯片侧面10c之外。而在再一个实施例中，重新分配接合焊盘22的至少一部分不投射在裸芯片侧面10c之外。在再一个实施例中，没有重新分配接合焊盘22投射在裸芯片侧面10c之外。可以理解的是，输入/输出焊盘12的行的数目可以与重新分配接合焊盘22的行的数目不同。举例说明，当重新分配接合焊盘22排布为三行时，输入/输出焊盘12可以放置成为四行。
根据本发明的另一个实施例，半导体裸芯片10可以为电源管理单元或者电源IC，其中一些排布在主动裸芯片面10a上的内侧(inner)行的电源焊盘或者接地焊盘，可以在电介质层24上，通过重接线层压结构20的方式，重新分配为重新分配接合焊盘22的多行的外侧(outer)行，或者最外侧(outmost)行。经由此操作，芯片效能就可以提高。换言之，在此发明中，焊盘就可以重新分配以适应封装以及效能要求。
图3为制造如图2所示的扩散型WLP 1的步骤的示意图。如图3所示，如第图所示的扩散型WLP 1可以通过包含晶圆切割(dicing)(步骤51)、晶圆重新配置(步骤52)、重新分配(步骤53)以及封装成型(singulation)(步骤54)的几个阶段而制造。在封装成型之后，可选择地，可实施抛光制造(polishing process)(步骤55)以去除一部分胶饼，因此可以将半导体裸芯片10的背面10b暴露出来。如果在步骤51-步骤54中，背面10b已经暴露出来的话，或者如果不希望其暴露出来的话，那么步骤55就可以省略。可以理解的是，可以使用其它方法而制造扩散型WLP。使用重新分配技术的不同的公司，使用不同的材料以及制造而实现扩散型WLP。尽管如此，所需步骤都是相似的。
重新分配层技术使用额外的步骤而扩展了传统的晶圆制造(fabrication)制造，其中，额外的步骤为将导电重布(conductive rerouting)以及互连系统沉积(deposit)到每个装置(例如，芯片，晶圆上)。扩展传统的晶圆制造工艺可以使用类似以及兼容的光刻(photolithography)以及薄膜沉积(thin film deposition)的技术而达到，其中，光刻以及薄膜沉积技术在装置制造自身中应用。额外层别的互连(additional layer of interconnection)将每个芯片的外围连接(peripheralcontact)焊盘重新分配为导电焊盘的区域阵列(area array)，而导电焊盘设置在芯片的表面。
图4为根据本发明的另一个实施例的，扩散型WLP 1a截面示意图。如图4所示，相似地，扩散型WLP 1a包含半导体裸芯片10，其中，半导体裸芯片10具有主动裸芯片面10a以及背面10b。而多个输入/输出焊盘12(例如铝接合焊盘)可以在半导体裸芯片10的主动裸芯片面10a上提供。输入/输出焊盘12可以沿着半导体裸芯片10的4个裸芯片侧面10c而设置。
本实施例提供支撑结构16包围半导体裸芯片10。较优地，支撑结构16可以包含具有较好的机械强度以及与半导体裸芯片10间优良的粘结(adhesion)力的胶饼。支撑结构16可以具有顶面16a，而顶面16a大致与主动裸芯片面10a齐平。在此实施例中，支撑结构16仅覆盖半导体裸芯片10的裸芯片侧面10c。支撑结构16不包围背面10b，背面10b暴露出来。
相似地，在主动裸芯片面10a以及支撑结构16的顶面16a上提供重接线层压结构20，重接线层压结构20包含重布金属层21，而重布金属层21形成在电介质层24上。重接线层压结构20中的重布金属层21将半导体裸芯片10之内或者之上的多个输入/输出焊盘12重新分配，以在电介质层24中或者电介质层24上形成重新分配接合焊盘22。
图5为根据本发明的再一个实施例的接合芯片封装结构100的截面示意图。如图5所示，具有主动裸芯片面10a以及裸芯片侧面10c的半导体裸芯片10，设置在芯片载体(chip carrier)40的裸芯片依附面(attach surface)40a上，其中，芯片载体40可以为例如封装基板或者印刷电路板，其中，多个输入/输出焊盘12位于半导体裸芯片10上。支撑结构16可以包围半导体裸芯片10。而支撑结构16具有顶面16a，而顶面16a大致与主动裸芯片面10a齐平。
半导体裸芯片10上提供重接线层压结构20，重接线层压结构20包含多个重新分配接合焊盘22，而多个重新分配接合焊盘22可以投射在裸芯片侧面10c之外，或者不投射在裸芯片侧面10c之外。使用多个接合线(bond wire)50将重新分配接合焊盘22与芯片载体40上的对应的接合焊盘42互连起来。提供胶体(mold cap)60以封装(encapsulate)至少半导体裸芯片10、重接线层压结构20、支撑结构16以及接合线50。根据此实施例，胶体60以及支撑结构16可以由不同的胶饼制成。
根据此实施例，接合线50可以包含金、铜或者上述两者的组合，或者其它适合的材料。换言之，接合线50可以为金线、铜线，或者上述两者的组合，或者其它适合的材料。根据本发明的一个实施例，重新分配接合焊盘22由铜形成，而接合线50为铜线。
既然半导体裸芯片10上具有紧密焊盘间距的输入/输出焊盘12重新分配在外围(peripheral)，投射在裸芯片侧面10c之外的外侧区域(outer area)，重新分配接合焊盘22因此具有用于线接合应用的宽松的焊盘间距。尽管如此，如前所述，重新分配接合焊盘22可以投射在裸芯片侧面10c之外，或者不投射在裸芯片侧面10c之外，依赖于设计要求。
图6为根据本发明再一个实施例的线接合芯片封装结构100a的截面示意图。如图6所示，扩散型WLP 1a，经由粘结层(adhesive layer)152，设置在芯片载体(例如，在此实施例中，芯片载体为引线框架140)的裸芯片依附面或者裸芯片焊盘140a，其中多个输入/输出焊盘12位于半导体裸芯片10上。扩散型WLP 1a包含支撑结构16，而支撑结构16包围半导体裸芯片10。支撑结构16具有顶面16a，而顶面16a大致与主动裸芯片面10a齐平。
扩散型WLP 1a进一步包含重接线层压结构20，而重接线层压结构20在半导体裸芯片10上以及支撑结构16的顶面16a上制造。重接线层压结构20可以在封装厂(assembly house)制造。重接线层压结构20包含多个重新分配接合焊盘22，而多个重新分配接合焊盘22可以投射在裸芯片侧面10c之外，而重新分配接合焊盘22可以具有用于线接合应用的宽松的焊盘间距。在另一实施例中，依赖于设计要求，重新分配接合焊盘22不投射在裸芯片侧面10c之外，或者仅重新分配接合焊盘22的一部分投射在裸芯片侧面10c之外。在再一个实施例中，至少重新分配接合焊盘22的一部分不投射在裸芯片侧面10c之外。
使用多个接合线50将重新分配接合焊盘22与引线框架140的对应内侧引脚(inner lead)142互连起来。提供胶体60封装至少半导体裸芯片10、裸芯片焊盘140a、内侧引脚142以及接合线50。根据此实施例，接合线50可以包含金、铜，或者上述二者的组合，或者其它适合的材料。
图7为根据本发明的再一个实施例的线接合芯片封装结构100b的截面示意图。如图7所示，包含半导体裸芯片10的扩散型WLP 1a，通过粘结层152，设置在引线框架140的裸芯片焊盘140a上，而半导体裸芯片10具有主动裸芯片面10a以及裸芯片侧面10c，其中，多个输入/输出焊盘12位于半导体裸芯片10内或者上。支撑结构16可以具有顶面16a，而顶面16a大致上与主动裸芯片面10a齐平。扩散型WLP 1a进一步包含重接线层压结构20，而重接线层压结构20在半导体裸芯片10以及支撑结构16的顶面16a上提供。相似地，重接线层压结构20包含多个重新分配接合焊盘22，而多个重新分配接合焊盘22可以投射在裸芯片侧面10c之外，或者不投射在裸芯片侧面10c之外。
多个接合线50用于将重新分配接合焊盘22与引线框架140的内侧引脚142互连起来。接合线50可以包含金、铜、或者上述二者的组合，或者其它适合的材料。可以提供胶体60封装至少半导体裸芯片10、重接线层压结构20、支撑结构16、内侧引脚142以及接合线50。根据此实施例，裸芯片焊盘140a的底面140b不由胶体60包围，因此，可以外露于空气中。这样的封装结构可以称之为外露式焊盘(Exposed-Pad，E-pad)薄型四边引脚扁平封装结构(Low-ProfileQuad Flat Package，LQFP)。
图8为根据本发明的再一个实施例的线接合芯片封装结构100c的截面示意图。如图8所示，包含半导体裸芯片10的扩散型WLP 1a，设置在引线框架240的裸芯片焊盘240a上，而半导体裸芯片10具有主动裸芯片面10a以及裸芯片侧面10c，其中，多个输入/输出焊盘12位于半导体裸芯片10内或者上。裸芯片焊盘240a进一步可以包含凹腔(recess)240c，而半导体裸芯片10可以设置在凹腔240c内。扩散型WLP 1a可以包含支撑结构16，而支撑结构16包围半导体裸芯片10。支撑结构16可以具有顶面16a，而顶面16a大致上与主动裸芯片面10a齐平。扩散型WLP 1a进一步包含重接线层压结构20，而重接线层压结构20在半导体裸芯片10以及支撑结构16的顶面16a上提供。相似地，重接线层压结构20包含多个重新分配接合焊盘22，而多个重新分配接合焊盘22可以投射在裸芯片侧面10c之外，或者不投射在裸芯片侧面10c之外。
多个接合线50用于将重新分配接合焊盘22与引线框架240的引线框架互连焊盘242互连起来。接合线50可以包含金、铜、或者上述二者的组合，或者其它适合的材料。可以提供胶体60封装至少半导体裸芯片10、重接线层压结构20、支撑结构16、引线框架240的上部、互连焊盘242的上部以及接合线50。如图8所示的封装结构配置可以称之为四方扁平无引脚(quad flat non-leaded，QFN)封装结构或者先进四方扁平无引脚(advanced quad flat non-leaded，aQFN)封装结构。
在其它实施例中，如图2、图4至图10所示的支撑结构16可以省略。在其它实施例中，在半导体裸芯片10上可以具有另一个半导体裸芯片。另一个半导体裸芯片可以经由至少一个接合线而耦接到半导体裸芯片10。在其它实施例中，另一个半导体裸芯片可以耦接到半导体裸芯片10的重新分配接合焊盘22，而上述半导体裸芯片10不投射到裸芯片侧面10c之外。
任何本领域技术人员，在不脱离本发明的精神和范围内，当可做些许的更动与润饰，因此本发明的保护范围当视所附权利要求所界定者为准。

Claims (18)

1.一种线接合芯片封装结构，包含：
芯片载体；
半导体裸芯片，设置在该芯片载体的裸芯片依附面上，其中，多个输入/输出焊盘位于该半导体裸芯片之内或者之上；
重接线层压结构，位于该半导体裸芯片之上，该重接线层压结构包含多个重新分配接合焊盘，其中，该多个重新分配接合焊盘耦接该多个输入/输出焊盘；以及
多个接合线，将该多个重新分配接合焊盘与该芯片载体互连。
2.如权利要求1所述的线接合芯片封装结构，其特征在于，进一步包括胶体，该胶体封装至少该半导体裸芯片以及该多个接合线。
3.如权利要求1所述的线接合芯片封装结构，其特征在于，该芯片载体为封装基板或印刷电路板或引线框架。
4.如权利要求3所述的线接合芯片封装结构，其特征在于，该线接合芯片封装结构为薄型四边引脚扁平封装结构或者四方扁平无引脚封装结构。
5.如权利要求1所述的线接合芯片封装结构，其特征在于，该多个接合线为金线或者铜线。
6.如权利要求1所述的线接合芯片封装结构，其特征在于，该多个重新分配接合焊盘至少一者投射在该半导体裸芯片的裸芯片侧面之外。
7.一种线接合芯片封装结构，包含：
芯片载体；
半导体裸芯片，设置在该芯片载体的裸芯片依附面上，其中，多个输入/输出焊盘位于该半导体裸芯片之内或者之上；
支撑结构，包围该半导体裸芯片；
重接线层压结构，位于该半导体裸芯片之上，该重接线层压结构包含多个重新分配接合焊盘，其中，该多个重新分配接合焊盘耦接该多个输入/输出焊盘；以及
多个接合线，将该多个重新分配接合焊盘与该芯片载体互连。
8.如权利要求7所述的线接合芯片封装结构，其特征在于，该半导体裸芯片具有主动裸芯片面，该支撑结构的顶面与该主动裸芯片面齐平。
9.如权利要求8所述的线接合芯片封装结构，其特征在于，该重接线层压结构也形成于该支撑结构的该顶面之上。
10.如权利要求7所述的线接合芯片封装结构，其特征在于，该芯片载体为封装基板或印刷电路板。
11.如权利要求7所述的线接合芯片封装结构，其特征在于，该多个输入/输入焊盘的材料为铜、铝或者上述二者的组合。
12.如权利要求7所述的线接合芯片封装结构，其特征在于，该重新分配焊盘的材料包含铜、铝、钛、镍、钒，或者上述几者的组合。
13.如权利要求12所述的线接合芯片封装结构，其特征在于，该多个接合线为铜线。
14.如权利要求7所述的线接合芯片封装，其特征在于，进一步包括胶体，该胶体封装至少该半导体裸芯片、该重接线层压结构、该支撑结构以及该多个接合线。
15.如权利要求14所述的线接合芯片封装结构，其特征在于，该支撑结构与该胶体由不同的胶饼形成。
16.如权利要求7所述的线接合芯片封装结构，其特征在于，该芯片载体为引线框架。
17.如权利要求16所述的线接合芯片封装结构，其特征在于，该线接合芯片封装结构为薄型四边引脚扁平封装结构或四方扁平无引脚封装结构。
18.如权利要求7所述的线接合芯片封装结构，其特征在于，该多个重新分配接合焊盘至少一者投射在该半导体裸芯片的裸芯片侧面之外。
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