CN101800209B - 具有凹涡结构导线架的倒装半导体组件封装 - Google Patents

具有凹涡结构导线架的倒装半导体组件封装 Download PDF

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CN101800209B
CN101800209B CN2010101218674A CN201010121867A CN101800209B CN 101800209 B CN101800209 B CN 101800209B CN 2010101218674 A CN2010101218674 A CN 2010101218674A CN 201010121867 A CN201010121867 A CN 201010121867A CN 101800209 B CN101800209 B CN 101800209B
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lead frame
semiconductor
grid
recessed whirlpool
flip chip
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CN101800209A (zh
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孙明
龚德梅
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Chongqing Wanguo Semiconductor Technology Co ltd
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Abstract

本发明公开一种具有凹涡结构导线架的倒装半导体组件封装，该组件封装包括：具有若干源极凹涡和一个栅极凹涡的导线架；一个具有分别相对应于导线架源极凹涡和栅极凹涡的若干源极接触窗区域和栅极接触窗区域的半导体晶粒，该半导体晶粒倒装于导线架上，因此，固化的导电环氧层为若干源极接触窗区域与源极凹涡和若干栅极接触窗区域与栅极凹涡之间提供了电连接和机械连接。本发明降低了半导体倒装封装的成本，有效地降低在具有凹涡的导线架与印刷电路板之间的热膨胀错位。此外，由于提供了较大的连接面积给主机板级封装，因此，可改善组件的可靠度、热性能与电性能。

Description

具有凹涡结构导线架的倒装半导体组件封装
本案是分案申请
原案发明名称：制造倒装于半导体组件封装的晶圆级无凸块式方法
原案国际申请号：PCT/US2006/022314
原案国家申请号：200680018779.3
原案国际申请日：2006年6月9日
技术领域
本发明涉及一种半导体组件的制作方法，特别涉及一种制造倒装于半导体组件封装的晶圆级无凸块式方法。
背景技术
现有技术的倒装方法为在基板上将一具有凸块的半导体晶粒连接至焊盘布局上，此凸块可由锡和金所构成，且其先形成在半导体晶粒的导电焊垫上，而后再利用加热与加压的方式使凸块在半导体晶粒与基板之间形成相互连接，而依据不同的需求，可将具有流动性的物质应用在介于半导体晶粒与基板之间的凹洞中，以改善半导体晶粒与基板之间的机械连接。
现有的倒装技术已使用来制造封装于导线架上的低接脚半导体组件中，如美国专利第5,817,540号中所公开的方法，一般而言，其包括覆装一晶粒于导线架上，并由凸块作为内连接。而硅晶圆片可为预先形成凸块并先经过切割。经由分离的晶粒，可直接将具有凸块的晶粒覆装于相应的导线架上。利用锡回焊来连接晶粒与导线架。当锡凸块未被用作内连接时，可使用导电涂料或是导电填充环氧树脂以取代。在晶粒与导电架连接后，可使用一介电层或是一垫料材料覆盖在晶粒与导电架之间的沟槽中，以避免短路并可提供晶粒与导电架之间的附着力。
现有的倒装技术的缺点是由于必须对半导体晶粒施以凸块制成而提高了成本。而且，当半导体晶粒的接触焊垫由铝构成时，则必须再形成一凸块底层金属化层以促进焊锡或是其他键结材料的使用，然而，凸块底层金属化层的使用，则又将耗费额外的半导体封装制造过程成本。
因此需要半导体组件倒装封装的晶圆级无凸块制成方法以可克服现有技术中的缺点。较好的晶圆级无凸块制造过程方法可在提供较佳的主机板级封装的可靠度的同时，降低半导体组件倒装封装的成本。此外，晶圆级无凸块制造过程方法可使进行主机板级封装时的导线架与印刷电路板之间具有较小的热膨胀错位，且提供一较大的连接面积。
发明内容
本发明的主要目的，提出一种制造倒装于半导体组件封装的晶圆级无凸块式方法，包括提供一具有凹涡结构的导线架，其具有源极与栅极凹涡，此具有凹涡结构的导线架可由导电环氧树脂以帖附于半导体组件，并且利用导电环氧树脂以同时提供电连接与机械连接。该连接可通过晶圆级的制造过程以实现，再将晶圆片切割成为独立的晶粒以供为主机级封装之用，例如：表面安装。
本发明的另一个目的，提出一种制造倒装于半导体组件封装的晶圆级无凸块式方法，其包括数个对一半导体晶粒的晶圆片前侧表面进行防焊漆涂布的步骤，其先进行防焊涂布以形成若干个栅极接触窗与若干个源极接触窗，并利用目标凹涡区域以对一导电架进行图案化，且在导线架上相对应于栅极接触窗与源极接触窗的位置上，以形成凹涡，将导线架上的凹涡通过印刷方式生成导电环氧树脂，并将导电架帖附在半导体晶粒的晶圆上、固化导线架与半导体晶粒晶圆，最终，切割导线架和半导体晶粒晶圆片，从而完成一半导体组件的封装。
本发明的另一个目的，提出一种制造倒装于半导体组件封装的晶圆级无凸块式方法，其包括在一半导体晶粒的晶圆片的前侧表面上制造出若干个栅极接触窗与若干个源极接触窗，并在导线架上相对应于若干栅极接触窗与若干源极接触窗的位置上形成凹涡，其中上述的栅极接触窗与源极接触窗连接在导线架与半导体晶粒晶圆片之间，最后，切割半导体晶粒晶圆片而完成一半导体组件的封装。
为了使下文有关于本发明的描述更加容易明白，也为了使本发明对于现有技术的贡献更加容易了解，上述仅仅概括性地且相当广泛地提供了本发明的特征，以下将提供更多有关本发明的特征。
有鉴于此，在进行实施方式的说明之前，应当了解本发明并不受限于用以描述其应用的架构中，且凡是利用以下所述或是附图中的任意组件的重组与排列而得到的应用，都当视做落入于本发明的保护范围中。而除了本说明书中所提供的实施例外，本发明也可由其它各种不同的实施例加以实现，因此，本发明的措词、学术用语、摘要都仅仅是用来解释本发明，而非限定本发明的保护范围。
因此，本领域的技术人员可通过本发明的公开而能了解本发明的内容并加以实施，而且，权利要求书应视为本发明的等效架构，且并未脱离本发明的实质范围。
参考以下附图、具体实施方式和权利要求，本发明的以上和其他特征、目的和优点将更加容易理解。
附图说明
图1为本发明的半导体组件封装结构晶片级L/F封装的截面剖视图；
图2为本发明的具有凹涡的晶片级引线框架的俯视图；
图3为本发明的具有凹涡的晶片级引线框架的俯视图；
图4为制造本发明的倒装半导体组件封装的流程图；
图5为图4的制造倒装半导体组件封装的预定图表的示意图。
具体实施方式
本发明提供一种制造倒装于半导体组件封装的晶圆级无凸块式方法，其包括提供一具有凹涡结构的导线架，此导线架上具有源极与栅极凹涡，且此源极与栅极凹涡结构可通过环氧树脂将导线架连接到半导体组件上，从而提供电连接与机械连接，所述连接可在晶圆级制造过程下进行，随后再把上述的晶圆片切割形成单独的晶粒以供主机板级封装使用，例如：表面封装。
如图1所示，是本发明的倒装半导体组件封装100，此半导体组件封装100由本发明公开的一种晶圆级制造过程来形成。半导体晶粒110可包括一保护性的环氧树脂层115，其采用现有技术印刷且固化在一漏极的后侧表面。利用现有技术将一防焊漆120涂布或曝光或剥离形成在一半导体晶粒110的栅极/源极的前侧表面上，从而暴露栅极与源极接触窗焊垫(未绘示于图中)；而在导线架135与半导体晶粒110相互连接之前，可通过模印(stamping)制造过程在导线架135上形成凹涡130，且此凹涡130的位置与栅极接触窗焊垫、源极接触窗焊垫对准。
环氧树脂140可印刷在导线架135上以提供导线架135与半导体晶粒110之间的电连接与机械连接，而在半导体晶粒110黏附于导线架135后进行环氧树脂140的固化，将晶圆片进行切割后，利用焊料155并通过焊接的方式使得半导体晶粒110与印刷电路板150连接。
如图2所示，是一典型的导电架135，其上印刷有图案用以准备形成凹涡。若干源极凹涡200与栅极凹涡210通过图案化形成在导线架135上，可利用一般惯用的模印或是压印方法在导线架135上形成源极凹涡200与栅极凹涡210。如图3中所示，是一经过图案化的晶圆级硅芯片300。
如图4所示，其中，一制造倒装于半导体组件封装的晶圆级无凸块方法400包括：在步骤410中，一保护性后侧表面环氧树脂115可涂布到形成在硅芯片上的半导体晶粒上，并且经过烘烤固化；在步骤420中，进行防焊漆涂布120的涂布；在步骤430中，防焊漆涂布120进行曝光和/或剥离生成栅极与源极接触窗焊垫。
在步骤440中，导线架135可经过图案化且形成凹涡，在步骤450中，环氧树脂140可印刷在导线架135上，在步骤460中，导线架135与半导体晶粒110可相互黏附并且经过烘烤固化的制造过程，在进行完毕固化的制造过程后，于步骤470中，硅芯片可进行切割以得到单独的半导体组件封装100，并在步骤480中，此半导体组件封装100可固定封装在一印刷电路板上。而步骤410至步骤480的每一流程中所对应的结构示意图，如图5所示。
本发明所提供的制造倒装于半导体组件封装的晶圆级无凸块式方法无须再将半导体晶粒进行凸块的制造过程，也因此降低了半导体倒装封装的成本。与现有技术中的倒装技术相比，常见的热膨胀所造成的错位及因此错位而导致在接点上产生的机械性缺失，而在本发明中，可有效地降低在具有凹涡的导线架与印刷电路板之间的热膨胀错位。此外，由于提供了较大的连接面积给主机板级封装，因此，可改善组件的可靠度、热性能与电性能。
本发明所公开的方法不需包括主机板级芯片尺寸封装(board level chipscale package)；也无须使用额外施加的外力或是热超音波将凸块连接到晶粒的主动区域上，也因此，本发明所提供的方法可由降低部件的损失进而提升产率；最后，本发明所提供的方法较现有技术的方法为简单，且可被封装测试厂接受，从而降低了倒装技术的成本。
以上所述由实施例说明本发明的特点，其目的在使本领域的技术人员能了解本发明的内容并据以实施，而非限定本发明的权利要求的保护范围，故，凡是其它未脱离本发明所公开的精神所完成的等效修饰或修改，仍应包含在权利要求的范围中。

Claims (4)

1.一种倒装半导体组件封装，包括：
具有若干源极凹涡和若干栅极凹涡的导线架；
一个具有分别相对应于导线架源极凹涡和栅极凹涡的若干源极接触窗区域和栅极接触窗区域的半导体晶粒，该半导体晶粒倒装于导线架上，因此，固化的导电环氧层为若干源极接触窗区域与源极凹涡和若干栅极接触窗区域与栅极凹涡之间提供了电连接和机械连接；
该些源极接触窗区域和栅极接触窗区域通过晶粒前侧表面上的防焊漆制造过程形成。
2.如权利要求1所述的半导体组件封装，其特征在于，该组件后侧表面包含一个保护性的环氧树脂层。
3.如权利要求1所述的半导体组件封装，其特征在于，所述源极凹涡和栅极凹涡通过模印导线架制造过程实现。
4.如权利要求1所述的半导体组件封装，其特征在于，该些源极凹涡和栅极凹涡通过压印导线架制造过程实现。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100688560B1 (ko) * 2005-07-22 2007-03-02 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 그 제조 방법
TWI422058B (zh) * 2008-03-04 2014-01-01 Everlight Electronics Co Ltd 發光二極體封裝結構與其製造方法
CN102222627B (zh) * 2010-04-14 2013-11-06 万国半导体(开曼)股份有限公司 具有晶圆尺寸贴片的封装方法
TWI466199B (zh) * 2010-04-14 2014-12-21 Alpha & Omega Semiconductor Cayman Ltd 具有晶圓尺寸貼片的封裝方法
US8970032B2 (en) 2011-09-21 2015-03-03 Infineon Technologies Ag Chip module and method for fabricating a chip module
US20130294042A1 (en) * 2012-05-07 2013-11-07 Guo-Quan Lu Methods and apparatus for connecting planar power electronics devices
CN104756225A (zh) * 2012-09-20 2015-07-01 斯莱戈科技公司 极薄封装
DE102013200868B4 (de) * 2013-01-21 2016-05-12 Infineon Technologies Ag Verfahren zur Herstellung einer stoffschlüssigen Verbindung und einer elektrischen Verbindung
US9741642B1 (en) * 2014-05-07 2017-08-22 UTAC Headquarters Pte. Ltd. Semiconductor package with partial plating on contact side surfaces
CN104465586B (zh) * 2014-12-26 2018-07-10 江苏长电科技股份有限公司 一种圆片级封装结构及其工艺方法
CN104538378A (zh) * 2014-12-26 2015-04-22 江苏长电科技股份有限公司 一种圆片级封装结构及其工艺方法
KR20190052957A (ko) * 2017-11-09 2019-05-17 에스케이하이닉스 주식회사 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지
CN112701091A (zh) * 2020-12-22 2021-04-23 杰群电子科技（东莞）有限公司 一种内埋元件的封装结构及封装方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926694A (en) * 1996-07-11 1999-07-20 Pfu Limited Semiconductor device and a manufacturing method thereof
CN1543675A (zh) * 2000-12-15 2004-11-03 ض� 具有无凸块的叠片互连层的微电子组件

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06209054A (ja) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp 半導体装置
JP2859194B2 (ja) * 1996-01-30 1999-02-17 九州日本電気株式会社 プラスチックパッケージ型半導体集積回路及びその製造 方法
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
US6256200B1 (en) * 1999-05-27 2001-07-03 Allen K. Lam Symmetrical package for semiconductor die
US6329714B1 (en) * 1999-11-01 2001-12-11 General Semiconductor, Inc. Hybrid S.C. devices and method of manufacture thereof
US6294409B1 (en) * 2000-01-27 2001-09-25 Siliconware Precisionware Industries Co., Ltd. Method of forming a constricted-mouth dimple structure on a leadframe die pad
US6989588B2 (en) * 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US20020030276A1 (en) * 2000-04-27 2002-03-14 Guo-Quan Lu Dimple array interconnect technique for semiconductor device
US6645791B2 (en) * 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
US20050035441A1 (en) * 2003-08-15 2005-02-17 Kwanghak Lee Integrated circuit stack with partially etched lead frames
US20050121806A1 (en) * 2003-12-04 2005-06-09 White Electronic Designs Corporation Method for attaching circuit elements
JP3858902B2 (ja) * 2004-03-03 2006-12-20 住友電気工業株式会社 導電性銀ペーストおよびその製造方法
WO2006020744A2 (en) * 2004-08-12 2006-02-23 Tessera, Inc. Structure and method of forming capped chips
US7238602B2 (en) * 2004-10-26 2007-07-03 Advanced Chip Engineering Technology Inc. Chip-size package structure and method of the same
US7238551B2 (en) * 2004-11-23 2007-07-03 Siliconix Incorporated Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926694A (en) * 1996-07-11 1999-07-20 Pfu Limited Semiconductor device and a manufacturing method thereof
CN1543675A (zh) * 2000-12-15 2004-11-03 ض� 具有无凸块的叠片互连层的微电子组件

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