CN101714533B - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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Publication number
CN101714533B
CN101714533B CN2009101780974A CN200910178097A CN101714533B CN 101714533 B CN101714533 B CN 101714533B CN 2009101780974 A CN2009101780974 A CN 2009101780974A CN 200910178097 A CN200910178097 A CN 200910178097A CN 101714533 B CN101714533 B CN 101714533B
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China
Prior art keywords
mentioned
sealing resin
circuit arrangement
filler
resin
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CN2009101780974A
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CN101714533A (zh
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中里功
吉羽茂治
关端隆
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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Abstract

本发明提供一种防止看到金属细线且为薄型的电路装置及其制造方法。电路装置(10)主要包括：基板，其由第1基板(12)和第2基板(14)构成；焊盘(34)，其形成在第2基板的上表面上；半导体元件(24)，其被固定在第1基板(12)的上表面上；金属细线(22)，其将半导体元件(24)和焊盘(34)连接起来；以及密封树脂(18)，其覆盖半导体元件(24)和金属细线(22)来进行树脂密封。并且，密封树脂(18)所包含的位于最表层的填料(20)被构成密封树脂(18)的树脂材料覆盖。

Description

电路装置及其制造方法
技术领域
本发明涉及一种半导体元件被混入有填料的密封树脂薄薄地覆盖的电路装置及其制造方法。
背景技术
电路装置的制造工序大致分为将期望的元件组装在一片半导体晶圆的表面上的前工序和对分割半导体晶圆而得到的半导体元件进行封装的后工序。近年来，正在开发如下制造方法：在一次密封工序中利用树脂密封多个电路装置，通过切割对密封后的树脂密封体进行分割来得到各电路装置(参照下面所述的专利文献1)。
参照图8，说明上述电路装置的制造方法。图8的各图为表示各工序的剖视图。
参照图8的(A)，首先，在基板100的上表面配置构成多个电路装置的导电图案102和半导体元件106。基板100由陶瓷或树脂材料构成，在基板100的上表面形成有多个导电图案102。在此，作为一个电路装置的单元108由多个导电图案102构成。并且，各单元108的导电图案102上固定有半导体元件106，半导体元件106的电极和导电图案102经由金属细线104连接起来。
参照图8的(B)，以覆盖多个单元108的方式在基板100的上表面涂敷密封树脂110。密封树脂110由填充了包括二氧化硅(SiO2)等粒状填料的树脂构成，以液态或者半固态的状态供给到基板100的上表面之后被固化。
下面，参照图8的(C)，对密封树脂110的上表面进行磨削，由此，使密封树脂110变薄，并且，使密封树脂110的上表面平坦化。
下面，参照图8的(D)，在各单元108的边界通过切割分割密封树脂110和基板100，得到分别独立的电路装置。
通过上述工序，由于一次性地制造多个电路装置，因此，具有提高电路装置的生产率的优点。
专利文献1：日本特开2000-164609号公报
然而，在上述制造方法中，存在如下问题：当为了使所制造的电路装置成为薄型而使图8的(C)所示的密封树脂110的厚度变薄时，有可能从外侧透过覆盖树脂110看到金属细线104等。
具体地说，进行树脂密封所使用的密封树脂110由填充了填料(由二氧化硅等构成)的树脂材料构成。并且，二氧化硅是一种容易透过光的透明材料。因而，如果磨削密封树脂110的上表面而使覆盖金属细线104的密封树脂110的厚度变薄为50μm左右，则来自外部的光容易经由填料到达金属细线104。
图9是拍摄以往类型的电路装置的截面的图像，拍摄有金属细线104以及覆盖金属细线的密封树脂110。在该图像中，用虚线表示密封树脂110的上表面，用白色的椭圆标示出一部分从密封树脂110的上表面露出到外部的填料。
参照该图像，覆盖金属细线104的密封树脂110的厚度为例如50μm左右，该厚度有可能比填料的直径小。当形成该厚度时，金属细线104出现仅由填料而不是由树脂材料覆盖的部位。并且，由于填料为比树脂材料更透明的材料，因此，来自外部的光容易经由填料到达金属细线104，其结果从外侧能够看到金属细线104。这样，如果从外侧看到金属细线104则会使外观变差。
发明内容
本发明是鉴于上述问题而完成的，本发明的目的在于提供一种防止看到金属细线并形成薄型的电路装置及其制造方法。
本发明的电路装置，其特征在于，包括：半导体元件；导电部件，其经由金属细线与上述半导体元件相连接；以及密封树脂，其由混入了填料的树脂材料构成，用于对上述半导体元件和上述金属细线进行树脂密封，使覆盖上述金属细线的最顶部的上述密封树脂的厚度比上述填料的最大直径小，并且位于最表层的上述填料被上述树脂材料覆盖。
本发明的电路装置的制造方法，其特征在于，包括如下工序：经由金属细线将形成在半导体元件的上表面上的电极和导电部件连接起来的工序，以及通过使用了注塑模具的注塑成形，用密封树脂覆盖上述半导体元件和上述金属细线的工序，该密封树脂由混入了填料的树脂材料构成，在进行覆盖的工序中，使覆盖上述金属细线的最顶部的上述密封树脂的厚度比上述填料的最大直径小，位于最表层的上述填料被上述树脂材料覆盖。
根据本发明，使覆盖金属细线的最顶部的密封树脂的厚度比密封树脂所包含的填料的最大直径小，并且，位于最表层的填料被树脂覆盖。因此，由于透明的填料没有露出到外部，能够抑制从外侧看到金属细线的不良情况。
附图说明
图1是表示本发明的电路装置的图，(A)为剖视图，(B)为放大后的剖视图，(C)为拍摄电路装置的截面而得到的图像。
图2是表示本发明的电路装置的图，(A)为立体图，(B)和(C)为放大后的剖视图。
图3是表示本发明的电路装置的制造方法的图，(A)为俯视图，(B)和(C)为剖视图。
图4是表示本发明的电路装置的制造方法的图，(A)和(B)为剖视图。
图5是表示本发明的电路装置的制造方法的图，(A)为剖视图，(B)为俯视图，(C)为放大后的剖视图。
图6是表示本发明的电路装置的制造方法的图，(A)为俯视图，(B)为放大后的剖视图。
图7是表示本发明的电路装置的制造方法的剖视图。
图8的(A)至(D)是表示背景技术的电路装置的制造方法的剖视图。
图9是拍摄背景技术的电路装置而得到的图像。
具体实施方式
参照图1，说明本实施方式的电路装置10的结构。图1的(A)为表示电路装置10的剖视图，图1的(B)为局部放大剖视图，图1的(C)为拍摄实际制造的电路装置10的截面而得到的图像。
参照图1的(A)，电路装置10主要包括：基板，其由第1基板12和第2基板14构成；焊盘34，其形成在第2基板14的上表面上；半导体元件24，其被固定在第1基板12的上表面上；金属细线22，其将半导体元件24和焊盘34连接起来；以及密封树脂18，其覆盖半导体元件24和金属细线22来进行树脂密封。
第1基板12是由陶瓷或者树脂材料等绝缘材料构成的基板。第1基板12的平面尺寸为稍微大于半导体元件24的程度，厚度为例如100μm左右。电路装置10的下部的左右端部通过切割形成为矩形状。另外，在第1基板12的下表面形成有由铜箔等构成的外部电极36，安装电路装置10时，在外部电极36上熔敷焊锡等导电性粘结材料后进行面安装。
第2基板14被层叠在第1基板12的上表面两端，在上表面形成有焊盘34。另外，第2基板14的材料和厚度与第1基板12相同即可。在形成在第2基板14的上表面的焊盘34上连接有由金或铝构成的金属细线22。
另外，形成在第2基板14的上表面上的焊盘34和设置在第1基板12的下表面上的外部电极36经由连续贯穿两基板设置的通孔16而被连接。金或铜等导电材料被埋入该通孔16中，另外，在基板上将包含钨等的导电浆(paste)形成为规定形状，通过镀金膜覆盖该导电浆来形成设置在第2基板14上的焊盘34、设置在第1基板12上的外部电极36。
半导体元件24是MOSFET或双极性晶体管等的分立的晶体管或者IC等。半导体元件24的下表面通过焊锡等导电性粘结材料或绝缘性粘结材料被固定在第1基板12的上表面上。在此，在第1基板12上安装有一个半导体元件24，但是，也可以在第1基板12的上表面固定有多个元件。另外，也可以在第1基板12的上表面设置岛(island)，在该岛的上表面安装半导体元件24。
金属细线22是由金或铝构成的直径为10μm左右的细线，用于将设在半导体元件24的上表面上的电极和设置在第2基板14的上表面上的焊盘34电连接。在本实施方式中，金属细线22的形状一部分呈弯曲状，剩余的部分呈直线状。具体地说，金属细线22所连接的端部附近的金属细线22为呈圆或者椭圆的一部分的形状，该部分包括金属细线的顶部。另外，金属细线22的呈弯曲的部分在引线接合的工序中进行加热而被重结晶，由此，变为高硬度，金属细线22呈直线状的部分为比较低的硬度。这样，与金属细线22被形成为同样地弯曲的情况相比，能够使金属细线22的顶部的位置比较低，其结果是能够使装置整体形成为薄型。
密封树脂18由混入了填料的树脂材料构成。作为填料，例如采用球状的二氧化硅，填料的最大粒径为例如55μm左右。在密封树脂18中混入填料的比例以体积百分比计为例如70％左右。另外，作为密封树脂18所包含的树脂材料也可以是环氧树脂等热固性树脂，也可以是热塑性树脂。在本实施方式中，填料20基本不露出到电路装置10的上表面，由密封树脂18所包含的树脂材料构成电路装置10的上表面。
参照图1的(B)，覆盖金属细线22的最顶部的密封树脂18的厚度小于密封树脂18所包含的填料20的最大粒径。具体地说，例如在作为球状的填料20的最大粒径如上所述为55μm的情况下，覆盖金属细线22的密封树脂18的厚度T2为40μm左右。并且，位于密封树脂18的最表层的填料20被树脂材料覆盖，该覆盖厚度T1为例如8μm左右。即、在本实施方式中，位于密封树脂18的上表面附近的填料20被树脂材料覆盖，填料20不会从上表面露出到外部。
在本实施方式中，为了使电路装置10薄型化，尽可能使覆盖半导体元件24的密封树脂18的厚度变薄。然而，当密封树脂18的厚度变薄时，光透过密封树脂18所包含的填料，有可能从外部看到金属细线22、焊盘34。为了防止从外面被看到，在本实施方式中，利用至少比填料20遮光性优异的树脂材料覆盖位于最表层的填料20。这样，通过覆盖填料20的树脂材料遮挡从外部入射的光，降低从外部入射到填料20的光。其结果，抑制了金属细线22、焊盘34被看到。此外，还具有如下优点：填料20不会从密封树脂18露出到外部，由此，由于填料20和树脂材料的边界不从上表面露出到外部，因此，也提高了耐压性。
并且，在本实施方式中，密封树脂18的上表面被设为形成了微细凹凸的梨皮状表面(梨皮状斑点，日文：梨地面)。因而，来自外部的光被该梨皮状表面散射，从而入射到装置内部的光被抑制，因此，增强了抑制金属细线22被看到的效果。
图1的(C)是拍摄实际制造的电路装置的剖视图。参照该图可知，位于密封树脂18的最上层的填料被树脂材料覆盖，未露出到上表面。
参照图2，进一步说明电路装置10的结构。图2的(A)为表示电路装置10的立体图，图2的(B)和图2的(C)是放大表示设置了识别标记30的部位的剖视图。
参照图2的(A)，在密封树脂18的上表面，标记有由位置标记26和记号标记28构成的识别标记30。位置标记26是为了检测电路装置10的平面的位置(角度)而设置的。在此，在电路装置10的左下角部设置有位置标记26。另一方面，记号标记28由文字、数字等构成，由制造公司名、制造时间、产品名、批号、内置的元件特性等构成。对密封树脂18的上表面照射激光，从表面去除部分密封树脂18，由此来形成识别标记30。
如上所述，为了实现电路装置10的薄型化，极薄地形成密封树脂18，该密封树脂18覆盖半导体元件、金属细线22。因而，当强化激光的输出来构成识别标记30时，有可能由于激光产生的热而使半导体元件受到不良影响。在此，为了抑制该不良影响，使激光的输出比通常小。
参照图2的(B)，向密封树脂18的上表面照射激光，由此，将密封树脂18的上部去除10μm左右(T3)，形成识别标记30。通常，在识别标记用的激光处理中将树脂材料去除20μm左右，因此，标记该深度T3的深度非常浅。这样，通过调节所照射的激光的输出，将识别标记30的视觉识别性确保为恒定以上，并防止伴随激光照射而造成的半导体元件的损坏。
图2的(C)示出了识别标记30的另一个结构。在此，密封树脂18的上表面被覆盖层32完全覆盖，去除该覆盖层32的局部来形成识别标记30。覆盖层32是例如与密封树脂18颜色不同的白色涂料等。并且，密封树脂18的上表面被覆盖层32完全覆盖之后，利用激光照射去除覆盖层32的局部来使密封树脂18露出，由此，形成识别标记30。这样，由于密封树脂18几乎没有被激光去除，因此，可以防止激光照射造成的半导体元件的损坏。
下面，参照图3至图7来说明上述结构的电路装置的制造方法。
首先，参照图3，准备基板来安装半导体元件。图3的(A)为表示基板40的俯视图，图3的(B)为基板40的局部剖视图，图3的(C)为连接了半导体元件24之后的基板40的剖视图。
参照图3的(A)，例如由陶瓷等绝缘材料构成的基板40的外形呈长方形，并分开地配置有多个块42。在此，示出了两个块42，但是，也可以在基板40上配置多个块42。在一个块42中矩阵状地包含有多个单元44。在本实施方式中，针对每个块42，通过传递模塑法(transfer molding)进行树脂密封。
参照图3的(B)，层叠第1基板46和第2基板48来形成基板40。第1基板46由厚度为100μm左右的陶瓷基板等构成，在背面设有外部电极36。并且，在与各单元44的周边部相对应的部位，在第1基板46的上表面上层叠有第2基板48。在第2基板48的上表面上设有焊盘34。另外，设置在第2基板48的上表面上的焊盘34与设置在第1基板46的下表面上的外部电极36通过贯穿两基板而设置的通孔进行电连接。
下面，参照图3(C)，将半导体元件24与基板40的各单元44进行连接。作为分立的晶体管或者IC等的半导体元件24的背面固定在第1基板46的上表面上。并且，设置在半导体元件24的上表面上的电极经由金属细线22与焊盘34相连接。如上所述，在本实施方式中，与半导体元件24相连接的金属细线22的端部附近的形状如圆或者椭圆的一部分那样呈弯曲形状。并且，与焊盘34相连接的一侧的金属细线22呈直线形状。
下面，参照图4，将安装有半导体元件的基板40安置在模具50内。参照图4的(A)，在本工序中，进行使用了由上模52和下模54构成的模具50的传递模塑法。在此，上模52的一部分为可沿上下方向移动的可动部58。通过使可动部58上升而使所形成的密封树脂的厚度变厚，通过使可动部58下降而使所形成的密封树脂的厚度变薄。本实施方式使由树脂构成的剥离片56与上模52的内壁紧贴。这样，密封树脂从树脂密封后的模具50的脱模变得容易。并且，剥离薄片56的下表面形成有微细的凹凸，由此形成的密封树脂的表面也成为形成有微细的凹凸的梨皮状表面。
参照图4的(B)，通过使上述结构的上模52和下模54抵接，而形成模腔60，图3的(A)所示的各块42被独立地收纳在模腔60中。
下面，参照图5，将液态或者半固态的密封树脂18注入模腔60中。图5的(A)为表示本工序的剖视图，图5的(B)为表示完成树脂密封后的基板40的俯视图，图5的(C)为放大表示密封树脂18的剖视图。
参照图5的(A)，通过从未图示的浇口向模腔60注入密封树脂，一个块所包含的半导体元件、金属细线以及基板40的上表面被覆盖。完成密封树脂18的填充之后，进行使密封树脂18固化的加热处理，在使上模52和下模54分开之后，从模具50取出形成有密封树脂18的基板40。
参照图5的(B)，在结束上述工序之后，以覆盖基板40的各块的方式形成密封树脂18。另外，为了防止在之后的切割工序中由切割刀片所产生的树脂的碎片对制品产生影响，形成有密封树脂18的区域比形成有单元44的块42宽。
参照图5的(C)，在本工序中，通过使用了注塑模具的注塑成形来形成密封树脂18，因此，密封树脂18所包含的填料20被树脂材料覆盖。覆盖位于最表层的填料20的树脂材料的厚度T1为例如8μm以上的程度。并且，覆盖金属细线22的顶部的密封树脂18的厚度T2为40μm左右以下，形成得比密封树脂18所包含的填料20的最大粒径(55μm)小。
如上所述，位于最表层的填料20被具有遮光性的树脂材料覆盖，由于来自外部的光未到达透明的填料20，因此，防止金属细线、图案被看到。此外，密封树脂18的上表面为与剥离片56的下表面的凹凸形状相对应的梨皮状表面。
下面，参照图6，在密封树脂18的上表面标记识别标记30。图6的(A)为表示本工序的俯视图，图6的(B)为表示激光照射的剖视图。
参照图6的(A)，在块42所包含的各单元44的表面利用激光标记由位置标记26和记号标记28构成的识别标记30。
参照图6的(B)，从上方对密封树脂18的上表面照射激光62，由此，通过从上表面略微去除密封树脂18来形成沟状的识别标记30。在本实施方式中，为了实现薄型封装，极薄地形成密封树脂18，因此，半导体元件容易受到由照射到密封树脂18上的激光的能量造成的不良影响。为了防止该不良影响，将激光的能量调节为较弱，将识别标记30的厚度形成为10μm以下。
另外，如图2的(C)所示，利用覆盖层32覆盖密封树脂18的上表面，也可以利用激光照射去除该覆盖层32的一部分来形成识别标记30。
下面，参照图7，在各单元44的边界分割密封树脂18和基板40而得到分别独立的电路装置。具体地说，首先，使基板40紧贴切割基座64。在此，形成有密封树脂18的基板40的主面与切割基座64紧贴。并且，在各单元44的边界进行切割，使得基板40和密封树脂18分离。
在本工序中，密封树脂18的周边部呈局部向下方突出的形状，树脂密封有可能在该部分破损。然而，密封树脂18以比形成有单元44的区域更广阔地覆盖基板40的方式形成，因此，该破损不会波及到构成单元44的密封树脂。
通过以上工序，制造图1所示的结构的电路装置10。

Claims (12)

1.一种电路装置，其特征在于，包括：
半导体元件；
导电部件，其经由金属细线与上述半导体元件相连接；以及
密封树脂，其由混入了填料的树脂材料构成，用于对上述半导体元件和上述金属细线进行树脂密封，
上述密封树脂的遮光性比上述填料的遮光性优异；
使覆盖上述金属细线的最顶部的上述密封树脂的厚度比上述填料的最大直径小，并且位于最表层的上述填料被上述树脂材料覆盖。
2.根据权利要求1所述的电路装置，其特征在于，
覆盖上述金属细线的最顶部的上述密封树脂的厚度为40μm以下。
3.根据权利要求2所述的电路装置，其特征在于，
上述密封树脂的表面为梨皮状表面。
4.根据权利要求3所述的电路装置，其特征在于，
上述填料呈球状的形状。
5.根据权利要求4所述的电路装置，其特征在于，
在上述密封树脂的主面上未露出上述填料。
6.根据权利要求5所述的电路装置，其特征在于，
上述导电部件为形成在基板的主面上的导电图案，
以覆盖上述基板的主面的方式形成上述密封树脂。
7.根据权利要求6所述的电路装置，其特征在于，
在上述密封树脂的主面上，通过对上述密封树脂照射激光来去除上述密封树脂的局部，由此来标记识别标记，上述识别标记的深度为10μm以下。
8.一种电路装置的制造方法，其特征在于，包括如下工序：
经由金属细线将形成在半导体元件的上表面的电极和导电部件连接起来的工序；以及
通过使用了注塑模具的注塑成形，用密封树脂覆盖上述半导体元件和上述金属细线的工序，该密封树脂由混入了填料的树脂材料构成，上述密封树脂的遮光性比上述填料的遮光性优异；
在进行覆盖的工序中，使覆盖上述金属细线的最顶部的上述密封树脂的厚度比上述填料的最大直径小，并且位于最表层的上述填料被上述树脂材料覆盖。
9.根据权利要求8所述的电路装置的制造方法，其特征在于，
在上述进行覆盖的工序中，进行了采用热固性树脂作为上述树脂材料的传递模塑法。
10.根据权利要求9所述的电路装置的制造方法，其特征在于，
在上述进行覆盖的工序中，由剥离片覆盖上述注塑模具的内壁。
11.根据权利要求10所述的电路装置的制造方法，其特征在于，
上述剥离片的面向内侧的面为梨皮状表面。
12.根据权利要求11所述的电路装置的制造方法，其特征在于，
还具有在上述密封树脂的主面上，通过对上述密封树脂照射激光来去除上述密封树脂的局部，由此来标记识别标记的工序，上述识别标记的深度为10μm以下。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5308213B2 (ja) * 2009-03-31 2013-10-09 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
JP2012243895A (ja) * 2011-05-18 2012-12-10 Renesas Electronics Corp 半導体装置およびその製造方法ならびに携帯電話機
KR102000348B1 (ko) * 2016-09-28 2019-07-15 아사히 가세이 일렉트로닉스 가부시끼가이샤 자기 센서
US10679960B2 (en) * 2017-04-18 2020-06-09 Hall Labs Llc Heat resistant and shock resistant integrated circuit
US10199299B1 (en) * 2017-08-07 2019-02-05 Micron Technology, Inc. Semiconductor mold compound transfer system and associated methods
US10446414B2 (en) * 2017-12-22 2019-10-15 Texas Instruments Incorporated Semiconductor package with filler particles in a mold compound
JP7187306B2 (ja) 2018-12-28 2022-12-12 株式会社オカムラ 扉体付き移動式間仕切パネル
CN112582285B (zh) * 2020-12-15 2023-07-25 青岛歌尔微电子研究院有限公司 封装结构的减薄方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000156434A (ja) * 1998-11-19 2000-06-06 Sanyo Electric Co Ltd 半導体装置
JP2004356382A (ja) * 2003-05-29 2004-12-16 Renesas Technology Corp 半導体集積回路装置
JP2006294825A (ja) * 2005-04-11 2006-10-26 Renesas Technology Corp 半導体集積回路装置
CN101173159A (zh) * 2006-11-02 2008-05-07 比亚迪股份有限公司 一种环氧树脂封装材料组合物

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3679465A (en) * 1970-10-23 1972-07-25 Ciba Geigy Corp Process for producing hardenable epoxy resin compositions
US4767433A (en) * 1986-05-22 1988-08-30 Asahi Glass Company Ltd. Spherical silica glass powder particles and process for their production
US5656098A (en) * 1992-03-03 1997-08-12 Canon Kabushiki Kaisha Photovoltaic conversion device and method for producing same
JPH065742A (ja) * 1992-06-22 1994-01-14 Mitsubishi Electric Corp 半導体装置、その封止に用いられる樹脂および半導体装置の製造方法
US5439622A (en) * 1993-09-07 1995-08-08 Motorola, Inc. Method and apparatus for producing molded parts
JP3434029B2 (ja) * 1994-07-25 2003-08-04 電気化学工業株式会社 エポキシ樹脂組成物
JP3294803B2 (ja) * 1997-08-18 2002-06-24 株式会社日本触媒 熱硬化性樹脂封止材
JP3017485B2 (ja) * 1998-01-23 2000-03-06 アピックヤマダ株式会社 半導体装置の樹脂封止方法及び樹脂封止装置
IL129281A (en) * 1998-06-05 2003-01-12 Premark Rwp Holdings Inc Method of making a textured decorative laminate
US6335548B1 (en) * 1999-03-15 2002-01-01 Gentex Corporation Semiconductor radiation emitter package
JP3738144B2 (ja) 1998-11-27 2006-01-25 三洋電機株式会社 半導体装置の製造方法
US6544816B1 (en) * 1999-08-20 2003-04-08 Texas Instruments Incorporated Method of encapsulating thin semiconductor chip-scale packages
EP1162867B1 (en) * 1999-10-26 2006-04-05 Ibiden Co., Ltd. Multilayer printed wiring board and method of producing multilayer printed wiring board
JP4155729B2 (ja) * 2001-10-01 2008-09-24 電気化学工業株式会社 球状無機質粉末およびその用途
JP2003218145A (ja) * 2002-01-18 2003-07-31 Sony Corp 樹脂封止型の半導体装置の製造法
JP2004074713A (ja) * 2002-08-21 2004-03-11 Hitachi Chem Co Ltd 半導体モールド用離型シート
JP2005011986A (ja) * 2003-06-19 2005-01-13 Sanyo Electric Co Ltd 半導体装置
US7517480B2 (en) * 2003-08-18 2009-04-14 Kortec, Inc. Automatic process control for a multilayer injection molding apparatus
JP4193052B2 (ja) * 2003-08-25 2008-12-10 信越化学工業株式会社 高熱伝導性シリコーンゴム組成物並びに定着ロール及び定着ベルト
EP1569276A1 (en) * 2004-02-27 2005-08-31 Heptagon OY Micro-optics on optoelectronics
JP4421972B2 (ja) * 2004-04-30 2010-02-24 日東電工株式会社 半導体装置の製法
KR100601761B1 (ko) * 2004-07-22 2006-07-19 삼성전자주식회사 이중 성형된 반도체 패키지 제조 방법
JP4652932B2 (ja) * 2005-08-31 2011-03-16 ローム株式会社 モールド型電子部品
JP5036563B2 (ja) * 2006-01-17 2012-09-26 スパンション エルエルシー 半導体装置およびその製造方法
US8470518B2 (en) * 2007-09-14 2013-06-25 E I Du Pont De Nemours And Company Photosensitive element having reinforcing particles and method for preparing a printing form from the element
US9431589B2 (en) * 2007-12-14 2016-08-30 Cree, Inc. Textured encapsulant surface in LED packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000156434A (ja) * 1998-11-19 2000-06-06 Sanyo Electric Co Ltd 半導体装置
JP2004356382A (ja) * 2003-05-29 2004-12-16 Renesas Technology Corp 半導体集積回路装置
JP2006294825A (ja) * 2005-04-11 2006-10-26 Renesas Technology Corp 半導体集積回路装置
CN101173159A (zh) * 2006-11-02 2008-05-07 比亚迪股份有限公司 一种环氧树脂封装材料组合物

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