CN101689509B - 用于形成双金属栅极结构的方法 - Google Patents

用于形成双金属栅极结构的方法 Download PDF

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Publication number
CN101689509B
CN101689509B CN2008800228330A CN200880022833A CN101689509B CN 101689509 B CN101689509 B CN 101689509B CN 2008800228330 A CN2008800228330 A CN 2008800228330A CN 200880022833 A CN200880022833 A CN 200880022833A CN 101689509 B CN101689509 B CN 101689509B
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layer
gate electrode
channel region
metal gate
grid
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CN101689509A (zh
Inventor
G·V·卡尔维
C·卡帕索
斯里坎斯·B.·萨马弗达姆
詹姆斯·K.·谢弗
W·J·泰勒
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NXP USA Inc
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Freescale Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
CN2008800228330A 2007-06-29 2008-05-20 用于形成双金属栅极结构的方法 Active CN101689509B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/771,721 US7666730B2 (en) 2007-06-29 2007-06-29 Method for forming a dual metal gate structure
US11/771,721 2007-06-29
PCT/US2008/064192 WO2009005903A1 (en) 2007-06-29 2008-05-20 Method for forming a dual metal gate structure

Publications (2)

Publication Number Publication Date
CN101689509A CN101689509A (zh) 2010-03-31
CN101689509B true CN101689509B (zh) 2011-05-25

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US (1) US7666730B2 (enExample)
JP (1) JP2010532578A (enExample)
CN (1) CN101689509B (enExample)
TW (1) TWI433273B (enExample)
WO (1) WO2009005903A1 (enExample)

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US8298882B2 (en) * 2009-09-18 2012-10-30 International Business Machines Corporation Metal gate and high-K dielectric devices with PFET channel SiGe
KR101926336B1 (ko) * 2010-02-05 2019-03-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9041116B2 (en) 2012-05-23 2015-05-26 International Business Machines Corporation Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
JP6467171B2 (ja) 2013-09-17 2019-02-06 株式会社半導体エネルギー研究所 半導体装置

Citations (4)

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CN1443367A (zh) * 2000-06-12 2003-09-17 摩托罗拉公司 用于cmos过程的双金属栅极晶体管
US6794252B2 (en) * 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
CN1771590A (zh) * 2003-04-09 2006-05-10 飞思卡尔半导体公司 用于形成双金属栅极结构的处理过程
CN1846305A (zh) * 2003-09-04 2006-10-11 先进微装置公司 整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的互补金属氧化物半导体栅极的方法

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JPH1145885A (ja) * 1997-07-25 1999-02-16 Nec Corp 半導体装置の製造方法
KR100399356B1 (ko) * 2001-04-11 2003-09-26 삼성전자주식회사 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법
JP4034627B2 (ja) * 2001-09-28 2008-01-16 テキサス インスツルメンツ インコーポレイテツド 集積回路及びその製造方法
JP2003318166A (ja) * 2002-04-26 2003-11-07 Promos Technologies Inc ハードマスク除去方法、トレンチ形成方法、コンタクト形成方法
US6645818B1 (en) 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
JP2004165555A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6972224B2 (en) 2003-03-27 2005-12-06 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
JP2005093530A (ja) * 2003-09-12 2005-04-07 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
US6897095B1 (en) * 2004-05-12 2005-05-24 Freescale Semiconductor, Inc. Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
US8178902B2 (en) * 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US20060011949A1 (en) * 2004-07-18 2006-01-19 Chih-Wei Yang Metal-gate cmos device and fabrication method of making same
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
KR100719340B1 (ko) 2005-01-14 2007-05-17 삼성전자주식회사 듀얼 게이트 전극을 갖는 반도체 소자 및 그 형성 방법
KR100697694B1 (ko) 2005-08-02 2007-03-20 삼성전자주식회사 듀얼 게이트를 갖는 반도체 장치 및 그 제조 방법
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Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
CN1443367A (zh) * 2000-06-12 2003-09-17 摩托罗拉公司 用于cmos过程的双金属栅极晶体管
US6794252B2 (en) * 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
CN1771590A (zh) * 2003-04-09 2006-05-10 飞思卡尔半导体公司 用于形成双金属栅极结构的处理过程
CN1846305A (zh) * 2003-09-04 2006-10-11 先进微装置公司 整合具有不同功函数的金属以形成具有高k栅极电介质及相关结构的互补金属氧化物半导体栅极的方法

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Publication number Publication date
CN101689509A (zh) 2010-03-31
JP2010532578A (ja) 2010-10-07
TW200903722A (en) 2009-01-16
US20090004792A1 (en) 2009-01-01
US7666730B2 (en) 2010-02-23
WO2009005903A1 (en) 2009-01-08
TWI433273B (zh) 2014-04-01

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