TWI433273B - 形成雙金屬閘極結構之方法 - Google Patents

形成雙金屬閘極結構之方法 Download PDF

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Publication number
TWI433273B
TWI433273B TW097118679A TW97118679A TWI433273B TW I433273 B TWI433273 B TW I433273B TW 097118679 A TW097118679 A TW 097118679A TW 97118679 A TW97118679 A TW 97118679A TW I433273 B TWI433273 B TW I433273B
Authority
TW
Taiwan
Prior art keywords
layer
forming
gate
gate electrode
channel region
Prior art date
Application number
TW097118679A
Other languages
English (en)
Chinese (zh)
Other versions
TW200903722A (en
Inventor
Gauri V Karve
Cristiano Capasso
Srikanth B Samavedam
James K Schaeffer
Jr William J Taylor
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200903722A publication Critical patent/TW200903722A/zh
Application granted granted Critical
Publication of TWI433273B publication Critical patent/TWI433273B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
TW097118679A 2007-06-29 2008-05-21 形成雙金屬閘極結構之方法 TWI433273B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/771,721 US7666730B2 (en) 2007-06-29 2007-06-29 Method for forming a dual metal gate structure

Publications (2)

Publication Number Publication Date
TW200903722A TW200903722A (en) 2009-01-16
TWI433273B true TWI433273B (zh) 2014-04-01

Family

ID=40161071

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097118679A TWI433273B (zh) 2007-06-29 2008-05-21 形成雙金屬閘極結構之方法

Country Status (5)

Country Link
US (1) US7666730B2 (enExample)
JP (1) JP2010532578A (enExample)
CN (1) CN101689509B (enExample)
TW (1) TWI433273B (enExample)
WO (1) WO2009005903A1 (enExample)

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* Cited by examiner, † Cited by third party
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US8298882B2 (en) * 2009-09-18 2012-10-30 International Business Machines Corporation Metal gate and high-K dielectric devices with PFET channel SiGe
KR101926336B1 (ko) * 2010-02-05 2019-03-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9041116B2 (en) * 2012-05-23 2015-05-26 International Business Machines Corporation Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
US9887297B2 (en) 2013-09-17 2018-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor layer in which thickness of the oxide semiconductor layer is greater than or equal to width of the oxide semiconductor layer

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JPH1145885A (ja) * 1997-07-25 1999-02-16 Nec Corp 半導体装置の製造方法
US6444512B1 (en) * 2000-06-12 2002-09-03 Motorola, Inc. Dual metal gate transistors for CMOS process
KR100399356B1 (ko) * 2001-04-11 2003-09-26 삼성전자주식회사 듀얼 게이트를 가지는 씨모스형 반도체 장치 형성 방법
JP4034627B2 (ja) * 2001-09-28 2008-01-16 テキサス インスツルメンツ インコーポレイテツド 集積回路及びその製造方法
US6794252B2 (en) 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
JP2003318166A (ja) * 2002-04-26 2003-11-07 Promos Technologies Inc ハードマスク除去方法、トレンチ形成方法、コンタクト形成方法
US6645818B1 (en) 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
JP2004165555A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US6972224B2 (en) 2003-03-27 2005-12-06 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
US6790719B1 (en) * 2003-04-09 2004-09-14 Freescale Semiconductor, Inc. Process for forming dual metal gate structures
US6872613B1 (en) * 2003-09-04 2005-03-29 Advanced Micro Devices, Inc. Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure
JP2005093530A (ja) * 2003-09-12 2005-04-07 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
US6897095B1 (en) * 2004-05-12 2005-05-24 Freescale Semiconductor, Inc. Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
US8178902B2 (en) * 2004-06-17 2012-05-15 Infineon Technologies Ag CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US20060011949A1 (en) * 2004-07-18 2006-01-19 Chih-Wei Yang Metal-gate cmos device and fabrication method of making same
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
KR100719340B1 (ko) 2005-01-14 2007-05-17 삼성전자주식회사 듀얼 게이트 전극을 갖는 반도체 소자 및 그 형성 방법
KR100697694B1 (ko) 2005-08-02 2007-03-20 삼성전자주식회사 듀얼 게이트를 갖는 반도체 장치 및 그 제조 방법
TWI267926B (en) * 2005-09-23 2006-12-01 Ind Tech Res Inst A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate
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US7504696B2 (en) * 2006-01-10 2009-03-17 International Business Machines Corporation CMOS with dual metal gate
JP2008210874A (ja) * 2007-02-23 2008-09-11 Toshiba Corp 半導体装置の製造方法
US7863124B2 (en) * 2007-05-10 2011-01-04 International Business Machines Corporation Residue free patterned layer formation method applicable to CMOS structures
US7445981B1 (en) * 2007-06-29 2008-11-04 Freescale Semiconductor, Inc. Method for forming a dual metal gate structure
US8211786B2 (en) * 2008-02-28 2012-07-03 International Business Machines Corporation CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication

Also Published As

Publication number Publication date
WO2009005903A1 (en) 2009-01-08
CN101689509A (zh) 2010-03-31
US7666730B2 (en) 2010-02-23
TW200903722A (en) 2009-01-16
CN101689509B (zh) 2011-05-25
US20090004792A1 (en) 2009-01-01
JP2010532578A (ja) 2010-10-07

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