JP2010532578A - デュアルメタルゲート構造の形成方法 - Google Patents

デュアルメタルゲート構造の形成方法 Download PDF

Info

Publication number
JP2010532578A
JP2010532578A JP2010514909A JP2010514909A JP2010532578A JP 2010532578 A JP2010532578 A JP 2010532578A JP 2010514909 A JP2010514909 A JP 2010514909A JP 2010514909 A JP2010514909 A JP 2010514909A JP 2010532578 A JP2010532578 A JP 2010532578A
Authority
JP
Japan
Prior art keywords
layer
forming
gate
gate electrode
channel region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010514909A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010532578A5 (enExample
Inventor
ブイ． カーブ、ガウリ
カパッソ、クリスチアーノ
ビー． サマベダム、スリカンス
ケイ． シェーファー、ジェームズ
ジェイ．ジュニア テイラー、ウィリアム
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2010532578A publication Critical patent/JP2010532578A/ja
Publication of JP2010532578A5 publication Critical patent/JP2010532578A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
JP2010514909A 2007-06-29 2008-05-20 デュアルメタルゲート構造の形成方法 Pending JP2010532578A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/771,721 US7666730B2 (en) 2007-06-29 2007-06-29 Method for forming a dual metal gate structure
PCT/US2008/064192 WO2009005903A1 (en) 2007-06-29 2008-05-20 Method for forming a dual metal gate structure

Publications (2)

Publication Number Publication Date
JP2010532578A true JP2010532578A (ja) 2010-10-07
JP2010532578A5 JP2010532578A5 (enExample) 2011-07-07

Family

ID=40161071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010514909A Pending JP2010532578A (ja) 2007-06-29 2008-05-20 デュアルメタルゲート構造の形成方法

Country Status (5)

Country Link
US (1) US7666730B2 (enExample)
JP (1) JP2010532578A (enExample)
CN (1) CN101689509B (enExample)
TW (1) TWI433273B (enExample)
WO (1) WO2009005903A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298882B2 (en) * 2009-09-18 2012-10-30 International Business Machines Corporation Metal gate and high-K dielectric devices with PFET channel SiGe
KR101926336B1 (ko) * 2010-02-05 2019-03-07 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
US9041116B2 (en) * 2012-05-23 2015-05-26 International Business Machines Corporation Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)
US9373501B2 (en) * 2013-04-16 2016-06-21 International Business Machines Corporation Hydroxyl group termination for nucleation of a dielectric metallic oxide
US9887297B2 (en) 2013-09-17 2018-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor layer in which thickness of the oxide semiconductor layer is greater than or equal to width of the oxide semiconductor layer

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145885A (ja) * 1997-07-25 1999-02-16 Nec Corp 半導体装置の製造方法
JP2002359295A (ja) * 2001-04-11 2002-12-13 Samsung Electronics Co Ltd デュアルゲートを有するｃｍｏｓ型半導体装置形成方法
JP2003188275A (ja) * 2001-09-28 2003-07-04 Texas Instr Inc <Ti> ゲート構造及びその製造方法
JP2003318166A (ja) * 2002-04-26 2003-11-07 Promos Technologies Inc ハードマスク除去方法、トレンチ形成方法、コンタクト形成方法
JP2004165555A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2005093530A (ja) * 2003-09-12 2005-04-07 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
US20050280104A1 (en) * 2004-06-17 2005-12-22 Hong-Jyh Li CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US20060011949A1 (en) * 2004-07-18 2006-01-19 Chih-Wei Yang Metal-gate cmos device and fabrication method of making same
JP2007088400A (ja) * 2005-09-23 2007-04-05 Ind Technol Res Inst 相補型ｍｏｓ装置およびその製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6444512B1 (en) * 2000-06-12 2002-09-03 Motorola, Inc. Dual metal gate transistors for CMOS process
US6794252B2 (en) 2001-09-28 2004-09-21 Texas Instruments Incorporated Method and system for forming dual work function gate electrodes in a semiconductor device
US6645818B1 (en) 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
US6972224B2 (en) 2003-03-27 2005-12-06 Freescale Semiconductor, Inc. Method for fabricating dual-metal gate device
US6790719B1 (en) * 2003-04-09 2004-09-14 Freescale Semiconductor, Inc. Process for forming dual metal gate structures
US6872613B1 (en) * 2003-09-04 2005-03-29 Advanced Micro Devices, Inc. Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure
US6897095B1 (en) * 2004-05-12 2005-05-24 Freescale Semiconductor, Inc. Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
KR100719340B1 (ko) 2005-01-14 2007-05-17 삼성전자주식회사 듀얼 게이트 전극을 갖는 반도체 소자 및 그 형성 방법
KR100697694B1 (ko) 2005-08-02 2007-03-20 삼성전자주식회사 듀얼 게이트를 갖는 반도체 장치 및 그 제조 방법
US20070152276A1 (en) * 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
US7504696B2 (en) * 2006-01-10 2009-03-17 International Business Machines Corporation CMOS with dual metal gate
JP2008210874A (ja) * 2007-02-23 2008-09-11 Toshiba Corp 半導体装置の製造方法
US7863124B2 (en) * 2007-05-10 2011-01-04 International Business Machines Corporation Residue free patterned layer formation method applicable to CMOS structures
US7445981B1 (en) * 2007-06-29 2008-11-04 Freescale Semiconductor, Inc. Method for forming a dual metal gate structure
US8211786B2 (en) * 2008-02-28 2012-07-03 International Business Machines Corporation CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1145885A (ja) * 1997-07-25 1999-02-16 Nec Corp 半導体装置の製造方法
JP2002359295A (ja) * 2001-04-11 2002-12-13 Samsung Electronics Co Ltd デュアルゲートを有するｃｍｏｓ型半導体装置形成方法
JP2003188275A (ja) * 2001-09-28 2003-07-04 Texas Instr Inc <Ti> ゲート構造及びその製造方法
JP2003318166A (ja) * 2002-04-26 2003-11-07 Promos Technologies Inc ハードマスク除去方法、トレンチ形成方法、コンタクト形成方法
JP2004165555A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP2005093530A (ja) * 2003-09-12 2005-04-07 Semiconductor Leading Edge Technologies Inc 半導体装置の製造方法
US20050280104A1 (en) * 2004-06-17 2005-12-22 Hong-Jyh Li CMOS transistor with dual high-k gate dielectric and method of manufacture thereof
US20060011949A1 (en) * 2004-07-18 2006-01-19 Chih-Wei Yang Metal-gate cmos device and fabrication method of making same
JP2007088400A (ja) * 2005-09-23 2007-04-05 Ind Technol Res Inst 相補型ｍｏｓ装置およびその製造方法

Also Published As

Publication number Publication date
WO2009005903A1 (en) 2009-01-08
CN101689509A (zh) 2010-03-31
US7666730B2 (en) 2010-02-23
TW200903722A (en) 2009-01-16
CN101689509B (zh) 2011-05-25
US20090004792A1 (en) 2009-01-01
TWI433273B (zh) 2014-04-01

Similar Documents

Publication Publication Date Title
CN104241135B (zh) 在硅化物形成之前在触点蚀刻之后添加的电介质衬里
JP4767946B2 (ja) 異なるゲート誘電体を用いたｎｍｏｓ及びｐｍｏｓトランジスタを具備する相補型金属酸化物半導体集積回路
CN101689508B (zh) 用于形成双金属栅极结构的方法
US9620506B2 (en) Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
CN101091244A (zh) 用于cmos工艺的金属栅极晶体管及其制造方法
US7297598B2 (en) Process for erase improvement in a non-volatile memory device
US9373624B1 (en) FinFET devices including epitaxially grown device isolation regions, and a method of manufacturing same
JP4982382B2 (ja) リセス型ソース／ドレイン領域をｓｏｉウェハに含む半導体形成プロセス
JP2010532578A (ja) デュアルメタルゲート構造の形成方法
CN104377204A (zh) 非易失性存储器(NVM)单元、高压晶体管和高-k 以及金属栅晶体管集成
US8778772B2 (en) Method of forming transistor with increased gate width
US9607903B2 (en) Method for forming field effect transistors
JP2008210874A (ja) 半導体装置の製造方法
KR100814372B1 (ko) 반도체 장치의 제조 방법
JP2007036116A (ja) 半導体装置の製造方法
CN110729248B (zh) 一种堆叠纳米线或片cmos器件制备方法
CN104037073A (zh) 一种半导体器件的制造方法
CN102487017A (zh) 应变cmos器件的制作方法
US20130273709A1 (en) Methods of recessing an active region and sti structures in a common etch process
CN107123619A (zh) 在绝缘体上半导体衬底上形成隔离结构的方法
KR100657155B1 (ko) 반도체 장치의 제조 방법
US20150064861A1 (en) Method for manufacturing semiconductor device
JP2010021310A (ja) 半導体装置の製造方法
CN102299110A (zh) 一种半导体器件的形成方法及其半导体器件

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110518

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110518

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110518

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20120227

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130108

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130408

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130415

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130507

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130604