CN101681924B - 形成具有量子阱沟道的非平面晶体管 - Google Patents

形成具有量子阱沟道的非平面晶体管 Download PDF

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CN101681924B
CN101681924B CN2008800061794A CN200880006179A CN101681924B CN 101681924 B CN101681924 B CN 101681924B CN 2008800061794 A CN2008800061794 A CN 2008800061794A CN 200880006179 A CN200880006179 A CN 200880006179A CN 101681924 B CN101681924 B CN 101681924B
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C·O·徐
P·马吉
W·蔡
J·卡瓦列罗斯
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Abstract

在一个实施例中，本发明包括一种设备，所述设备具有：衬底；形成于所述衬底上的掩埋氧化物层；形成于所述掩埋氧化物层上的绝缘体上硅(SOI)内核；包覆在SOI内核周围的压缩应变量子阱(QW)层；以及包覆在QW层周围的拉伸应变硅层。还描述其他实施例并主张其权利。

Description

形成具有量子阱沟道的非平面晶体管
背景技术
通过在元素硅(Si)衬底上开发薄膜弛豫的晶格常数III-V半导体可以实现多种电子和光电子器件。能够实现III-V材料性能优点的表面层可以承载各种高性能电子器件，例如，用诸如但不限于锑化铟(InSb)、砷化铟镓(InGaAs)和砷化铟(InAs)等的极高迁移率材料制造的互补金属氧化物半导体(CMOS)和量子阱(QW)晶体管。尽管已经将这种高迁移率QW沟道结合到平面晶体管中，但尚未将它们结合到非平面晶体管中。
附图说明
图1是根据本发明实施例的器件结构的截面图。
图2是根据本发明实施例的结构的能带图。
图3是根据本发明实施例的方法的流程图。
具体实施方式
在各实施例中，可以将高迁移率应变量子阱(QW)沟道结合到诸如非平面金属氧化物半导体场效应晶体管(MOSFET)等的非平面结构中。这种非平面晶体管包括形成于下方氧化物层上的硅结构或鳍，接着可以在硅鳍周围形成栅极结构。通过这种方式，可以实现具有极好静电控制的高迁移率沟道，以进行最终的沟道长度缩放。此外，可以同时引入拉伸应变和压缩应变，以利用共同的材料内核分别优化n沟道MOSFET(NMOS)的硅中的电子输运和p沟道MOSFET(PMOS)的锗(Ge)中的空穴输运。此外，正确而充分大的导电性和价带偏移提供了电子和空穴的约束。利用实施例，可以利用常规叠置工程学形成晶体管器件，因为可以由硅形成最外面的内核层，以允许在其上形成栅极叠置体。
现在参考图1，其示出了根据本发明实施例的器件结构10的截面图。如图1所示，可以使用结构10在衬底30上形成NMOS或PMOS器件。在各实施例中，衬底30可以是高电阻率n或p型(100)偏离-取向Si衬底，但本发明的范围不受此限制。如图1所示，接下来可以在衬底30上形成掩埋氧化物层34。在各实施例中，可以由诸如二氧化硅(SiO2)或其他氧化物等的适当氧化物材料形成掩埋氧化物层34。
仍然参考图1，接下来可以形成绝缘体上硅(SOI)层。具体而言，可以沉积(或键合)SOI层并对其进行构图以获得SOI内核40，SOI内核是掩埋氧化物层34上的非平面结构。注意，该SOI内核是由宽度远小于掩埋氧化物层34的范围的硅鳍或窄条形成的。注意，该层也可以是发生应变的。如图1所示，压缩应变QW层42可以被包覆在SOI内核40周围。在各实施例中，QW层42可以是SOI内核40上选择性生长的Ge层。可以通过气相沉积方法进行生长，且厚度范围可以从1纳米(nm)-20nm。接下来，可以在QW层42上形成拉伸应变Si层44。在各实施例中，可以选择性生长Si层44，以包覆在QW层42周围。可以通过气相沉积方法进行生长，且厚度范围可以从1nm-20nm。利用这种构造，空穴(电子)可以迁移并被约束在QW层42之内，以实现高迁移率导通。
仍然参考图1，接下来可以在Si层44上形成栅极电介质层46。在各实施例中，可以利用原子层沉积(ALD)形成保形的栅极电介质层，从而包覆在Si/Ge/SOI形成的内核周围。在各实施例中，可以利用低介电常数(低k)材料，例如掺碳氧化物或其他这样的电介质来形成栅极电介质层46。在栅极电介质层46上可以形成栅电极层48。在各实施例中，可以使用ALD工艺来形成保形的栅电极层48。注意，在各实施例中，可以将类似的或不同的电极材料用于n沟道和p沟道MOSFET。
尽管以图1的实施例中的这一特定的实施方式示出，但本发明的范围不限于此。例如，在其他实施例中，可以使用具有适当隔离的体Si衬底来形成Si内核(即在给定的SOI衬底上方)。此外，除了由纯Ge形成的QW层之外，也可以利用发生压缩应变的高Ge含量的硅锗(SiGe)来形成QW层。在各实施例中，Ge浓度可以介于大约10％和100％之间。通过这种方式，可以为特定应用实现较厚的QW。尽管图1中未示出，完全完成的器件还可以包括由接触层形成的源电极和漏电极。对于NMOS器件而言，接触层可以是n+掺杂的，而对于PMOS器件而言，接触层可以是p+掺杂的。
因此，在各实施例中，可以利用高迁移率材料形成非平面晶体管器件，以形成高电子迁移率晶体管(HEMT)或高空穴迁移率晶体管(HHMT)或具有高速度和低功耗的高空穴迁移率晶体管(HHMT)。这种器件可以具有小于大约50nm的尺寸，开关频率大约为562吉赫(GHz)。这种器件可能能够工作在大约0.5-1.0伏之间而没有驱动电流的显著减小的情况下。此外，实施例可以在栅极长度上提供低于硅基器件的栅极延迟。
现在参考图2，其示出了根据本发明实施例的结构的能带图。如图2所示，能带图通过顶部的线示出了导带(即EC)，通过下方的线示出了价带(即EV)。从图2的左侧开始，形成可以为纯硅的SOI层。在该层上方，可以形成QW层，可以由压缩应变锗或硅锗(SiGe)形成QW层。可以将QW沟道层形成为比SOI内核具有更小的带隙。在QW沟道层上方，可以形成上拉伸应变硅层，在一些实施例中，该层可以具有比SOI内核小的带隙，但具有比QW沟道层大的带隙。然后，如图2所示，可以在硅层上方形成电介质层，其具有比其他层更大的带隙。如图2所示，Ge层为空穴提供QW，Si层为电子提供QW。
现在参考图3，其示出了根据本发明实施例的方法的流程图。如图3所示，可以通过在Si衬底上形成掩埋氧化物层(方框110)开始方法100。接下来，可以在掩埋氧化物层上形成SOI内核(方框120)。例如，可以沉积(或键合)硅层并对其进行构图以形成SOI内核。然后可以在SOI内核周围包覆QW层(方框130)。例如，在一个实施例中，可以在SOI内核上生长应变压缩Ge或SiGe层。在QW层上方可以形成Si层，以包覆在QW层周围(方框140)。然后，可以在该结构上方形成栅极叠置体，其包括电介质层和栅电极(方框150)。在各实施例中，可以执行ALD工艺以获得保形的栅极电介质层和保形的栅电极。通过这种方式，可以形成具有高迁移率的非平面晶体管。
尽管已经针对有限数量的实施例描述了本发明，但本领域的技术人员将从中想到很多修改和变化。所附权利要求意在覆盖落在本发明的真实精神和范围之内的所有这种修改和变化。

Claims (11)

1.一种半导体设备，其包括：
衬底；
形成于所述衬底上的掩埋氧化物层；
直接形成于所述掩埋氧化物层上的绝缘体上硅内核，所述绝缘体上硅内核由所述掩埋氧化物层上的硅鳍形成；
直接包覆在所述绝缘体上硅内核周围的量子阱层，其中所述量子阱层是发生压缩应变的；以及
包覆在所述量子阱层周围的硅层，其中所述硅层是发生拉伸应变的。
2.根据权利要求1所述的设备，其中所述量子阱层由硅锗形成，且Ge浓度至少为10％。
3.根据权利要求1所述的设备，还包括：
形成于所述硅层上方的栅极电介质层；以及
形成于所述栅极电介质层上方的栅电极层。
4.根据权利要求3所述的设备，其中所述设备包括非平面晶体管，其中所述量子阱层包括所述非平面晶体管的沟道。
5.根据权利要求4所述的设备，其中所述非平面晶体管包括高电子迁移率晶体管或高空穴迁移率晶体管。
6.一种制造半导体设备的方法，其包括：
在衬底上形成掩埋氧化物层；
直接在所述掩埋氧化物层上形成绝缘体上硅内核，所述绝缘体上硅内核包括硅的窄条；
形成直接包覆在所述绝缘体上硅内核周围的压缩应变量子阱层；以及
形成包覆在所述量子阱层周围的硅层，其中所述硅层是发生拉伸应变的。
7.根据权利要求6所述的方法，还包括形成Ge浓度至少为10％的硅锗量子阱层。
8.根据权利要求6所述的方法，还包括形成非平面晶体管，其中所述量子阱层包括所述非平面晶体管的沟道。
9.根据权利要求8所述的方法，其中所述非平面晶体管包括高电子迁移率晶体管或高空穴迁移率晶体管。
10.根据权利要求6所述的方法，还包括：
形成栅极电介质层，该栅极电介质层形成在所述硅层上方；以及
在所述栅极电介质层上方形成栅电极层。
11.根据权利要求10所述的方法，还包括利用原子层沉积工艺形成所述栅极电介质层和所述栅电极层。
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