CN106298947A - 一种双栅InGaAs PMOS场效应晶体管 - Google Patents

一种双栅InGaAs PMOS场效应晶体管 Download PDF

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CN106298947A
CN106298947A CN201610890501.0A CN201610890501A CN106298947A CN 106298947 A CN106298947 A CN 106298947A CN 201610890501 A CN201610890501 A CN 201610890501A CN 106298947 A CN106298947 A CN 106298947A
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CN106298947B (zh
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王盛凯
刘洪刚
孙兵
常虎东
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Abstract

本发明公开了一种双栅InGaAs PMOS场效应晶体管，涉及半导体集成电路制造技术领域。本发明所述的场效应晶体管包括底栅电极、底栅介质层、底栅界面控制层、InGaAs沟道层、上界面控制层、高掺杂P型GaAs层、欧姆接触层、源漏金属电极、顶栅介质层、顶栅电极，其中源漏金属电极位于欧姆接触层两侧，在源漏金属电极中间刻蚀栅槽结构至界面控制层上表面，并将顶栅介质层均匀覆盖在栅槽结构内表面，最后将顶栅电极制备在顶栅介质层上。本发明利用双栅结构和界面控制层设计，实现了PMOS场效应晶体管更好的栅控功能和低界面态密度，能够满足高性能PMOS管的技术要求。

Description

一种双栅InGaAs PMOS场效应晶体管
技术领域
本发明属于半导体集成电路制造技术领域，具体涉及到一种双栅InGaAs沟道的PMOS场效应晶体管，能应用于高性能III-V族CMOS器件中。
背景技术
现有的硅集成电路技术遵循摩尔定律通过缩小特征尺寸来提高性能，在这过程中将带来工艺设备和工艺的复杂化，尤其是当半导体技术发展到纳米尺度后，硅集成电路技术日益逼近其理论和技术的双重极限。采用新材料和新器件结构成为继续提高CMOS器件性能的一个重要研究方向。III-V族半导体以其较高的电子迁移率，并且在低电场和强场下都具有非常优异的输运性能，成为当前的研究热点。除此之外，III-V族半导体拥有一系列晶格匹配的异质结材料体系，可以灵活地应用能带工程和杂质工程同时对器件进行设计。但对于InGaAs PMOS器件，针对较低的空穴迁移率，要实现高性能的PMOS器件依然需要解决一系列问题，在III-V族半导体表面，需要降低MOS界面态密度来提高沟道的载流子迁移率，同时采用传统器件结构难以满足高性能的要求。
因此，需要一种新的方法和结构形式实现高性能的InGaAs PMOS器件，以满足III-V族CMOS技术的要求。
发明内容
(一)要解决的技术问题
传统结构的CMOS器件因为在电路不断集成缩小的情况下，在其研究中遇到了工作电流低、载流子散射高、界面态密度高等瓶颈，限制了该器件的研究和发展工作。因此，本发明通过提供了一种具有高载流子迁移率的双栅结构和低界面态密度的界面控制层并与底栅介质层的结合，以满足高性能III-V族CMOS技术的性能要求。
(二)技术方案
为达到上述目的，本发明提供了一种双栅InGaAs PMOS场效应晶体管，其中，包括：底栅电极、界面控制层、顶栅电极。
一种双栅InGaAs PMOS场效应晶体管，包括：底栅结构、InGaAs沟道层和顶栅结构、下界面控制层和上界面控制层，所述的下界面控制层位于所述底栅结构和InGaAs沟道层之间，所述的上界面控制层位于所述顶栅结构和InGaAs沟道层之间。
所述的上界面控制层和所述的下界面控制层的厚度范围均介于单个原子层到20nm之间。
所述的下界面控制层和上界面控制层禁带宽度大于所述InGaAs沟道层材料，可钝化MOS界面处的悬挂键，实现低界面态密度，并降低沟道中载流子的散射，均具有第一类量子阱能带对准关系。
所述的InGaAs沟道层的厚度为1-20nm，In组分为低In组分，组分为0.2-0.4之间，以利于器件关态电流的下降。
所述的底栅结构包括底栅电极和底栅介质层。
所述的底栅电极包括电极金属层和功函数层。
所述的顶栅结构包括顶栅电极、顶栅介质层、欧姆接触层、高掺杂P型GaAs层和源漏金属电极。
所述的顶栅电极包括电极金属层和功函数层。
所述的高掺杂P型GaAs层与所述InGaAs沟道层的晶格为匹配或者赝配关系。
所述的高掺杂P型GaAs层，掺杂浓度大于1e18cm-3。
所述的欧姆接触层采用重掺杂的InGaAs材料，掺杂浓度大于1e19cm-3。
所述的InGaAs沟道层中空穴具有量子限制效应。
所述的欧姆接触层和高掺杂GaAs层中形成栅槽结构，栅槽结构内表面均匀覆盖有一层顶栅介质层；在顶栅介质层上具有顶栅电极，源漏金属电极分布在欧姆接触层两端。
所述的顶栅介质层和底栅介质层的介电常数K大于8。
所述的顶栅介质层或底栅介质层采用的材料包括氧化物、氮化物、氮氧化物、以及它们的任意混合、或者多层任意组合。
(三)有益效果
根据上述技术方案可以得出，本发明具有以下有益效果：本发明提供的一种InGaAs PMOS场效应晶体管，通过采用双栅器件结构来提高器件的栅控功能，提高器件的工作电流，同时通过采用界面控制层来降低界面态密度，并降低沟道中载流子的散射，实现较高的载流子迁移率，通过界面控制层与高介电常数栅介质的结合来降低等效氧化层厚度(EOT)，最终实现低界面态密度和高工作电流的双栅InGaAs PMOS场效应晶体管，满足了高性能III-V族CMOS技术的要求。
附图说明
图1是本发明提供的具有低界面态密度和高工作电流的双栅InGaAs PMOS场效应晶体管的结构示意图。
图2是根据上述器件结构利用TCAD工具仿真得到的器件的转移特性曲线。
其中，图1：底栅电极(101)、底栅介质层(102)、下界面控制层(103)、InGaAs沟道层(104)、上界面控制层(105)、高掺杂P型GaAs层(106)、欧姆接触层(107)、源漏金属电极(108)(109)、顶栅介质层(110)、顶栅电极(111)。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明作进一步的详细说明。
根据图1具体实施例1所示的双栅InGaAs PMOS场效应晶体管的结构示意图，该场效应晶体管包括：底栅电极(101)；在该底栅电极(101)上的底栅介质层(102)；在底栅介质层(102)上的下界面控制层(103)；在下界面控制层(103)上的InGaAs沟道层(104)；在InGaAs沟道层上的上界面控制层(105)；在上界面控制层(105)上的高掺杂P型GaAs层(106)；在高掺杂GaAs层(106)上的欧姆接触层(107)；在欧姆接触层(107)上形成的源漏金属电极(108)(109)；在源漏金属电极中间对所述欧姆接触层(107)和高掺杂P型GaAs层(106)进行刻蚀，刻蚀至所述上界面控制层(105)表面从而形成栅槽结构；在栅槽结构内形成顶栅介质层(110)；在顶栅介质层(110)上形成顶栅电极(111)。
所述顶栅结构包括顶栅电极(111)、顶栅介质层(110)、漏源金属电极(108)(109)、欧姆接触层(107)、高掺杂P型GaAs层(106)；所述的低栅结构包括底栅电极(101)和底栅介质层(102)，其中，所述的顶栅电极(111)和底栅电极(101)均包括电极金属层和功函数层，其中的功函数层用于调节器件的阈值电压。
所述底栅介质层(102)的介电常数K大于8，该底栅介质层(102)采用的材料包括氧化物、氮化物、氮氧化物、以及它们的任意混合、或者多层任意组合。
所述上界面控制层(105)、下界面控制层(103)其禁带宽度大于所述InGaAs沟道层(104)材料，能钝化MOS界面处的悬挂键，实现低界面态密度，并降低沟道中载流子的散射，且所述上界面控制层(105)、下界面控制层(103)的厚度范围介于单个原子层到20nm之间。
所述采用的InGaAs沟道层(104)的厚度为1-20nm，In组分为低In组分，组分为0.2-0.4之间，以利于器件关态电流的下降。
所述上界面控制层(105)、下界面控制层(103)与所述InGaAs沟道的晶格为匹配或者赝配关系，且具有第一类量子阱能带对准关系，空穴在InGaAs沟道层(104)中具有量子限制效应。
所述高掺杂P型GaAs层(106)，掺杂浓度大于1e18cm-3。
所述欧姆接触层(107)采用重掺杂的InGaAs材料，掺杂浓度大于1e19cm-3.
所述栅槽结构形成于源漏金属电极(108)(109)之间，采用选择性腐蚀技术使栅槽刻蚀自动终止于所述上界面控制层(105)表面。
所述顶栅介质层(110)形成于所述栅槽结构的内表面，底栅介质层(102)形成于下界面控制层(103)的表面。
根据图1具体实施例1所示的双栅InGaAs PMOS场效应晶体管的结构示意图，以下对其制备方法进行详细描述，该方法包括以下步骤：
步骤1：在单晶GaAs衬底上外延生长III-V族半导体缓冲层；
步骤2：在半导体缓冲层上外延生长刻蚀阻止层，以利于工艺制作过程中刻蚀GaAs衬底而保护其他外延层；
步骤3：在刻蚀阻止层上依次外延欧姆接触层(107)InGaAs材料和高掺杂P型GaAs层(106)GaAs材料；
步骤4：然后外延生长下界面控制层(103)，InGaAs沟道层(104)和上界面控制层(105)，在InGaAs沟道层(104)位于上界面控制层(105)和下界面控制层(103)之间，其禁带宽度大于InGaAs沟道材料，能起到钝化界面的悬挂键，实现低界面态密度；
步骤5：在上界面控制层(105)上沉积顶栅介质层(110)材料，沉积的主要方法为原子层沉积(ALD)；
步骤6：在顶栅介质层(110)上沉积顶栅电极(111)，形成双栅器件的背栅电极，包括电极金属层、功函数层及低电阻栅电极层；
步骤7：通过键合的方式将背栅电极键合在单晶衬底上，包括硅以及III-V族半导体衬底；
步骤8：刻蚀GaAs衬底至刻蚀阻止层，随后形成源漏结构，可以采用湿法或干法选择性刻蚀形成；
步骤9：在刻蚀形成的栅槽结构中，沉积顶栅介质(110)材料，随后在顶栅介质层(110)表面沉积顶栅电极(111)；
步骤10：沉积源漏金属电极(108)(109)，源漏金属电极(108)(109)与高掺杂欧姆接触层(107)形成良好的欧姆接触，以满足高性能PMOS器件的要求。
如图2所示根据上述器件结构利用TCAD工具仿真得到的器件的转移特性曲线，依据本发明研制的40纳米双栅InGaAs PMOS晶体管可以在0.7V下工作，电流开关比大于100000，开态电流超过500mA/mm，表现出优越的高速低功耗特性。因此，本发明提供的这种双栅InGaAs PMOS场效应晶体管，通过采用双栅器件结构来提高器件的栅控功能，提高器件的工作电流，同时通过采用界面控制层来降低界面态密度，并降低沟道中载流子的散射，实现较高的载流子迁移率，通过界面控制层与高介电常数栅介质的结合来降低等效氧化层厚度(EOT)，最终实现低界面态密度和高工作电流的双栅InGaAs PMOS场效应晶体管，满足高性能III-V族CMOS技术的要求。
以上所述的具体实施例，对本发明的目的、技术方案和有益结果进行了进一步的说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡是在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

1.一种场效应晶体管，包括底栅结构、InGaAs沟道层、顶栅结构，其特征在于，还包括下界面控制层和上界面控制层，所述的下界面控制层位于所述底栅结构和InGaAs沟道层之间，所述的上界面控制层位于所述顶栅结构和InGaAs沟道层之间。
2.根据权利要求1所述的场效应晶体管，其特征在于，所述的上界面控制层和所述的下界面控制层的厚度范围均介于单个原子层到20nm之间。
3.根据权利要求1所述的场效应晶体管，其特征在于，所述的上界面控制层和下界面控制层禁带宽度大于所述InGaAs沟道层材料，均具有第一类量子阱能带对准关系。
4.根据权利要求1所述的场效应晶体管，其特征在于，所述的InGaAs沟道层的厚度为1-20nm，In组分为低In组分，组分为0.2-0.4之间。
5.根据权利要求1所述的场效应晶体晶体管，其特征在于，所述的InGaAs沟道层中空穴具有量子限制效应。
6.根据权利要求1所述的场效应晶体管，其特征在于，所述的底栅结构包括底栅电极和底栅介质层。
7.根据权利要求6所述的场效应晶体管，其特征在于，所述的底栅电极包括电极金属层和功函数层。
8.根据权利要求1所述的场效应晶体管，其特征在于，所述的顶栅结构包括顶栅电极、顶栅介质层、欧姆接触层、高掺杂P型GaAs层和源漏金属电极。
9.根据权利要求8所述的场效应晶体管，其特征在于，所述的顶栅电极包括电极金属层和功函数层。
10.根据权利要求8所述的场效应晶体管，其特征在于，所述的欧姆接触层采用重掺杂的InGaAs材料，掺杂浓度大于1e19cm-3。
11.根据权利要求8所述的场效应晶体管，其特征在于，所述的高掺杂P型GaAs层，掺杂浓度大于1e18cm-3。
12.根据权利要求8所述的场效应晶体管，其特征在于，所述的高掺杂P型GaAs层与所述InGaAs沟道层的晶格为匹配或者赝配关系。
13.根据权利要求8所述的场效应晶体管，其特征在于，所述的欧姆接触层和高掺杂GaAs层中形成栅槽结构，栅槽结构内表面均匀覆盖有一层顶栅介质层；在顶栅介质层上具有顶栅电极，源漏金属电极分布在欧姆接触层两端。
14.根据权利要求13所述的场效应晶体管，其特征在于，所述的顶栅介质层和底栅介质层的介电常数K大于8。
15.根据权利要求14所述的场效应晶体管，其特征在于，所述的顶栅介质层或底栅介质层采用的材料包括氧化物、氮化物、氮氧化物、以及它们的任意混合、或者多层任意组合。
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