CN101681852B - 具有互连导电体的倒装芯片及其制作方法 - Google Patents

具有互连导电体的倒装芯片及其制作方法 Download PDF

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CN101681852B
CN101681852B CN200880016609.0A CN200880016609A CN101681852B CN 101681852 B CN101681852 B CN 101681852B CN 200880016609 A CN200880016609 A CN 200880016609A CN 101681852 B CN101681852 B CN 101681852B
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interconnect conductive
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江东必
戴维·J·科里西斯
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Micron Technology Inc
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Abstract

本发明揭示一种装置，其包含包括集成电路的裸片及耦合到所述裸片的互连导电体，所述互连导电体具有比所述裸片的占用面积小的占用面积。本发明揭示一种方法，其包含将互连导电体以操作方式耦合到包括集成电路的裸片，所述互连导电体具有比所述裸片的占用面积小的占用面积，及用底填充材料填充所述互连导电体与所述裸片之间的空间。

Description

具有互连导电体的倒装芯片及其制作方法
技术领域
本文中所揭示的标的物一般来说针对集成电路装置的封装领域，且更明确地说针对具有互连导电体的经组装倒装芯片及其各种制造方法。
背景技术
集成电路技术使用(例如)晶体管、电阻器、电容器等电子装置来规划设计巨大的功能电路阵列。这些电路的复杂性需要使用不断增加数目的链接式电子装置以使得所述电路可执行其预定功能。随着晶体管数目的增加，集成电路尺寸缩小。半导体工业中的一个挑战是开发用于电连接及封装制作于相同及/或不同晶片或芯片上的电路装置的经改善方法。一般来说，在半导体工业中想要构造在硅芯片/裸片上占据较小表面积的晶体管。
在半导体装置组合件的制造中，单个半导体裸片最普遍地并入到每一所密封封装中。使用许多不同封装方式，包含双列直插式封装(DIP)、Z字形直插式封装(ZIP)、小外形J型接脚(SOJ)、薄形小外形封装(TSOP)、塑料有引线芯片载体(PLCC)、小外形集成电路(SOIC)、塑料四列平面封装(PQFP)及交指型引线框(IDF)。一些半导体装置组合件在囊封之前连接到衬底，例如电路板。制造商在恒压下减小所封装集成电路装置的大小且增加封装集成电路装置中的封装密度。
存在许多其中多个集成电路裸片附装到通常称为多芯片模块的单个模块的应用。在一些情况中，已采用传统倒装芯片技术来将集成电路裸片电耦合到所述模块。在一些情况中，在所述裸片附装到所述模块之后，将底填充材料定位于所述集成电路裸片与所述模块之间以致力于增强所述集成电路裸片与所述多芯片模块之间的导电连接的稳定性。通常，通过如下操作施加底填充材料：施与一定数量的底填充材料且使所述底填充材料芯吸于集成电路裸片下并填充裸片与多芯片模块之间的空间。此后，固化所述底填充材料。使用此种底填充材料可耗时且昂贵的，尤其当在大的表面积上需要其时。
发明内容
附图说明
可通过结合附图参照以下描述来理解本发明，其中相同参考编号识别相同元件，且在附图中：
图1及图2描绘本文中所述的集成电路裸片及互连导电体的实施例的各种视图；
图3是说明性多芯片模块的平面图；且
图4到9描绘用于形成本文中所揭示的装置的说明性工艺流程。
虽然本文中所揭示的标的物容许各种修改及替代形式，但已在这些图式中以实例方式显示了其具体实施例且在本文中对其进行详细描述。然而，应理解，本文中对具体实施例的描述并非打算将本发明限于所揭示的特定形式，而是相反，本文将涵盖归属于如由所附权利要求书所界定的本发明的精神及范围内的所有修改、等效内容及替代内容。
具体实施方式
为清楚起见，本说明书并不包含本文中所揭示的装置及方法的实际实施方案的所有特征的详细描述。当然应了解，在任一此种实际实施例的开发中，必须做出许多实施方案特定的决定以实现开发者的特定目标，例如遵照系统相关及商务相关限制，其将随实施方案而变化。此外，应了解，此开发工作可能是复杂且耗时的，但对于受益于本发明的所属领域的技术人员来说，其将不过是常规任务而已。
虽然这些图式中所示的各种区域及结构描绘为具有极精密、清楚的配置及轮廓，但所属领域的技术人员实际上认识到，这些区域及结构并不像这些图式中所指示的那样精密。另外，如与所制作装置上的那些特征或区域的大小相比较，可扩大或减小这些图式中所描绘的各种特征及经掺杂区域的相对大小。然而，包含这些所附图式以描述及解释本文中所揭示的标的物的说明性实例。
图1及图2分别是装置10的横截面视图及底视图，装置10包括通过多个导电结构15(例如，焊料球等)以导电方式耦合到互连导电体14的集成电路裸片12。底填充材料16填充裸片12与互连导电体14之间的开放区域。出于清楚目的，已从图2省略所述底填充材料。在所描绘的实施例中，暴露裸片12的背侧18。然而，在其它应用中，背侧18可覆盖有封装材料，例如，模制化合物、胶带、聚合物涂层等。互连导电体14的表面17定位成与裸片12的表面19相对。多个导电结构22(例如，焊料球)以导电方式耦合到形成于互连导电体14的表面13上的多个接合垫35。
在所描绘的实施例中，装置10以导电方式耦合到说明性印刷电路板30的安装表面24。在一个实例中，印刷电路板30是多芯片模块的一部分。更具体地说，导电结构22(例如，焊料球)咬合印刷电路板30上的说明性接合垫33。如图3中所示，装置10可连同多个其它示意性描绘的集成电路裸片40一起安装于印刷电路板30上。当然，安装于印刷电路板30上的集成电路裸片40的确切数目及类型将依据特定应用而变化。
如图2中最佳所见，互连导电体14具有比裸片12的占用面积或水平表面积小的占用面积或水平表面积。裸片12的主表面19(例如，水平表面)界定第一面积，而主互连导电体表面17或13(例如，水平表面)界定第二面积，其中所述第二面积小于所述第一面积。在所描绘的实施例中，互连导电体14对称地定位于裸片12上以便在互连导电体14的边缘与裸片12的凸出边缘之间存在均匀间距25。间距25的量值将依据特定应用而变化。在一个说明性实例中，间距25可介于0.1-1mm之间。应理解，间距25无需均匀，例如，互连导电体14无需对称地位于裸片12上。例如，互连导电体14的一个边缘14E可大致对准于裸片12的边缘12E。互连导电体14相对于裸片12的其它不对称布置也可行。
如上文所指示，图1及图2中所描绘的装置打算在本质上具有代表性。例如，集成电路裸片12可由多种不同类型的集成电路装置中的全部或一部分组成，例如，存储器装置、逻辑装置、微处理器、应用专用集成电路(ASIC)等。类似地，可由多种已知结构或技术中的任一者提供裸片12与互连导电体14之间的导电结构15。例如，布线图案(例如，重分布层，未显示)可形成于裸片12的表面19上且耦合到多个接合垫39。导电结构15(例如，焊料球)可使用已知技术耦合到裸片12的接合垫39。导电结构15依图案布置以使其匹配互连导电体14的表面17上的对应接合垫29。当然，裸片12与互连导电体14之间的电连接可使用多种技术中的任一者达成，例如，金到金结合等。
以类似风格，导电结构22可具有使得互连导电体14能够电耦合到印刷电路板30的安装表面24的任一类型的结构。在所描绘的实施例中，导电结构22为耦合到形成于互连导电体14上的说明性接合垫35的多个焊料球。在一个实例中，导电结构22(例如，焊料球)经定大小及配置以便在互连导电体14与印刷电路板30之间不需要底填充材料。例如，导电结构22可配置为传统球栅阵列(BGA)，且球22可具有约420-450μm的直径。接合垫33及35可相对大，例如，其可具有约330-350μm的直径。依据特定应用，互连导电体14可由多种不同材料组成，例如，双马来酰亚胺三嗪(BT)、FR4、FR5等。互连导电体14的厚度也依据特定应用而变化，例如，100-300μm。
现将参照图4到9描述用于制造装置10的一个说明性技术。图4描绘由多个说明性集成电路裸片12组成的说明性半导体衬底或晶片50。出于清楚目的，在图4中仅描绘十二个此种裸片12。在实际实践中，可存在形成于衬底50上的数百个此种裸片12，例如，300-600个裸片。图4中所描绘的裸片12处于正好在导电结构15(例如，焊料球)形成于裸片12上的时刻之前的制造阶段。如上文所阐明，导电结构15的确切性质可依据特定应用而变化。例如，重分布层(未显示)可形成于裸片12上以电耦合裸片12上的接合垫(未显示)与在所述重分布层形成之后形成的焊料球15。图5描绘在多个示意性描绘的导电结构15(例如，焊料球)已形成于裸片12的表面19上之后的衬底50。如上所述，多种不同类型的导电结构15中的任一者可形成于裸片12上以准许将裸片12电耦合到另一结构(例如互连导电体14)，且此种导电结构15可使用多种已知技术形成。在形成说明性导电结构15之后，个别裸片12可经受各种电测试以确定哪些裸片可接受(已知良好的裸片)和那些不可接受的(坏裸片)。
图6是面板14A的平面图，多个互连导电体14将通过沿切割线21切割所述面板而由其制造。图7是互连导电体14在其从面板14A切割之后的一个实施例的横截面视图。在一个实施例中，导电结构22(例如，焊料球)形成于表面13的接合垫35上，而互连导电体14仍呈面板14A的形式。在形成导电结构22之后，可沿说明性切割线21切割面板14A。
接着，如图8中所示，个别互连导电体14(图7中所示的互连导电体)放置于衬底50上的裸片12中的每一者上。互连导电体14仅放置于已知良好的裸片上。在图8中所描绘的实例中，裸片31为坏裸片，亦即，未通过一个或一个以上电测试的裸片。互连导电体14不定位于坏裸片12上。在将个别互连导电体14定位于已知良好的裸片12上之前，可将助熔材料施加到裸片12以为表面17上的接合垫29与裸片12上的导电结构15之间的附装确保可润湿表面。在互连导电体14附装到已知良好的裸片之后，执行回流过程以使焊料块15回流且从而在裸片12与互连导电体14之间建立电连接。另一选择为，互连导电体14可放置于坏裸片31上以确保施加底填充材料的更均匀流动，如下文更完全地描述。
接着，如图9中所示，使用底填充材料16来底填充互连导电体14与裸片12之间的空间。底填充材料16可在在单片化裸片12之前(亦即，在晶片级上)施加，或其可在单片化裸片12之后施加。底填充材料16可由多种已知材料组成，且其可使用多种已知技术施加。在所描绘的实例中，固化底填充材料16且使衬底50经受其中单片化装置10(包括裸片12及互连导电体14)的切片操作，如图1中所反映。装置10可接着使用多种已知技术附装到印刷电路板30。如上文所阐明，焊料球22经定大小及定位以使得互连导电体14可电耦合到印刷电路板30而无需在互连导电体14与印刷电路板30之间提供底填充16。

Claims (26)

1.一种集成电路装置，其包括：
裸片，其包括集成电路，所述裸片具有多个裸片边缘；及
互连导电体，其耦合到所述裸片，其中所述互连导电体具有由多个互连导电体边缘界定的占用面积，所述互连导电体的所述占用面积小于所述裸片的占用面积且所述互连导电体相对于所述裸片对称地定位以使得裸片边缘与毗邻互连导电体边缘之间的间距均匀。
2.如权利要求1所述的装置，其进一步包括印刷电路板，所述印刷电路板包括至少一个额外裸片，所述至少一个额外裸片以操作方式耦合到所述印刷电路板，其中所述互连导电体以操作方式耦合到所述印刷电路板。
3.如权利要求1所述的装置，其进一步包括定位于所述互连导电体与所述裸片之间的底填充材料。
4.如权利要求2所述的装置，其中所述互连导电体与所述印刷电路板之间的空间无任何底填充材料。
5.如权利要求1所述的装置，其中所述裸片通过多个焊料球电耦合到所述互连导电体。
6.如权利要求2所述的装置，其中所述互连导电体通过多个焊料球电耦合到所述印刷电路板。
7.如权利要求6所述的装置，其中所述互连导电体与所述印刷电路板之间的空间无任何底填充材料。
8.一种集成电路装置，其包括：
裸片，其包括集成电路；
互连导电体，其耦合到所述裸片，所述互连导电体具有比所述裸片的占用面积小的占用面积，且所述互连导电体相对于所述裸片定位以使得所述互连导电体的边缘与所述裸片的对应边缘之间的间距相等；
底填充材料，其在所述互连导电体与所述裸片之间；及
印刷电路板，其包括至少一个额外裸片，所述至少一个额外裸片以操作方式耦合到所述印刷电路板，其中所述互连导电体以操作方式耦合到所述印刷电路板，且其中所述互连导电体与所述印刷电路板之间的空间无任何底填充材料。
9.一种集成电路装置，其由如下部分组成：
裸片，其包括集成电路，所述裸片具有界定第一表面积的由裸片边缘限制的主表面；及
互连导电体，其耦合到所述裸片，所述互连导电体具有界定第二面积的由互连导电体边缘限制的主互连导电体表面，其中所述第二面积小于所述第一表面积，且其中所述互连导电体的相对侧上的互连导电体边缘与所述裸片的相对侧上的对应裸片边缘间隔开均匀距离。
10.如权利要求9所述的装置，其进一步包括印刷电路板，所述印刷电路板包括至少一个额外裸片，所述至少一个额外裸片以操作方式耦合到所述印刷电路板，其中所述互连导电体以操作方式耦合到所述印刷电路板。
11.如权利要求9所述的装置，其进一步包括定位于所述互连导电体与所述裸片之间的底填充材料。
12.如权利要求10所述的装置，其中所述互连导电体与所述印刷电路板之间的空间无任何底填充材料。
13.如权利要求9所述的装置，其中所述裸片通过多个焊料球电耦合到所述互连导电体。
14.如权利要求10所述的装置，其中所述互连导电体通过多个焊料球电耦合到所述印刷电路板。
15.如权利要求14所述的装置，其中所述互连导电体与所述印刷电路板之间的空间无任何底填充材料。
16.一种用于制作集成电路装置的方法，其包括：
将互连导电体以操作方式耦合到包括集成电路的裸片，所述互连导电体具有比所述裸片的占用面积小的占用面积且所述互连导电体相对于所述裸片对称地定位以使得裸片边缘与毗邻互连导电体边缘之间的间距均匀；及
用底填充材料填充所述互连导电体与所述裸片之间的空间。
17.如权利要求16所述的方法，其进一步包括将所述互连导电体以操作方式耦合到印刷电路板。
18.如权利要求17所述的方法，其中所述印刷电路板是用于多芯片模块的印刷电路板。
19.如权利要求17所述的方法，其中执行将所述互连导电体以操作方式耦合到所述印刷电路板的所述步骤，使得所述互连导电体与所述印刷电路板之间的空间无任何底填充材料。
20.如权利要求19所述的方法，其进一步包括将至少一个额外裸片以操作方式耦合到所述印刷电路板。
21.一种用于制作集成电路装置的方法，其包括：
形成多个互连导电体；
在单片化衬底上的多个裸片之前，将单个互连导电体以操作方式耦合到所述多个裸片中的每一者，所述裸片中的每一者包括集成电路；
其中所述互连导电体具有比所述裸片的占用面积小的占用面积；且
其中所述互连导电体的相对侧上的互连导电体边缘与所述裸片的相对侧上的对应裸片边缘间隔开均匀距离；及在单片化所述多个裸片之前，将底填充材料引入所述互连导电体与所述多个裸片之间。
22.如权利要求21所述的方法，其进一步包括固化所述底填充材料。
23.如权利要求22所述的方法，其进一步包括单片化所述多个裸片。
24.如权利要求21所述的方法，其中所述衬底上的所述多个裸片包括多个已知良好的裸片，且其中互连导电体仅以操作方式耦合到已知良好的裸片。
25.如权利要求21所述的方法，其中形成所述多个互连导电体包括由单个材料面板形成所述多个互连导电体。
26.如权利要求21所述的方法，其中形成所述多个互连导电体包括在材料面板上形成用于多个互连导电体的多个导电连接，且在形成所述导电连接之后，切割所述材料面板以单片化所述互连导电体。
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US20100109149A1 (en) 2010-05-06
US8178984B2 (en) 2012-05-15
US20080251943A1 (en) 2008-10-16
US7659151B2 (en) 2010-02-09
WO2008127985A1 (en) 2008-10-23
CN101681852A (zh) 2010-03-24
KR20100005112A (ko) 2010-01-13
TWI411065B (zh) 2013-10-01
TW200908243A (en) 2009-02-16

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