TWI411065B - 具有插入器之覆晶晶片，以及製造其之方法 - Google Patents

具有插入器之覆晶晶片，以及製造其之方法 Download PDF

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TWI411065B
TWI411065B TW097113428A TW97113428A TWI411065B TW I411065 B TWI411065 B TW I411065B TW 097113428 A TW097113428 A TW 097113428A TW 97113428 A TW97113428 A TW 97113428A TW I411065 B TWI411065 B TW I411065B
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interposer
die
circuit board
printed circuit
edge
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TW200908243A (en
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David J Corisis
Tongbi Jiang
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Micron Technology Inc
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Description

具有插入器之覆晶晶片，以及製造其之方法
本發明主要係與積體電路器件之封裝領域相關，更具體而言係關於一具有插入器之封裝覆晶晶片及其各種製造方法。
積體電路技術使用電子器件(如，電晶體，電阻器，電容器，等等)來定義大陣列的功能電路的。此類電路的複雜性要求使用越來越多的相連結之電子器件，以便該電路可以發揮其理想功能。所使用電晶體越多，該積體電路之尺寸越小。半導體工業中存在的挑戰之一就是要開發電氣連接和封裝電路器件(形成於相同和/或不同晶圓或晶片上)之改良方法。總之，在半導體工業有必要構建占用更少矽晶片/晶粒表面積的電晶體。
在半導體器件裝置的製造中，每個密閉的封裝內通常都併入一單個半導體積體晶粒。會用到許多不同的封裝形式，包括雙列直插式封裝(DIP)、曲折式線內封裝(ZIP)、小外型J接腳封裝(SOJ)、薄小外型封裝(TSOP)、塑膠引線晶片載體(PLCC)、小外型積體電路(SOIC)、塑膠四方平面封裝(PQFP)及交叉導線框(IDF)。一些半導體器件裝置在封裝之前被連接至一基板，如一電路板。製造者在積體電路器件的封裝上一直都有減小封裝積體電路器件尺寸及增加封裝密度方面的壓力。
有許多應用，複數個積體電路晶粒被連接至一單一模組 而被稱為多晶片模組。在一些情況下，傳統的覆晶晶片技術被應用與將一積體電路晶粒與一模組電耦合。在一些情況下，該積體電路晶粒連接至該模組後，一種側填滿材料被置於該積體電路晶粒與該模組之間以加強該積體電路晶粒與該多晶片模組之間傳導連接的穩定性。該側填滿材料之主要應用係藉由使用一些該側填滿材料並使其鋪墊於該積體電路晶粒下面並填充晶粒與該多晶片模組間之空隙。然後將該側填滿材料固化。此類側填滿材料的使用既耗時花費又高，尤其是在有大面積表面區域的要求之時。
為清晰起見，該說明不包括對本文所揭示之器件及方法實際實施之所有特性的詳細描述。應瞭解，任何該種實際實施例之開發過程中，需要作出許多的特別的實施決定來達到開發者之特別目的，如遵從與系統或商業相關的限制，各種實施之間都互不相同。然而，應瞭解，此種開發之努力會複雜且耗時，不過對與那些擁有本發明優點之一般技術者不過是一個常規的工作。
儘管圖示所示之許多區域和結構都描繪的非常簡潔，清晰的構形及輪廓，然而熟悉此項技術者都知道，實際上這些區域和結構並不如圖示所示那麼簡潔。此外，各圖示所描繪之不同特點及摻雜區的相關尺寸與製成的器件相比會有放大或縮小。不過，其中包含有附圖用來描述並揭示本文所揭示之發明之示例。
圖1與圖2分別係一包含一積體電路晶粒12之器件10之截 面圖和一仰視圖，該積體電路晶粒12係藉由複數個傳導結構15(如，焊球等)與一插入器14電導耦合。側填滿材料16將晶粒12與插入器14之間的敞開區域填滿。為清晰顯示器件，該側填滿材料在圖2中略去未標出。在圖示之實施例中，晶粒12之背面18係曝露。不過，該背面18可以用封裝材料覆蓋(如在其他應用中使用模塑膠，帶子，聚合物塗層等)。插入器14之表面17與晶粒12之表面19相對。複數個傳導結構22(如，焊球)與該插入器14表面13所組成之複數個焊墊35傳導性耦合。
在圖示之實施例中，該器件10與一示例印刷電路板30之安裝面24電導耦合。在一個例子中，該印刷電路板30係一多晶片模組之一部分。更具體的說，該等傳導結構22(如焊球)將圖示焊墊33焊接在該印刷電路板30上。如圖3所示，該器件10與一其他圖示所示之複數個積體電路晶粒40一起加在該印刷電路板30上。當然，加在印刷電路板30上之積體電路晶粒40之確切數量及類型取決於特定應用而異。
在圖2中能清楚看到，該插入器14的佔據面積或水平表面區域小於晶粒12的佔據面積或水平表面區域。晶粒12之主要表面19(例如，一水平表面)界定了一第一區域，而一主要插入器表面17或13(例如，一水平表面)界定一第二區域，其中該第二區域係小於該第一區域。在圖示之實施例中，該插入器14是對稱地置於晶粒12之上以致使介於插入器14之邊緣與晶粒12之突出邊緣之間有一一致空隙。該空 隙25之大小取決於特定應用而異。在一示例中，該空隙25之大小範圍在0.1毫米至1毫米之間。應瞭解該空隙25非必須一致，例如，插入器14非必須對稱地置於晶粒12上。例如，插入器14的一邊緣14E可能與晶粒12的一邊緣12E大致對準。插入器14相對於晶粒12之其他不對稱的配置均有可能。
正如前文所指出，圖1與圖2所示之器件係希望作為代表性器件。例如，該積體電路晶粒12可以是由各種不同積體電路器件之全部或一部分組成，例如，一記憶體器件、一邏輯器件、一微處理器、一有特殊用途的積體電路(ASIC)等。類似地，可藉由各種已知結構或技術之任一者來提供介於晶粒12與插入器14之間之傳導結構15。例如，一佈線圖案(諸如一重佈層)(圖中未顯示)可形成於晶粒12之表面1上並且耦合至複數個焊墊39。可以用已知技術將該等傳導結構15(例如，焊球)耦合至晶粒12之焊墊39。該等傳導結構15係以致使其相匹配於該插入器14之該表面17上的相對應焊墊29的圖案予以配置。當然，可以使用許多技術中之任一者(如金至金接合)等來達成介於晶粒12與插入器14之間的電連接。
同樣，該等傳導結構22可以是能夠將該插入器14電耦合至該印刷電路板30之安裝表面24的任何結構類型。在圖示之實施例中，該等傳導結構22係耦合至形成於該插入器14上的圖示之焊墊35的複數個焊球。在一實例中，該等傳導結構22(例如，焊球)經訂定尺寸及經組態以致使插入器14 與印刷電路板30之間不需要側填滿材料。例如，該等傳導結構22可經組態為傳統的球格陣列(BGA)，並且該等球22的直徑可以係大約420微米至450微米。焊墊33及35可相對大，例如，其直徑可以係大約330微米至350微米之間。插入器14可取決於特定應用而由各種不同材料構成，如雙馬來醯亞胺三(bismaleimide triazine，BT)、FR4、FR5等。該插入器14的厚度亦根據具體應用而不同，如100微米至300微米之間。
現將描述製造該器件10之一種示例技術，參考圖4至圖9。圖4所示係一由複數個積體電路晶粒12所組成的示例半導基板或晶圓50。為清晰起見，圖4所示僅12塊該種晶粒12。在實務中，在該基板50上可能有幾百塊該種晶粒12，如，300塊至600塊晶粒。圖4所示晶粒12係正好在該等傳導結構15(例如，焊球)正被形成在晶粒12上之前的製造階段。正如前文所提到，該等傳導結構15之確切本質取決於特定應用而不同。例如，可在晶粒12上形成一個重佈層(圖中未顯示)以電耦合晶粒12上之焊墊(圖中未顯示)至在該重佈層形成後所形成之焊球15。圖5所示係在已在晶粒12之表面19形成複數個示例傳導結構15(例如，焊球)後的基板50。如前文中所提到，可以在晶粒12上形成各種不同類型之傳導結構15中之任一者，使晶粒12電耦合至另一結構(諸如插入器14)，且可使用任何已知技術形成該等傳導結構15。形成示例傳導結構15後，個別晶粒12可歷受各種電測試以決定哪些晶粒係可接受的(良品晶粒)和哪些晶粒 是不可接受的(非良品晶粒)。
圖6係一面板14A的俯視圖，藉由沿著切割線21切割該面板而製造複數個插入器14。圖7係自面板14A上切割後的插入器14之一實施例的截面圖。在一實施例中，該等傳導結構22(例如，焊球)係形成在表面13上的焊墊35上面，而該等插入器14仍然是以該面板14A的形式。在該等傳導結構22形成後，可沿圖示之切割線21切割該面板14A。
接下來，如圖8所示，基板50上之各個晶粒20上都置放一單個插入器14(圖7中所示)。該等插入器14僅置放在良品晶粒上。圖8所示之例子中，晶粒31是非良品晶粒(指一次或多次電測試未通過的晶粒)。插入器14不會被置放在非良品晶粒12上。在將個別插入器14置放在良品晶粒12上之前，一種焊劑被施用於晶粒12上以確保表面17上的焊墊29與晶粒12上之傳導結構15之間有一個可濕的附著表面。在插入器14被附著在良品晶粒上以後，實施一以回熔處理來回熔焊凸塊15並由此來建立晶粒12與插入器14之間的電連接。或者，插入器14可以置放在非良品晶粒31之上，以確保將要用到之側填滿材料更均勻地分佈，這將在下文中有更全面的描述。
接下來，如圖9所示，一種側填滿材料16被用於填充插入器14和晶粒12之間的空隙。該側填滿材料16在分離(singulate)晶粒12之前使用，如，以晶圓大小的量，或者亦可在晶粒12分離後再用。該側填滿材料16可以由許多已知材料組成，且其可使用多種已知技術而被應用。在圖示 的例子中，該側填滿材料16被固化且該基板50要經過晶圓切割操作，如此一來該器件10(包括晶粒12和插入器14)就被分離，如圖1所示。該器件10可以用許多已知技術附著在該印刷電路板30上。如前文所述，該焊球22的尺寸和安置可以使該插入器14電耦合至該印刷電路板30而不需在插入器14和該印刷電路板30之間提供側填滿材料16。
10‧‧‧器件
12‧‧‧積體電路晶粒
13‧‧‧插入器之接觸面
14‧‧‧插入器
15‧‧‧複數個傳導結構
16‧‧‧側填滿材料
17‧‧‧插入器之外表面
18‧‧‧積體電路晶粒之背面
19‧‧‧積體電路晶粒之接觸面
22‧‧‧傳導結構
24‧‧‧印刷電路板之安裝面
29‧‧‧焊墊
30‧‧‧印刷電路板
33‧‧‧焊墊
35‧‧‧焊墊
39‧‧‧焊墊
40‧‧‧積體電路晶粒
50‧‧‧基板
12E‧‧‧積體電路晶粒之邊緣
14A‧‧‧面板
14E‧‧‧插入器之邊緣
本發明可藉由參考以下與附圖一起之描述來幫助理解，其中相關參考數據表示相關元件，其中：圖1和圖2所描繪係本文所述之積體電路晶粒和插入器之各種視圖；圖3係一多晶片模組之設計示意圖；及圖4至圖9所示係組成本發明之器件之流程示意圖。
然而本文所揭示之本發明還可以有多種修改及選擇形式，與此相關之具體實施例已藉由圖示之例子及此處之詳細描述顯示。但是，應瞭解，本文對具體實施例之描述並非意圖限制所揭示之特別形式之發明，相反地，本發明意在涵蓋由附加請求項限定之本發明精神及範疇內的所有修改、等效件及替代件。
10‧‧‧器件
12‧‧‧積體電路晶粒
13‧‧‧插入器之接觸面
14‧‧‧插入器
15‧‧‧複數個傳導結構
16‧‧‧側填滿材料
17‧‧‧插入器之外表面
18‧‧‧積體電路晶粒之背面
19‧‧‧積體電路晶粒之接觸面
22‧‧‧傳導結構
24‧‧‧印刷電路板之安裝面
29‧‧‧焊墊
30‧‧‧印刷電路板
33‧‧‧焊墊
35‧‧‧焊墊
39‧‧‧焊墊

Claims (26)

  1. 一種覆晶晶片器件，其包括：一晶粒，其包括一積體電路，該晶粒具有複數個晶粒邊緣；及一插入器，其耦合至該晶粒，其中該插入器具有由複數個插入器邊緣所界定之一佔據面積，該插入器之該佔據面積小於該晶粒之佔據面積，及該插入器係相對於該晶粒呈對稱地定位，使得在晶粒邊緣與相鄰插入器邊緣之間的空隙係一致的。
  2. 如請求項1之器件，其進一步包括一印刷電路板，該印刷電路板包括可操作地耦合至該印刷電路板之至少一附加晶粒，其中該插入器係可操作地耦合至該印刷電路板。
  3. 如請求項1之器件，其進一步包括一置於該插入器與該晶粒之間的側填滿材料。
  4. 如請求項2之器件，其中該插入器與該印刷電路板之間的一空隙未具有任何側填滿材料。
  5. 如請求項1之器件，其中該晶粒係藉由複數個焊球電耦合至該插入器。
  6. 如請求項2之器件，其中該插入器係藉由複數個焊球電耦合至該印刷電路板。
  7. 如請求項6之器件，其中該插入器與該印刷電路板之間的一空隙未具有任何側填滿材料。
  8. 一種覆晶晶片器件，其包括： 一晶粒，其包括一積體電路；一插入器，其耦合至該晶粒，該插入器之佔據面積小於該晶粒之佔據面積，及該插入器係相對於該晶粒定位，使得在該插入器之邊緣與相對應之該晶粒之邊緣之間的空隙係相等的；一介於該插入器與該晶粒之間之側填滿材料；及一印刷電路板，其包括可操作地耦合至該印刷電路板之至少一附加晶粒，其中該插入器係可操作地耦合至該印刷電路板，且其中該插入器與該印刷電路板之間的一空隙未具有任何側填滿材料。
  9. 一種覆晶晶片器件，其包括：一晶粒，其包含一積體電路，該晶粒具有由晶粒邊緣所界限之界定一第一表面區域之一主表面；及一插入器，其耦合至該晶粒，該插入器具有由插入器邊緣所界限之界定一第二區域之一主要插入器表面，其中該第二區域係小於該第一區域，及其中在該插入器兩側之插入器邊緣與在該晶粒兩側之相對應之晶粒邊緣相隔一一致的距離。
  10. 如請求項9之器件，其進一步包括一印刷電路板，該印刷電路板包括可操作地耦合至該印刷電路板的至少一附加晶粒，其中該插入器係可操作地耦合至該印刷電路板。
  11. 如請求項9之器件，其進一步包括一置於該插入器與該晶粒之間的側填滿材料。
  12. 如請求項10之器件，其中該插入器與該印刷電路板之間的一空隙未具有任何側填滿材料。
  13. 如請求項9之器件，其中該晶粒係藉由複數個焊球電耦合至該插入器。
  14. 如請求項10之器件，其中該插入器係藉由複數個焊球電耦合至該印刷電路板。
  15. 如請求項14之器件，其中該插入器與印刷電路板之間的一空隙未具有任何側填滿材料。
  16. 一種組裝一覆晶晶片器件之方法，其包括：可操作地耦合一插入器至一包含一積體電路之晶粒，該插入器之佔據面積小於該晶粒之佔據面積，及該插入器係相對於該晶粒呈對稱地定位，使得在晶粒邊緣與相鄰插入器邊緣之間的空隙係一致的；及以一側填滿材料填充介於該插入器與該晶粒之間的一空隙。
  17. 如請求項16之方法，其進一步包括可操作地耦合該插入器至一印刷電路板。
  18. 如請求項17之方法，其中該印刷電路板係一用於多晶片模組之印刷電路板。
  19. 如請求項17之方法，其中可操作地耦合該插入器至一印刷電路板之該步驟係經執行而使介於該插入器與該印刷電路板之間之一空隙未具有任何側填滿材料。
  20. 如請求項19之方法，其進一步包括可操作地耦合至少一附加晶粒至該印刷電路板。
  21. 一種組裝一覆晶晶片器件之方法，包括：形成複數個插入器；在分離一基板上之複數個晶粒之前可操作地耦合一單一插入器至該複數個晶粒之各者上，每一晶粒都包括一積體電路，其中該插入器之佔據面積小於該晶粒之佔據面積，及其中在該插入器兩側之插入器邊緣與在該晶粒兩側之相對應之晶粒邊緣相隔一一致的距離；及在分離該複數個晶粒之前在該插入器與該複數個晶粒之間引入一側填滿材料。
  22. 如請求項21之方法，進一步包括將該側填滿材料固化。
  23. 如請求項22之方法，進一步包括分離該複數個晶粒。
  24. 如請求項21之方法，其中該基板上之該複數個晶粒包括複數個良品晶粒，且其中一插入器僅可操作地耦合至一良品晶粒。
  25. 如請求項21之方法，其中形成該複數個插入器包括：從一單材料面板形成該複數個插入器。
  26. 如請求項21之方法，其中形成該複數個插入器包括：為一材料面板上之複數個插入器形成複數個傳導連接，且在形成該等傳導連接後切割該材料面板來分離該等插入器。
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WO2008127985A1 (en) 2008-10-23
KR20100005112A (ko) 2010-01-13
TW200908243A (en) 2009-02-16
KR101122805B1 (ko) 2012-03-21
CN101681852A (zh) 2010-03-24
US20100109149A1 (en) 2010-05-06
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US20080251943A1 (en) 2008-10-16
US8178984B2 (en) 2012-05-15

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