CN101677087A - 半导体元件的制法 - Google Patents
半导体元件的制法 Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
本发明提供一种半导体元件的制法,包括以下步骤:形成具有第一晶体管与第二晶体管的半导体基材,其中第一晶体管具有第一虚设栅极的第一栅极结构,第二晶体管具有第二虚设栅极的第二栅极结构;移除第一与第二虚设栅极,以分别形成第一与第二沟槽;形成第一金属层以部分填充第一与第二沟槽;移除于第一沟槽中的第一金属层;形成第二金属层,以部分填充第一与第二沟槽;形成第三金属层,以部分填充第一与第二沟槽;实施热处理工艺,以回焊(reflow)第二金属层与第三金属层;以及形成第四金属层,以填充第一与第二沟槽的剩余部分。本发明提供CMOS制作流程中简单且有效方法,用以调整NMOS元件和PMOS元件的金属栅极的功函数。
Description
技术领域
本发明涉及半导体元件的制法,且特别涉及一种调整高介电常数(high-k)金属栅极元件的功函数的方法。
背景技术
半导体集成电路(integrated circuit,IC)已经历快速的发展。随着IC材料与设计上的发展,使得IC每一个世代拥有比前一个世代小且复杂的电路。然而,这些发展也提高了IC工艺的复杂度,为了实现这些先进IC,在IC的工艺上也需要对等的发展。
IC发展的过程中,当IC几何尺寸(亦即工艺所能得到的最小元件(或线))逐渐缩小的同时,功能元件的密度(亦即每单位晶片面积中的内连线元件)随的逐渐增加。尺寸缩小的好处在于增加生产效率(production efficiency)与降低相关工艺成本。然而,尺寸的缩小也产生相对较高的耗电量(powerdissipation),此问题可通过使用低耗电元件而解决,例如互补金属氧化物半导体(CMOS)元件。CMOS元件一般包括栅极氧化层与多晶硅栅极电极。当元件尺寸逐渐缩小时,为了增进元件的效能,需要将栅极氧化层与多晶硅栅极金属分别置换成高介电常数(high-k)栅极介电层与金属栅极电极。然而,NMOS元件和PMOS元件需要不同的功函数(work function)的栅极结构。方法之一包括利用盖层(capping layer)调整PMOS元件和NMOS元件的金属栅极的有效功函数。虽然此种方法可满足特定目的,但是却无法满足所有的需求。例如,盖层可能降低载子迁移率(carrier mobility),且可能使得元件性能反而受到影响。
发明内容
为克服现有技术的缺陷,本发明提供一种半导体元件的制法,包括以下步骤:提供一半导体基材;形成一第一晶体管与一第二晶体管于该半导体基材中,其中该第一晶体管具有一第一虚设栅极的第一栅极结构,该第二晶体管具有一第二虚设栅极的第二栅极结构;移除该第一虚设栅极与该第二虚设栅极,以分别形成一第一沟槽与一第二沟槽;形成一第一金属层以部分填充该第一沟槽与该第二沟槽;移除于该第一沟槽中的第一金属层;形成一第二金属层,以部分填充该第一沟槽与该第二沟槽;形成一第三金属层,以部分填充该第一沟槽与该第二沟槽;实施一热处理工艺(thermal process),以回焊(reflow)该第二金属层与该第三金属层;以及形成一第四金属层,以填充该第一沟槽与该第二沟槽的一剩余部分。
本发明另提供一种半导体元件的制法,包括以下步骤:提供一半导体基材;形成一第一晶体管与一第二晶体管于该半导体基材中,其中该第一晶体管具有一第一栅极结构,该第二晶体管具有一第二栅极结构,且该第一栅极结构与该第二栅极结构各自包括一高介电常数层形成于该半导体基材之上,一阻障层形成于该高介电常数层之上,以及一虚设多晶硅层形成于该阻障层之上;从该第一栅极结构与该第二栅极结构中移除该虚设多晶硅层,以分别形成一第一沟槽与一第二沟槽;形成一P型功函数金属层(P-metal)以部分填充该第一沟槽与该第二沟槽;移除于该第一沟槽中的P型功函数金属层;形成一钛(Ti)层,以部分填充该第一沟槽与该第二沟槽;形成一铝(Al)层,以部分填充该第一沟槽与该第二沟槽;回焊(reflow)该钛层与该铝层,以形成一铝钛(TiAl)层;以及形成一填充金属层,以填充该第一沟槽与该第二沟槽的一剩余部分。
本发明亦提供一种半导体元件的制法,包括以下步骤:提供一半导体基材;形成一第一晶体管与一第二晶体管于该半导体基材中,其中该第一晶体管具有一第一栅极结构,该第二晶体管具有一第二栅极结构,且该第一栅极结构与该第二栅极结构各自包括一高介电常数层形成于该半导体基材之上,一阻障层形成于该高介电常数层之上,以及一虚设多晶硅层形成于该阻障层之上;从该第一栅极结构与该第二栅极结构中移除该虚设多晶硅层,以分别形成一第一沟槽与一第二沟槽;形成一P型功函数金属层(P-metal)以部分填充该第一沟槽与该第二沟槽;移除于该第一沟槽中的P型功函数金属层;形成一钛(Ti)层,以部分填充该第一沟槽与该第二沟槽;形成一铝(Al)层,以部分填充该第一沟槽与该第二沟槽;回焊(reflow)该钛层与该铝层,以形成一铝钛(TiAl)层;实施一化学机械研磨工艺(CMP),用以移除位于该第一沟槽与该第二沟槽之外的的各金属层;以及形成一填充金属层,以填充该第一沟槽与该第二沟槽的一剩余部分。
本发明所公开的方法提供一种CMOS制作流程中简单且有效方法,用以调整NMOS元件和PMOS元件的金属栅极的功函数。再者,本发明所公开的方法与元件可轻易的整合于目前的CMP工艺流程与半导体配备,且不需昂贵的成本。
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合所附附图,作详细说明如下。
附图说明
图1为一流程图,用以说明本发明制备具有双金属栅极结构的半导体元件的方法。
图2A~2K为一系列剖面图,用以说明依照本发明图1所示方法的各个工艺阶段。
并且,上述附图中的附图标记说明如下:
100~半导体元件的制法
102~提供具有第一区域与第二区域的半导体基材
104~形成一高介电常数(high-k)层于基材之上
106~形成阻障层于高介电常数层之上
108~形成半导体层于阻障层之上
110~于第一区域形成第一栅极堆叠,以及于第二区域形成第二栅极堆叠
111~于第一与第二栅极堆叠的侧壁形成侧壁间隙壁
112~从第一栅极堆叠移除半导体层以形成第一沟槽,以及从第二栅极堆叠移除半导体层以形成第二沟槽
114~形成第一金属层于第二沟槽中的阻障层之上
116~形成第二金属层于第一沟槽中的阻障层之上,并形成于第二沟槽的第一金属层之上
118~形成第三金属层于第一沟槽与第二沟槽的第二金属层之上
120~实施一热处理工艺以回焊(reflow)第二金属层与第三金属层
122~形成第四金属层以填充第一沟槽与第二沟槽剩余的部分
124~实施化学机械研磨工艺(CMP)
200~半导体元件
202~半导体基材
204~隔离结构
206、208~有源区域
212、212n、212p~高介电常数层
216、216n、216p~阻障层
218、218n、218p~多晶硅层
220、220n、220p~硬掩模层
221、222~图案
231、232~栅极堆叠
234~栅极间隙壁
236~S/D区域
238~层间介电层(ILD)
241n、241p~沟槽
244~氮化钛层
246~氮化钨层
250~铝层
251~热处理工艺
252~铝层
具体实施方式
以下特举出本发明的实施例,并配合所附附图作详细说明。以下实施例的元件和设计是为了简化所公开的发明,并非用以限定本发明。举例而言,说明书中提及形成第一特征位于第二特征之上,其包括第一特征与第二特征是直接接触的实施例,另外也包括于第一特征与第二特征之间另外有其他特征的实施例,亦即,第一特征与第二特征并非直接接触。此外,为了简化与清晰的目的,各种特征可能用不同的尺寸简化地绘出。此外,本发明所公开的实施例是“后栅极”金属工艺,然而,本领域普通技术人员可应用于其他工艺及/或使用其他材料。
依照本发明所公开的各种实施例,图1显示具有双栅极结构的半导体元件的制作方法100的流程图。依照图1所示的方法100,图2A至图2K显示半导体元件200于各个工艺阶段的剖面图。须注意的是,为了强调分别形成NMOS元件和PMOS元件的双金属栅极结构,因此图2A至图2K的图示已经过简化。再者,部分的半导体元件200可以使用一般CMOS的制造流程。据此,须了解的是,于图1方法100之前,期间或之后可提供额外的工艺,且某些其他工艺在此仅作简单陈述。可利用后栅极工艺制备半导体元件200(也称为取代多晶硅栅极工艺)。于后栅极工艺,先形成虚设多晶硅栅极结构,接着,进行一般CMOS制造流程,直到沉积层间介电层(interlayer dielectric,ILD)。之后,虚设多晶硅栅极结构可被移除,并且被金属栅极结构所取代。
半导体元件的制作方法100起始于方块102,其提供具有第一区域与第二区域的半导体基材。于图2A中,半导体元件200可包括一半导体基材202,例如硅基材。此基材202可另外包括硅化锗、砷化镓、或其他适合的半导体材料。基材202还可包括其他特征,例如各种掺杂区域,如p型阱或n型阱,阻障层,及/或外延层。再者,基材202可以是位于绝缘体上的半导体,例如绝缘层上覆硅(silicon on insulator,SOI)。于另外的实施例中,半导体基材202可包括一掺杂外延层,一梯度(gradient)半导体层,及/或还可包括一半导体层位于另一不同类型的半导体层之上,例如硅层位于硅化锗层之上。于其他实施例中,一化合物半导体基材可包括多层硅结构,或者是含有多层化合物半导体结构的硅基材。
半导体元件200还可包括一绝缘结构(图中未显示)204,例如浅沟槽隔离结构(shallow trench isolation,STI)形成于基材202之中,用以隔离基材202中的有源区域206和208。隔离结构204可由氧化硅,氮化硅,氮氧化硅,掺杂氟的硅酸盐(FSG),及/或本领域熟知的低介电常数(low k)材料所组成。有源区域206可用来形成NMOS元件,而有源区域208可用来形成PMOS元件。
半导体元件200还包括一界面层204于基材202之上(如图2F所示)。界面层可包括厚度为约5埃到10埃的氧化硅层(由热氧化或化学氧化法形成)。界面层可通过下述方法形成:原子层沉积法(atomic layer deposition,ALD)、化学气相沉积法(chemical vapor deposition,CVD)、物理气相沉积法(physicalor sputter),热氧化法或上述的组合。另外,界面层可视需要的包括氮氧化硅(SiON)。
方法100接着进行方块104,其形成一高介电常数(high-k)层于基材之上。半导体元件200还包括一高介电常数层212形成于界面层之上。此高介电常数层212可通过原子层沉积法(ALD)、化学气相沉积法(CVD)、金属-有机CVD(MOCVD)、物理气相沉积法(PVD)、热氧化法(thermal oxidation)或上述的组合。高介电常数层212的厚度为约10埃到30埃。高介电常数层212可包括氧化铪(HfOx)。另外的,高介电常数层212可视需要的包括其他高介电常数材料,例如氧化镧(LaO)、氧化铝(AlO)、氧化锆(ZrO)、氧化钛(TiO)、氧化钽(Ta2O5)、氧化钇(Y2O3)、氧化钛锶(SrTiO3,STO))、氧化钛钡(BaTiO3,BTO)、氧化锆钡(BaZrO)、氧化锆铪(HfZrO)、氮氧化锆铪(HfZrON)、氧化镧铪(HfLaO)、氧化硅铪(HfSiO)、氮氧化硅铪(HfSiON)、氧化硅镧(LaSiO)、氧化硅铝(AlSiO)、氧化钽铪(HfTaO)、氧化钛铪(HfTiO)、钛酸(钡,锶)((Ba,Sr)TiO3,BST)、氧化铝(Al2O3)、氮化硅(Si3N4)、氮氧化物(oxynitride)或其他适合的材料。
方法100接着进行方块106,其形成阻障层于高介电常数层之上。请参见图2B,半导体元件200还包括一阻障层216形成于高介电常数层212之上。阻障层216可包括厚度为约10埃到20埃的氮化钛(TiN)。阻障层216可具有的成分为TixN(1-x),其中x等于0.43-0.57。于后续工艺步骤期间,阻障层216可作为高介电常数层212与后续形成的虚设多晶硅栅极结构之间的阻障,用以降低或消除介于多晶硅与高介电常数层之间的费米能阶钉扎效应(Femi level pinning)。再者,阻障层216于后续的蚀刻工艺可扮演停止层的角色。阻障层216可通过各种沉积工艺制得,例如物理气相沉积法(PVD或sputtering)、化学气相沉积法(CVD)、电镀(plating)或其他适合的方法。
方法100接着进行方块108,其形成多晶硅层于阻障层之上。请参见图2C,半导体元件200还包括通过合适的沉积工艺将多晶硅层218形成于阻障层216之上。多晶硅层218的厚度为约400埃到800埃。半导体元件200可包括一硬掩模层220形成于多晶硅层218之上。硬掩模层220可包括氮化硅、氮氧化硅、碳化硅、及/或其他适合的介电材料,其可通过沉积方法形成(如CVD或PVD)。硬掩模层220的厚度为约100埃到400埃。此外,为了于光刻工艺(photolithography)时帮助光致抗蚀剂层的图案化,半导体元件200可包括一抗反射层(antireflective coating layer)或底部抗反射层(bottomantireflective coating,BARC)。例如,图案化光致抗蚀剂层可形成于硬掩模层220之上,其中硬掩模层220包括一图案221位于NMOS元件206之上,以及另一图案222位于PMOS元件208之上。图案221,222可通过干式蚀刻或湿式蚀刻工艺图案化硬掩模层220。
方法100接着进行方块110,其于第一区域形成第一栅极堆叠,以及于第二区域形成第二栅极堆叠。请参见图2D,利用图案化硬掩模层于NMOS元件206中形成栅极堆叠231,于PMOS元件208中形成栅极堆叠232,形成的方法为干式蚀刻、湿式蚀刻或上述的组合。例如,硬掩模层的图案220n,220p可被转换到多晶硅层218上,用以形成虚设多晶硅栅极结构218n,218p。栅极堆叠231可包括一高介电常数层212n,一阻障层216n,一虚设多晶硅栅极218n,以及一硬掩模层220n。栅极堆叠232可包括一界面层,一高介电常数层212p,一阻障层216p,一虚设多晶硅栅极218p,以及一硬掩模层220p。
方法100接着进行方块111,其于第一与第二栅极堆叠的侧壁形成侧壁间隙壁。请参见图2E,各种特征与结构可通过本领域普通技术人员所熟知的CMOS制作流程而形成,因此在此不多着墨。例如,可形成轻掺杂源极区域(lightly doped drain regions,LDD)、侧壁或栅极间隙壁234、重掺杂源极/漏极区(S/D)236、硅化物区、接触蚀刻停止层(contact etch stop layer,CESL)、层间介电层(inter-level dielectric,ILD)238。间隙壁234可包括氧化硅、氮化硅、氮氧化硅、碳化硅、或其他适合的材料。轻掺杂源极区域(lightly doped drainregions,LDD)与重掺杂源极/漏极区(S/D)236可依据晶体管设计(亦即NMOS或PMOS)的需求注入p型或n型杂质至基材202中而得。硅化物特征可通过自对准硅化物工艺(self-aligned silicide process)形成于重掺杂源极/漏极区(S/D)236之上。接触蚀刻停止层(CESL)可包括氮化硅、氮氧化硅或其他适合的材料。可依据半导体元件200的一或多个额外的特征选择CESL的成分。ILD层238通过化学气相沉积法(CVD)、高密度等离子体(high density plasma,HDP)、物理气相沉积法(PVD)、旋转涂布法(spin-on)或其他适合的方法形成于CESL之上。ILD层238可包括氧化硅、氮氧化硅或低介电常数材料。
方法100接着进行方块112,从第一栅极堆叠与第二栅极堆叠中移除虚设多晶硅栅极,以分别形成第一沟槽与第二沟槽。请参见图2F,实施一化学机械研磨工艺(CMP)以分别曝露栅极堆叠231,232的虚设多晶硅栅极218n,218p的上表面。化学机械研磨工艺可平坦化ILD层238,以到达硬掩模层220n,220p,且可过度研磨(overpolishing)以移除硬掩模层并曝露出虚设多晶硅栅极218n,218p。可通过后蚀刻工艺、干式蚀刻、湿式蚀刻、或其他适合的方法移除于NMOS元件206中的虚设多晶硅栅极218n以及于PMOS元件208中的虚设多晶硅栅极218p。例如,湿式蚀刻工艺包括曝露于含有氢氧化物的溶液(亦即氢氧化铵),去离子水,及/或其他适合的蚀刻溶液。阻障层216n,216p于蚀刻工艺可扮演蚀刻阻障层的角色。通过选择性地蚀刻虚设多晶硅栅极218n,218p,以于栅极堆叠231中形成沟槽214n,且于栅极堆叠232中形成沟槽214p。
方法100接着进行方块114,其中第一金属层形成于第二沟槽中的阻障层之上。一或多层金属层(亦即功函数金属层)形成于PMOS元件208中的沟槽241p中。例如,P型功函数金属(P-metal)可形成于PMOS元件208的沟槽241p中。须了解的是,图2G到图2K显示NMOS元件206和PMOS元件208个别的金属栅极的详细剖面图,其中于后栅极工艺中形成金属栅极。请参见图2G,沉积氮化钛(TiN)层244以部分填充沟槽241n,241p,且其厚度可为约40埃。氮化钛(TiN)层244可通过原子层沉积法或其他适合的工艺制备而得。氮化钨(WN)层246形成于氮化钛(TiN)层244之上,用以部分填充沟槽241n,241p,且其厚度可为约50埃。氮化钨(WN)层246可通过物理气相沉积法(PVD)或其他适合的工艺制备而得。须了解的是,虽然此处举例了多层P金属层,但是P-金属层可包括单层,例如氮化钛(TiN)、氮化钨(WN)、或其他适合的金属。
请参见图2H,通过N/P图案化工艺从NMOS元件206的沟槽241n中移除氮化钛(TiN)层244与氮化钨(WN)层246。例如,为了保护PMOS元件208,因此进行N/P图案化工艺时使用光致抗蚀剂。光刻工艺(photolithography)可包括旋转涂布(spin coating)、软烘烤(soft-baking)、曝光(exposure)、后烘烤(post-baking)、显影(developing)、润洗(rinsing)、干燥(drying)、与其他适合的工艺。另外的,N/P图案化可包括湿浸式光刻(immersion lithography)、电子束光刻(electron beam lithography)或其他适合的工艺。据此,利用干式蚀刻或湿式蚀刻工艺移除于NMOS元件206中的氮化钛(TiN)层244与氮化钨(WN)层246。所以,氮化钛(TiN)层244p与氮化钨(WN)层246p(亦即P功函数金属)残留于PMOS元件208的沟槽241p中。
方法100接着进行方块116,其中第二金属层形成于第一沟槽中的阻障层之上,并形成于第二沟槽的第一金属层之上。请参见图2I,沉积钛(Ti)层248,因此钛层248形成于沟槽241n的阻障层216n之上,且钛层248形成于沟槽241p的TiN/WN层244p,246p之上。钛层248的厚度可为约30埃。钛层248可通过物理气相沉积法(PVD)制得,例如,利用ExtensaTM系统(Applied Materials,Inc of Santa,Clara,California)
方法100接着进行方块118,其中第三金属层形成于第一沟槽与第二沟槽中的第二金属层之上。于此实施例中,沉积铝(Al)层250,因此铝层250形成于沟槽241n,241p中的钛层248上。铝层250的厚度可为约70埃。铝层250可通过化学气相沉积法(CVD)或其他适合的方法制得。
方法100接着进行方块120,其中实施一热处理工艺(thermal process),用以回焊(reflow)第二金属层与第三金属层。请参见图2J,实施热处理工艺251用以回焊沟槽241n,241p中的铝层250与钛层248(亦即对铝/钛反应)。热处理工艺于约200℃~500℃的温度下进行,时间为约50秒~200秒。于NMOS元件206的金属成分可包括钛:铝为2.3∶1的比例。此外,须了解的是,钛/铝可包括其他比例。因此,回焊工艺所提供的是,将NMOS元件206与PMOS元件208中的金属栅极调整成有效的功函数。
方法100接着进行方块122,其中沉积第四金属层以填充第一沟槽与第二沟槽剩余的部分。请参见图2K,一填充金属层252,例如铝,通过往上堆积的物理气相沉积法(bottom-up PVD)或其他适合的方法,形成于沟槽241n,241p中的回焊钛/铝层248,250之上。另外,填充金属层252可视需要的包括钨(W)、铜(Cu)或其他适合的材料。可沉积填充金属层252直到沟槽241n,241p的剩余部分大体上或完全被填满。于沟槽241n(NMOS元件206)中的填充金属的含量大于沟槽241p(PMOS元件208)中的含量。因此,须注意的是,由于沟槽241p中已经有其他各种金属层,PMOS的缺口填充(gap fill)是较具挑战的。据此,于沉积后续填充金属层或其他金属层之前,可实施一额外的化学机械研磨工艺(CMP),用以平坦化并移除沟槽外的各种金属层。
方法100接着进行方块124,实施一化学机械研磨工艺(CMP)。实施化学机械研磨(亦即金属栅极CMP工艺)于各种金属之上,用以平坦化NMOS元件206和PMOS元件208中的栅极结构231,232。CMP工艺具有高度选择性,因此能提供栅极结构和ILD层大体上平坦的表面。NMOS元件206的栅极结构231可包括界面层、高介电常数层212n、氮化钛层216n、回焊的钛/铝层248,250,以及铝层252。PMOS元件208的栅极结构232可包括界面层、高介电常数层212p、氮化钛层216p、氮化钛层244p、氮化钨层246p、回焊的钛/铝层248,250,以及铝层252。据此,NMOS元件206的金属栅极可执行正确的N功函数,而PMOS元件208的金属栅极可执行正确的P功函数。因此,可轻易的达到NMOS元件206和PMOS元件208所需的临界电压(threshold voltage),用以增进元件效能与可靠度(reliability)。
须注意的是,半导体元件200可进行其他工艺,用以形成各种特征,例如接触插塞/介层插塞(contacts/vias),内连线金属层(interconnect metal layer)、层间或金属介电层(interlayer或metal dielectric)、保护层(passivation)、接合垫(bonding pad)、封装结构(packaging)等等。
应能理解的是,此处所公开的不同实施例提供不同的优点,且对于所有实施例不需要特定的优点。例如,本发明所公开的方法提供一种CMOS制作流程中简单且有效方法,用以调整NMOS元件和PMOS元件的金属栅极的功函数。此处所公开的方法与元件不需要用盖层作为调整金属栅极的功函数,因此载子迁移率不会因此受到影响。再者,此处所公开的方法与元件可轻易的整合于目前的CMP工艺流程与半导体配备。例如,此处所公开的注入材料与工艺与CMOS制造流程相容,且不需昂贵的成本。
虽然本发明已以数个较佳实施例公开如上,然而其并非用以限定本发明,任何本领域普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视后附的权利要求所界定的范围为准。例如,为了特定的技术与应用,可调整各种金属层的厚度,用以最佳化NMOS元件和PMOS元件的操作性能。
Claims (15)
1.一种半导体元件的制法,包括以下步骤:
提供一半导体基材;
形成一第一晶体管与一第二晶体管于该半导体基材中,其中该第一晶体管具有一第一虚设栅极的第一栅极结构,该第二晶体管具有一第二虚设栅极的第二栅极结构;
移除该第一虚设栅极与该第二虚设栅极,以分别形成一第一沟槽与一第二沟槽;
形成一第一金属层以部分填充该第一沟槽与该第二沟槽;
移除于该第一沟槽中的第一金属层;
形成一第二金属层,以部分填充该第一沟槽与该第二沟槽;
形成一第三金属层,以部分填充该第一沟槽与该第二沟槽;
实施一热处理工艺,以回焊该第二金属层与该第三金属层;以及
形成一第四金属层,以填充该第一沟槽与该第二沟槽的剩余部分。
2.如权利要求1所述的半导体元件的制法,其中该第二金属层包括钛,该第三金属层包括铝。
3.如权利要求1所述的半导体元件的制法,其中实施该热处理工艺包括于约200℃~500℃的温度下实施该热处理工艺。
4.如权利要求1所述的半导体元件的制法,其中形成第四金属层之后,还包括实施一化学机械研磨工艺,用以研磨该第一栅极与该第二栅极结构。
5.如权利要求4所述的半导体元件的制法,其中形成该第四金属层之前,还包括实施另一化学机械研磨工艺。
6.如权利要求1所述的半导体元件的制法,其中该第四金属层包括铝。
7.如权利要求1所述的半导体元件的制法,其中该第一金属层包括氮化钛与氮化钨所组成的多层金属层。
8.如权利要求1所述的半导体元件的制法,其中该第一晶体管为NMOS元件,且该第二晶体管为PMOS元件。
9.一种半导体元件的制法,包括以下步骤:
提供一半导体基材;
形成一第一晶体管与一第二晶体管于该半导体基材中,其中该第一晶体管具有一第一栅极结构,该第二晶体管具有一第二栅极结构,且该第一栅极结构与该第二栅极结构各自包括一高介电常数层形成于该半导体基材之上,一阻障层形成于该高介电常数层之上,以及一虚设多晶硅层形成于该阻障层之上;
从该第一栅极结构与该第二栅极结构中移除该虚设多晶硅层,以分别形成一第一沟槽与一第二沟槽;
形成一P型功函数金属层以部分填充该第一沟槽与该第二沟槽;
移除于该第一沟槽中的P型功函数金属层;
形成一钛层,以部分填充该第一沟槽与该第二沟槽;
形成一铝层,以部分填充该第一沟槽与该第二沟槽;
回焊该钛层与该铝层,以形成一铝钛层;以及
形成一填充金属层,以填充该第一沟槽与该第二沟槽的剩余部分。
10.如权利要求9所述的半导体元件的制法,其中该钛层由物理气相沉积法制得,该铝层由化学气相沉积法制得。
11.如权利要求9所述的半导体元件的制法,其中该回焊该钛层与铝层包括于约200℃~500℃的温度下实施一热处理工艺。
12.一种半导体元件的制法,包括以下步骤:
提供一半导体基材;
形成一第一晶体管与一第二晶体管于该半导体基材中,其中该第一晶体管具有一第一栅极结构,该第二晶体管具有一第二栅极结构,且该第一栅极结构与该第二栅极结构各自包括一高介电常数层形成于该半导体基材之上,一阻障层形成于该高介电常数层之上,以及一虚设多晶硅层形成于该阻障层之上;
从该第一栅极结构与该第二栅极结构中移除该虚设多晶硅层,以分别形成一第一沟槽与一第二沟槽;
形成一P型功函数金属层以部分填充该第一沟槽与该第二沟槽;
移除于该第一沟槽中的P型功函数金属层;
形成一钛层,以部分填充该第一沟槽与该第二沟槽;
形成一铝层,以部分填充该第一沟槽与该第二沟槽;
回焊该钛层与该铝层,以形成一铝钛层;
实施一化学机械研磨工艺,用以移除位于该第一沟槽与该第二沟槽之外的各金属层;以及
形成一填充金属层,以填充该第一沟槽与该第二沟槽的剩余部分。
13.如权利要求12所述的半导体元件的制法,其中形成该填充金属层之后,还包括实施另一化学机械研磨工艺,用以移除位于该第一沟槽与该第二沟槽外的该填充金属层。
14.如权利要求12所述的半导体元件的制法,其中该填充金属包括铝、钨或铜。
15.如权利要求12所述的半导体元件的制法,其中该钛层由物理气相沉积法制得,且该铝层由化学气相沉积法制得。
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US8105891B2 (en) | 2012-01-31 |
TWI393220B (zh) | 2013-04-11 |
CN101677087B (zh) | 2012-02-01 |
TW201025509A (en) | 2010-07-01 |
US20110059601A1 (en) | 2011-03-10 |
US20100068877A1 (en) | 2010-03-18 |
US7927943B2 (en) | 2011-04-19 |
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