CN101652846B - 可循环热连接 - Google Patents

可循环热连接 Download PDF

Info

Publication number
CN101652846B
CN101652846B CN2008800110042A CN200880011004A CN101652846B CN 101652846 B CN101652846 B CN 101652846B CN 2008800110042 A CN2008800110042 A CN 2008800110042A CN 200880011004 A CN200880011004 A CN 200880011004A CN 101652846 B CN101652846 B CN 101652846B
Authority
CN
China
Prior art keywords
temperature
electric contact
composition
electric
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2008800110042A
Other languages
English (en)
Other versions
CN101652846A (zh
Inventor
约翰·特雷扎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cufer Asset Ltd LLC
Cubic Wafer Inc
Original Assignee
Cubic Wafer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cubic Wafer Inc filed Critical Cubic Wafer Inc
Publication of CN101652846A publication Critical patent/CN101652846A/zh
Application granted granted Critical
Publication of CN101652846B publication Critical patent/CN101652846B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/165—Material
    • H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
    • H01L2224/16507—Material outside the bonding interface, e.g. in the bulk of the bump connector comprising an intermetallic compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H01L2224/81204—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding with a graded temperature profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8181—Soldering or alloying involving forming an intermetallic compound at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/8182—Diffusion bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Contacts (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)

Abstract

一种建立电连接的方法，包括：在两个不同的芯片(802，804)中的每一个上设置触点对(808，810)中的一个触点，所述触点对限定它们之间的体积，所述体积容纳至少两个各自具有熔点的成分，所述成分已被选择使得加热到第一温度将在所述至少两个成分中的至少一个成分中引起改变，所述改变将产生新成分，该新成分具有第二温度的新成分熔点，所述新成分熔点高于所述第一温度和所述至少两个成分中的至少第一个成分的熔点；以及将所述触点对和所述至少两个成分加热到所述第一温度。该方法在芯片堆叠的制造中是很有用的，在堆叠的制造中保持焊料的层次是很重要的，该方法允许用于接合芯片触点的相同的成分被用在每个芯片与芯片的交界面处。

Description

可循环热连接
技术领域
本发明涉及半导体，并且更具体地，涉及用于这样的装置的电连接。
背景技术
当堆叠芯片时，主要有两种方式可以形成芯片与芯片的连接。一种方式是形成全部堆叠，然后同时使整个堆叠都处于诸如加热和冷却的条件下，这些条件促使导电粘合材料建立导电通路。另一种方式是通过连接点的加热和冷却将两个元件顺序连接到一起，然后以同样的方式顺序地附接下一个芯片，依次类推，直到完成堆叠。
第一，“同时”方法存在缺点，因为实际上很难在堆叠元件之间保持对齐。另外，很难保证使所有单独连接中的每一个连接都处于在堆叠的组成元件中形成可靠的互连所必需的合适的条件下。因此，存在由于接近连接的条件不充分或不利地超过所需的条件而不能构成任意特定连接的风险。
第二，“顺序”方法不存在对齐的问题。但是，因为用于在第一个芯片之后接合每个芯片的热量对之前被接合的芯片的连接起不利的作用，所以“顺序”方法仍然存在缺点。
因此，需要一种更好的接合芯片以形成堆叠的方法，这种方法可以减少或消除通过使用传统的同时和顺序接合技术会遇到的问题。
发明内容
我们已经设计出一种允许通过不会遭受上述问题的顺序方法或同时方法来建立芯片的堆叠(在芯片、管芯或晶片基底上)的方法。
一个方面涉及建立电连接的方法。该方法涉及在两个不同的芯片中的每一个上设置触点对中的一个触点，该触点对限定它们之间的体积，该体积容纳至少两个各自具有熔点的成分，该成分已被选择使得加热到第一温度将在该至少两个成分中的至少一个成分中引起改变，这种改变将产生新成分，该新成分具有第二温度的新成分熔点，该新成分熔点高于该第一温度和该至少两个成分的至少第一个成分的熔点，以及将该触点对和该至少两个成分加热到该第一温度。
另一个方面涉及芯片的堆叠。芯片的堆叠具有使用具有第一熔点的第一材料成分将两个芯片电接合到一起的第一组成对的触点，和在该两个芯片的一个芯片上的触点组，在该两个芯片的一个芯片上包括具有低于第一熔点的第二熔点的粘合组成成分，使得当该触点组与第三芯片上相对应的触点组配合并且该触点组和相对应的触点组被加热到与第一和第二熔点相对应的温度之间的温度时，该粘合组成成分将成为第一材料成分。
又一个方面涉及在电触点上执行的方法。该方法涉及将位于连接点的至少两个导电材料加热到第一温度，该第一温度超过引起该至少两个导电材料的第一个导电材料的至少一些变成某一状态所需的温度，该状态具有比该至少两个导电材料中的第一个导电材料的熔点高、但比与该至少两个导电材料中的第一个导电材料在状态图上的液态相对应的液相温度低的较高的熔点，以及使得连接点冷却到低于引起该至少两个导电材料中的第一个导电材料的至少一些改变至具有较高的熔点的状态所需的温度。
本文中说明的优点和特点是可从代表性实施例中获得的许多优点和特点中的一部分，并且是仅为帮助理解本发明而陈述的。应当了解这些优点和特点不被认为是对权利要求所限定的本发明的限制，或者是对权利要求的等同物的限制。例如，这些优点中的一些优点互相矛盾，因为它们不能同时存在于单一实施例中。类似地，一些优点可适用于本发明的一个方面，不适用于其他方面。因此，这些特点和优点的概括在确定等效性时不应当被认为是决定性的。本发明另外的特点和优点在以下说明中从附图和权利要求中变得显而易见。
附图说明
图1是金和锡的二元合金的相图表示；
图2是根据本文所述方法的变形例的触点200的剖面照片；
图3是如图2所示的类似原始成分触点在已经被接合到相配合的触点之后的剖面照片；
图4是触点的剖面照片；
图5是如同图4的触点在已经被接合到另一个触点之后的剖面图；
图6是如同图5的触点在完成高温暴露之后的剖面照片；
图7是铅和锡的二元合金的相图表示；和
图8A至图8H图示使用上述方法的变形例的堆叠建立。
具体实施方式
如所说明的，本文中说明的技术特别适用于建立非常紧凑的芯片的堆叠。而且，这些技术可以涉及提供独立于本文所述的多个技术的其他优点的“定位焊&熔合”处理的使用。
另外，与本文同时提交并通过引用结合在本文中的名称为“电连接中的移动粘合”的美国专利申请描述了减少或消除在连接中的相间隔离的问题。将显而易见的是，该方法与本文中所述的技术完全兼容，可以实现其他的优点，而这些优点无法靠它们中的任意一个而获得。
具体地，我们已经设计出对这些技术的进一步改进，该改进允许通过不会遭受上述问题的顺序方法或同时方法来建立芯片的堆叠(在芯片、管芯或晶片基底上)。另外，在某些实现中，我们利用特定阻隔与特定粘合材料的使用来防止移动原子产生相间间隔或空隙。这是基于粘合材料流动所处的温度，通过特定地选择所使用的粘合材料而实现的，以允许多个高温处理步骤发生而不会对任意之前形成的连接产生不利影响。
这可以通过不同的方式实现。但是，一般该方法涉及选择将作为电连接形成的一部分的特定材料(不管特定材料是否是纯金属、基本纯金属或是合金)使得导电连接的初始形成发生在特定温度“T1”。但是，这种形成的结果是形成导电连接的材料将会变成具有比原始材料熔点高的熔点的成分。结果，使用相同材料建立的随后的连接不会引起原始连接开始液化(或如果新熔点高于T1，但非常接近T1，使得没有最低限度地存在的原始材料明显液化)。
任意地，材料可以被选择为随后提高到较高的温度“T2”会引起其进一步变成仍然具有较高熔点的成分。在这种方式中，随后温度提高到T1将根本不会有影响。
有利地是，与定位焊&熔合连接处理在一起该方法尤其有用，因为该方法已经涉及较低温度“定位焊”阶段和随后较高温度“熔合”阶段。
该方法的一个实例相关于图1至图3而图示。
在本实例中，合金沉积在触点上。在本实例中，沉积的合金是金和锡的合金，具体地，是80％金和20％锡。图1是金和锡的二元合金的相图100的表示(虽然未精确地按比例显示)。可以看出，这种80/20金锡合金位于相图100中的共熔点102。这个共熔点102代表这种合成合金的最低熔点。但是，当合金被加热到较高温度时，合金与存在的一些其他材料，例如触点材料或优选地，沉积在i)触点和合金之间或ii)合金上方的材料互相作用，引起合金的成分改变。取决于互相作用和材料，该成分改变根据重量百分比成分浓度减少或增加而引起在相图上向右或左移动。只要成分不引起在相图上向较低熔点的成分移动，结果就是产生具有比初始成分熔点高的成分。
取决于特定执行方式，在相图上的左移或右移可以是组成成分之一增加、组成成分之一减少或一个或更多个成分增加的结果。
通过一个实例，纯锡或高锡浓度的金-锡层可以被沉积在合金顶部。因此，当达到主金-锡合金的熔化温度时，增加的锡或金-锡合金也已熔化并且与80/20的合金结合以形成锡更高的新浓度，例如70/30的金-锡合金。该浓度在原始成分的右边，并且因此具有比80/20的合金高的熔点。
或者，可以使用将锡从金-锡合金和它本身的合金中抽取出来以剩下较高浓度的金的材料。这将导致由于金的较高浓度，从而因此作为结果的较高的合金熔点而在相图上向左移动。
在80/20金-锡合金的情况下，观察相图，为实现期望的结果，成分的改变可以是增加的锡或被移除的金而引起的在相图上向右的成分移动，或者是被移除的锡或增加的金而引起的在相图上向左的成分移动。
在另一个相似的可选方案中，可以使用将金和锡两者与其自身熔合产生少量三元合金的材料，并且只要主合金的成分改变使得其具有较高熔点，就能达到同样的效果。
参考图2和图3，通过类似实例的方式，假设使用与上述相同的方法和材料(即80/20金-锡)，但例如在合金下方沉积足量的镍作为合金和触点之间的阻隔，或者在合金的顶部沉积足量的镍作为盖。图2是根据本文中所述方法的变形例、具有沉积在阻隔材料204(镍阻隔)的顶部的连接材料202(80/20金-锡合金)的触点200的横截面的照片。在这种情况下，在大约300℃或高于300℃的提升的温度处，材料将扩散到一定范围。结果是，在镍已捕获一些较高迁移率的锡并且吸收其剩余部分的同时，锡原子将被镍层吸收或与镍层形成合金，留下高浓度的较低迁移率种类的金属(在本情况下是金)的金-锡合金成分。
图3是诸如图2所示的类似原始成分触点302在如上所讨论的提高的温度下在其已被连结到相配合的触点304以在两个触点302、304之间形成导电连结之后的横截面照片。在图3中，作为上述方法所得到的结果，在触点对302、304之间的体积中的新的成分远不是原始的80/20的百分比。一些区域306具有97％的金，而一些区域308具有25％的锡。结果，根据图1的相图100，应当很明显地可以看出各种作为结果的材料的熔点已被显著地改变。而且，由于触点的实质部分现在多于95％的金的事实，触点的大多数将具有高于300℃、接近1000℃的熔点。即使那些具有较高锡浓度的区域也具有高于300℃、接近400℃的熔点。
此外，有利地，在成分混合物中增加的镍使锡更少可能被移动。这意味着减少了相间隔离问题的可能性。
另外，有利地，锡的吸收或加入合金成分防止整个混合物变得以自我为中心(self-centering)，我们和上述结合的申请中称其为“液化(liquidous)”或“液相”状态，该状态不同于在相中提及的液相状态。
但是注意，对于某些执行方式的连接被软化为对于材料或其某些成分在相图上不及液相状态的某些状态，例如，使用柱和穿透连接方法，“可锻”材料需要在高温下以允许材料充分软化，从而允许柱穿透但不被软化成我们已经定义的“液相”状态，更不用说熔化状态。
结果，触点可以被反复提高到原始熔点而不影响该连接。因此，应当认识到该方法可以被反复使用以将芯片加到堆上而不用考虑新连接的形成会毁坏先前的连接。
当然，现在应认识到，只要成分的改变导致熔点向上移动，初始成分就无需处于最低熔点。这可以从以下实例中得出，在该实例中材料开始隔离然后结合成最终状态。
图4是根据阻隔402，在本情况下是镍，构成的一个变形例的触点400的横截面的照片，该阻隔离402在被100％金的层406覆盖的器件衬垫404的顶部，该层406被100％锡的层408覆盖。
如同图4的触点将被连结到另一个触点(未显示在图4中)以形成电连接。在本实例中，另一个触点是被镍层覆盖的柱。
图5是类似图4的触点400在其已被连结到处于定位焊&熔合处理的定位焊阶段的另一个触点500之后的横截面照片。
对触点加热已引起具有较低熔点的锡层408扩散到金层406中，并且穿过镍的阻隔402。这将成分改变使得仍然存在具有大量的约100％金的层406，但同时也存在约80％金和20％锡的合金层502而不是原始的100％锡层。因此，虽然原始成分在图1的相图上位于点“C0”和“C1”，金层仍然大约处于点“C0”，但是新成分现在在图1的相图上位于点“C2”，使得在锡变化为锡合金的情况下，熔点已从232℃左右上升到282℃左右，并且金的熔点基本上未改变。(当然实际上，金的成分目前也许稍微小于100％，从而稍微降低熔点，但是因为有意义的温度在232℃左右和282℃左右之间，所以这是非实质的改变)。重新参考图5，如果对触点对400、500被施加合适的较高温度，例如通过使用定位焊&熔合处理的熔合阶段，会发生进一步的成分改变。
图6是如同图5的触点在完成高温暴露处理例如经过熔合处理之后的剖面照片。如图6可见，连接的最终成分目前主要是与金、锡和镍的三元合金604侧面相接的金(大约98％)中心区602，在本实例中，三元合金604是大约45％Au、35％Sn和20％Ni。由于该合金604具有比80％/20％金-锡合金高的熔点，所以已经获得与上述相同的效果。因此，可以对该触点实行热循环直到引起三元合金604形成的温度，而不存在因为成分熔点全部高于该温度而破坏连接的风险。
此处应注意上述方法不局限于使用纯金属或合金。可以对焊料(无论他们是否含铅或无铅)使用相同的方法。
图7是用于铅和锡(虽然刻度上未精确显示)的二元合金的相图700的表示。记住以上说明和实例，现在可知如果使用与共晶点702一致的初始成分并且使用附加成分来增加铅或去除锡，则随着成分向相图的左侧移动，熔点将上升。换句话说，对于相同的起点702，如果使用附加成分来去除铅或增加锡，则熔点将由于成分移动到相图700的右侧而上升。
现在应认识到同样的方法也可以有利地与传统的C4焊料一起使用，如在相图上所示的，传统的C4焊料含有大约60％铅/40％锡的成分。为达到该目的，显而易见地，在加热时使用附加成分将从C4焊料中去除锡或在C4焊料中增加铅。在这种方式中，成分的改变将在C4焊料的成分的左侧的点产生，并且因此导致较高熔点。如果假设对连接实施上述处理并且作为结果的成分是25％锡和75％铅，则熔点将从温度TC4上升到与在相图上标记“TN”的点相对应的温度。此后，连接的温度可以上升到且超过C4熔点，并且，只要不超过TN点温度，连接就不会被破坏。
现在，可以了解，通过使用该方法的变形例，可以很容易地以顺序的方式如下来建立芯片的堆叠800。该处理以极其简化的形式在图8A至图8H中图示，图8A至图8H中图示了使用上述方法的变形例的堆叠建立。
使用上述的连接，将用于堆叠的两个芯片802、804(不管仍然是晶片的部分或是分离后)(图8A)放在一起(图8B)，连接点806处的温度被升高到高于连接的两个元件808、810中的一个的熔点，该连接包含一个适合本文描述的方法的材料的变形。这将会使电连接在每个连接点806处形成，并且还会将导电粘合材料的成分变成新成分812，新成分812将具有比用于形成该成分的温度更高的熔点。然后，被接合的芯片802，804可以被冷却到低于连接形成温度的温度以使连接形成“组”。之后，可以将另一个芯片814放到现在形成的堆叠中(图8C)，该芯片的触点(该触点也可以用于这里所描述的变形例，并且理想地，用同样的变形例接合最先的两个芯片)能够与堆叠上相配合的触点在它们各自的连接点处接触。随后在这些连接点处将温度升高到连接形成温度将使第三芯片连接到堆叠上(图8D)，但是，由于接合处理产生的成分具有较高的熔点，最先的两个芯片之间的连接将不会受到影响。反复进行该处理(图8E，图8F)(图8G，图8H)，重复建立堆叠所需的次数。
因此应当理解本说明书(包括附图)只是某些示例性的实施例的代表。为了方便读者，上述描述已经集中在所有可能的实施例的代表性实例上，教导本发明的原理的实例上。本说明书并没有试图穷举所有可能的变形例。可替代的实施例可能没有作为本发明的具体部分呈现，或者此外未描述的可替代的实施例可能是可作为一部分得到的，但是这并不被认为是对那些可替代的实施例的放弃。一个普通的技术人员应了解许多那些未描述的实施例结合了本发明的相同原理，并且其他的也是等同的。

Claims (13)

1.一种在第一芯片上的第一电触点和第二芯片上的第二电触点之间形成电连接的方法，其特征在于，该方法包括：
使所述第一和第二电触点彼此紧接，其中所述第一电触点包含具有第一熔点的第一成分，以及其中所述第二电触点包含具有第二熔点的第二成分；
在低于所述第一和第二熔点的温度将所述第一或第二电触点中的一个插入所述第一或第二电触点中的另一个；以及
将所述第一和第二电触点加热到第一温度以在它们之间形成具有第三成分的电连接，其中所述第三成分具有高于所述第一和第二熔点的第三熔点；其中将所述第一和第二电触点加热到第一温度的步骤是在所述将所述第一或第二电触点中的一个插入所述第一或第二电触点中的另一个的步骤之后进行的；
该方法进一步包括将所述第一或第二电触点中的一个加热到低于所述第一和第二熔点的温度，并且
所述第一和第二电触点共同包含柱和可锻材料，并且其中插入包括使所述柱穿透所述可锻材料。
2.如权利要求1所述的方法，其特征在于，将所述第一或第二电触点中的一个加热包括加热所述可锻材料以使所述可锻材料软化，使得所述柱可以使所述可锻材料在压力下变形，从而穿透进入所述可锻材料。
3.如权利要求1所述的方法，其特征在于，进一步包括，在将所述第一和第二电触点加热到第一温度以在它们之间形成具有第三成分的电连接后，将所述第一和第二电触点冷却到低于所述第一温度的温度。
4.如权利要求3所述的方法，其特征在于，进一步包括，在冷却之后：
使第三芯片上的第三电触点紧接所述第一或第二芯片中的一个芯片上的配合的电触点；
将所述第三电触点和所述配合的电触点加热到至少是所述第一温度但是低于所述第三熔点的温度；以及
在加热所述第三电触点和所述配合的电触点之后，将所述第三电触点和所述配合的电触点冷却到低于所述第一温度的温度。
5.如权利要求1所述的方法，其特征在于，在所述第一和第二电触点之间设置阻隔材料。
6.如权利要求1所述的方法，其特征在于，在所述第一和第二电触点之间设置材料，其中该材料在被加热到高于所述第一温度时将与所述第一或第二成分中的一个成分形成合金。
7.如权利要求1所述的方法，其特征在于，所述第一和第二成分被排列成层叠构造，以及其中所述第三熔点大于所述第一温度。
8.如权利要求1所述的方法，其特征在于，所述在低于所述第一和第二熔点的温度将所述第一或第二电触点中的一个插入所述第一或第二电触点中的另一个包括对所述第一或第二芯片中的一个施加压力。
9.如权利要求1所述的方法，其特征在于，进一步包括在插入之前，在所述第一或第二电触点中的至少一个上沉积合金。
10.如权利要求9所述的方法，其特征在于，在所述第一和第二电触点之间设置阻隔材料，其中所述阻隔材料被构造成束缚能移动的成分，所述能移动的成分包含在所述合金、所述第一电触点或所述第二电触点中的一个之中。
11.如权利要求10所述的方法，其特征在于，所述阻隔材料包括镍，以及其中所述能移动的成分包括锡。
12.如权利要求1所述的方法，其特征在于，所述第三成分包括大约70％的金和30％的锡。
13.如权利要求1所述的方法，其特征在于，进一步包括：
允许所述电连接冷却到低于所述第一温度；以及
在所述允许所述电连接冷却之后，将所述电连接加热到高于所述第一温度但低于所述第三熔点的再加热温度。
CN2008800110042A 2007-04-05 2008-06-05 可循环热连接 Active CN101652846B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/696,774 2007-04-05
US11/696,774 US7850060B2 (en) 2007-04-05 2007-04-05 Heat cycle-able connection
PCT/IB2008/001436 WO2008122890A2 (en) 2007-04-05 2008-06-05 Heat cycle-able connection

Publications (2)

Publication Number Publication Date
CN101652846A CN101652846A (zh) 2010-02-17
CN101652846B true CN101652846B (zh) 2013-04-24

Family

ID=39826084

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008800110042A Active CN101652846B (zh) 2007-04-05 2008-06-05 可循环热连接

Country Status (6)

Country Link
US (1) US7850060B2 (zh)
EP (1) EP2313916A2 (zh)
JP (1) JP5702136B2 (zh)
KR (1) KR20100012865A (zh)
CN (1) CN101652846B (zh)
WO (1) WO2008122890A2 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090008430A1 (en) * 2007-07-06 2009-01-08 Lucent Technologies Inc. Solder-bonding process
BRPI0914522B1 (pt) 2008-10-30 2019-04-02 Evogene Ltd Método para aumentar o rendimento, a biomassa, a taxa de crescimento, o vigor, oteor de óleo, e/ou a eficiência da utilização do nitrogênio de uma planta
JP6043058B2 (ja) 2011-11-07 2016-12-14 デクセリアルズ株式会社 接続装置、接続構造体の製造方法、チップスタック部品の製造方法及び電子部品の実装方法
JP6206159B2 (ja) * 2013-12-17 2017-10-04 三菱電機株式会社 半導体装置の製造方法

Family Cites Families (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312878A (en) 1965-06-01 1967-04-04 Ibm High speed packaging of miniaturized circuit modules
US4465223A (en) * 1980-12-31 1984-08-14 International Business Machines Corporation Process for brazing
US4418857A (en) * 1980-12-31 1983-12-06 International Business Machines Corp. High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
US4967950A (en) * 1989-10-31 1990-11-06 International Business Machines Corporation Soldering method
JPH0831617B2 (ja) 1990-04-18 1996-03-27 三菱電機株式会社 太陽電池及びその製造方法
JP2918307B2 (ja) 1990-08-07 1999-07-12 沖電気工業株式会社 半導体記憶素子
KR940006696B1 (ko) 1991-01-16 1994-07-25 금성일렉트론 주식회사 반도체 소자의 격리막 형성방법
EP0516866A1 (en) 1991-05-03 1992-12-09 International Business Machines Corporation Modular multilayer interwiring structure
JP2608513B2 (ja) 1991-10-02 1997-05-07 三星電子株式会社 半導体装置の製造方法
US5261593A (en) * 1992-08-19 1993-11-16 Sheldahl, Inc. Direct application of unpackaged integrated circuit to flexible printed circuit
US5603847A (en) 1993-04-07 1997-02-18 Zycon Corporation Annular circuit components coupled with printed circuit board through-hole
US5587119A (en) 1994-09-14 1996-12-24 E-Systems, Inc. Method for manufacturing a coaxial interconnect
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
US5608264A (en) 1995-06-05 1997-03-04 Harris Corporation Surface mountable integrated circuit with conductive vias
US5814889A (en) 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5872051A (en) 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
JP2739855B2 (ja) 1995-12-14 1998-04-15 日本電気株式会社 半導体装置およびその製造方法
US5973396A (en) 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
US6310484B1 (en) 1996-04-01 2001-10-30 Micron Technology, Inc. Semiconductor test interconnect with variable flexure contacts
US5872338A (en) 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
JP2790122B2 (ja) 1996-05-31 1998-08-27 日本電気株式会社 積層回路基板
US7052941B2 (en) 2003-06-24 2006-05-30 Sang-Yun Lee Method for making a three-dimensional integrated circuit structure
JP3176307B2 (ja) 1997-03-03 2001-06-18 日本電気株式会社 集積回路装置の実装構造およびその製造方法
JPH10335383A (ja) 1997-05-28 1998-12-18 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH11166935A (ja) 1997-09-25 1999-06-22 Canon Inc 光検出または照射用の光プローブと該プローブを備えた近視野光学顕微鏡、及該光プローブの製造方法とその製造に用いる基板
US6620731B1 (en) 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6075710A (en) 1998-02-11 2000-06-13 Express Packaging Systems, Inc. Low-cost surface-mount compatible land-grid array (LGA) chip scale package (CSP) for packaging solder-bumped flip chips
US5962922A (en) 1998-03-18 1999-10-05 Wang; Bily Cavity grid array integrated circuit package
US6222276B1 (en) 1998-04-07 2001-04-24 International Business Machines Corporation Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
US6380023B2 (en) 1998-09-02 2002-04-30 Micron Technology, Inc. Methods of forming contacts, methods of contacting lines, methods of operating integrated circuitry, and integrated circuits
US6122187A (en) 1998-11-23 2000-09-19 Micron Technology, Inc. Stacked integrated circuits
US6316737B1 (en) 1999-09-09 2001-11-13 Vlt Corporation Making a connection between a component and a circuit board
JP3386029B2 (ja) 2000-02-09 2003-03-10 日本電気株式会社 フリップチップ型半導体装置及びその製造方法
US6446317B1 (en) 2000-03-31 2002-09-10 Intel Corporation Hybrid capacitor and method of fabrication therefor
JP2001338947A (ja) 2000-05-26 2001-12-07 Nec Corp フリップチップ型半導体装置及びその製造方法
TW525417B (en) 2000-08-11 2003-03-21 Ind Tech Res Inst Composite through hole structure
US6577013B1 (en) 2000-09-05 2003-06-10 Amkor Technology, Inc. Chip size semiconductor packages with stacked dies
US6720245B2 (en) 2000-09-07 2004-04-13 Interuniversitair Microelektronica Centrum (Imec) Method of fabrication and device for electromagnetic-shielding structures in a damascene-based interconnect scheme
US6740576B1 (en) 2000-10-13 2004-05-25 Bridge Semiconductor Corporation Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly
JP2002134545A (ja) 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd 半導体集積回路チップ及び基板、並びにその製造方法
JP4608763B2 (ja) 2000-11-09 2011-01-12 日本電気株式会社 半導体装置
EP1217656A1 (en) 2000-12-20 2002-06-26 STMicroelectronics S.r.l. Process for manufacturing components in a semiconductor material with reduction in the starting wafer thickness
US6512300B2 (en) 2001-01-10 2003-01-28 Raytheon Company Water level interconnection
JP4118029B2 (ja) 2001-03-09 2008-07-16 富士通株式会社 半導体集積回路装置とその製造方法
US7218349B2 (en) 2001-08-09 2007-05-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US6747347B2 (en) 2001-08-30 2004-06-08 Micron Technology, Inc. Multi-chip electronic package and cooling system
JP3495727B2 (ja) 2001-11-07 2004-02-09 新光電気工業株式会社 半導体パッケージおよびその製造方法
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
US6590278B1 (en) 2002-01-08 2003-07-08 International Business Machines Corporation Electronic package
US6770822B2 (en) 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
US7135777B2 (en) 2002-05-03 2006-11-14 Georgia Tech Research Corporation Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof
US6939789B2 (en) 2002-05-13 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of wafer level chip scale packaging
SG111069A1 (en) 2002-06-18 2005-05-30 Micron Technology Inc Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
JP3679786B2 (ja) 2002-06-25 2005-08-03 松下電器産業株式会社 半導体装置の製造方法
SG111972A1 (en) 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
ITTO20030269A1 (it) 2003-04-08 2004-10-09 St Microelectronics Srl Procedimento per la fabbricazione di un dispositivo
JP2005011838A (ja) 2003-06-16 2005-01-13 Toshiba Corp 半導体装置及びその組立方法
US20050046034A1 (en) 2003-09-03 2005-03-03 Micron Technology, Inc. Apparatus and method for high density multi-chip structures
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US20050104027A1 (en) 2003-10-17 2005-05-19 Lazarev Pavel I. Three-dimensional integrated circuit with integrated heat sinks
US7276787B2 (en) 2003-12-05 2007-10-02 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7230318B2 (en) 2003-12-24 2007-06-12 Agency For Science, Technology And Research RF and MMIC stackable micro-modules
US7157310B2 (en) 2004-09-01 2007-01-02 Micron Technology, Inc. Methods for packaging microfeature devices and microfeature devices formed by such methods
JP2006179570A (ja) 2004-12-21 2006-07-06 Renesas Technology Corp 半導体装置の製造方法
US7390735B2 (en) 2005-01-07 2008-06-24 Teledyne Licensing, Llc High temperature, stable SiC device interconnects and packages having low thermal resistance
US7400042B2 (en) 2005-05-03 2008-07-15 Rosemount Aerospace Inc. Substrate with adhesive bonding metallization with diffusion barrier
WO2006138492A2 (en) 2005-06-14 2006-12-28 Cubic Wafer, Inc. Post & penetration interconnection
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection

Also Published As

Publication number Publication date
US20080245846A1 (en) 2008-10-09
US7850060B2 (en) 2010-12-14
KR20100012865A (ko) 2010-02-08
CN101652846A (zh) 2010-02-17
JP5702136B2 (ja) 2015-04-15
WO2008122890A2 (en) 2008-10-16
EP2313916A2 (en) 2011-04-27
WO2008122890A3 (en) 2009-02-12
JP2011501394A (ja) 2011-01-06

Similar Documents

Publication Publication Date Title
CN101652846B (zh) 可循环热连接
US10068864B2 (en) Nanowires for pillar interconnects
CN101258593B (zh) 隔离的芯片至芯片的接触点
JP2000210767A (ja) ２つの部品の接合方法
KR950030285A (ko) 칩 캐리어에 집적 회로 칩을 플립 칩 본딩하는 방법
JP2006190850A (ja) 半導体装置およびその製造方法
CN104704620A (zh) 用于流控自组装的双焊料层、电组件衬底以及采用该流控自组装的方法
CN106133895A (zh) 使用罩盖装配电气构件的方法和适合在该方法中使用的罩盖
CN105027307B (zh) 热电变换装置以及其制造方法
CN102569251A (zh) 三维封装用金属间化合物填充的垂直通孔互连结构及制备方法
KR20150135419A (ko) In-bi-ag 연결 층을 형성하기 위해 등온 응고 반응을 이용한 접합부들의 연결 방법, 및 접합부들의 상응하는 배열체
US20140008801A1 (en) Submicron connection layer and method for using the same to connect wafers
CN102457016A (zh) 半导体激光装置的制造方法、半导体激光装置及光装置
DE102012110542A1 (de) Selbstaktivierender Dünnschichtgetter in reaktiven Mehrschichtsystemen
KR970701428A (ko) 3차원 회로 장치의 제조 방법(process for producing a three-dimensional circuit)
US4465223A (en) Process for brazing
CN112136210A (zh) 由三个堆叠的接合副构成的复合组件
JPH07506773A (ja) 中間温度拡散接合
CN101373802B (zh) 红外焦平面探测器互连铟柱感应回熔技术
US6609651B1 (en) Method of soldering a leaded circuit component
JP2670098B2 (ja) ろう付きリードフレーム
Golim et al. Low-temperature Metal Bonding for Optical Device Packaging
US3735479A (en) Method of fusion-bonding parts by partial liquid phase formation
JPH11121813A (ja) 熱電素子及びその製造方法
JP5722915B2 (ja) 電気接点材料およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant