CN101627468A - 半导体材料内的沟槽形成 - Google Patents

半导体材料内的沟槽形成 Download PDF

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Publication number
CN101627468A
CN101627468A CN200880007500A CN200880007500A CN101627468A CN 101627468 A CN101627468 A CN 101627468A CN 200880007500 A CN200880007500 A CN 200880007500A CN 200880007500 A CN200880007500 A CN 200880007500A CN 101627468 A CN101627468 A CN 101627468A
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CN
China
Prior art keywords
gate electrode
semiconductor layer
patterned gate
layer
electrode structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200880007500A
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English (en)
Chinese (zh)
Inventor
马克·D·霍尔
格伦·C·阿别利
约翰·M·格兰特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101627468A publication Critical patent/CN101627468A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0293—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using formation of insulating sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
CN200880007500A 2007-03-08 2008-02-06 半导体材料内的沟槽形成 Pending CN101627468A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/683,846 2007-03-08
US11/683,846 US7879663B2 (en) 2007-03-08 2007-03-08 Trench formation in a semiconductor material

Publications (1)

Publication Number Publication Date
CN101627468A true CN101627468A (zh) 2010-01-13

Family

ID=39738663

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880007500A Pending CN101627468A (zh) 2007-03-08 2008-02-06 半导体材料内的沟槽形成

Country Status (7)

Country Link
US (1) US7879663B2 (enExample)
EP (1) EP2122677A4 (enExample)
JP (1) JP5370161B2 (enExample)
KR (1) KR101530099B1 (enExample)
CN (1) CN101627468A (enExample)
TW (1) TWI414039B (enExample)
WO (1) WO2008109221A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950251A (zh) * 2017-12-12 2019-06-28 瑞萨电子株式会社 半导体器件及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009130167A (ja) * 2007-11-26 2009-06-11 Renesas Technology Corp 半導体装置およびその製造方法
US10573751B2 (en) * 2012-01-23 2020-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for providing line end extensions for fin-type active regions
US10707352B2 (en) * 2018-10-02 2020-07-07 Qualcomm Incorporated Transistor with lightly doped drain (LDD) compensation implant

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4789648A (en) 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4988643A (en) 1989-10-10 1991-01-29 Vlsi Technology, Inc. Self-aligning metal interconnect fabrication
US5021848A (en) 1990-03-13 1991-06-04 Chiu Te Long Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof
US5019879A (en) 1990-03-15 1991-05-28 Chiu Te Long Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
JPH04206775A (ja) * 1990-11-30 1992-07-28 Casio Comput Co Ltd 薄膜トランジスタ
JPH0521465A (ja) * 1991-07-10 1993-01-29 Fujitsu Ltd 半導体装置及びその製造方法
JPH0613615A (ja) * 1992-04-10 1994-01-21 Fujitsu Ltd 半導体装置の製造方法
US5523258A (en) 1994-04-29 1996-06-04 Cypress Semiconductor Corp. Method for avoiding lithographic rounding effects for semiconductor fabrication
US5496771A (en) 1994-05-19 1996-03-05 International Business Machines Corporation Method of making overpass mask/insulator for local interconnects
US5545581A (en) 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
US5920108A (en) * 1995-06-05 1999-07-06 Harris Corporation Late process method and apparatus for trench isolation
JPH113999A (ja) * 1997-06-13 1999-01-06 Sony Corp 半導体装置の製造方法
TW351849B (en) 1997-09-11 1999-02-01 United Microelectronics Corp Method for fabricating shadow trench insulation structure
US5998835A (en) * 1998-02-17 1999-12-07 International Business Machines Corporation High performance MOSFET device with raised source and drain
JPH11274508A (ja) * 1998-03-25 1999-10-08 Toshiba Corp 薄膜トランジスタの製造方法
KR20000074841A (ko) 1999-05-26 2000-12-15 윤종용 트렌치 격리 형성 방법
JP2001144170A (ja) * 1999-11-11 2001-05-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6359305B1 (en) 1999-12-22 2002-03-19 Turbo Ic, Inc. Trench-isolated EEPROM flash in segmented bit line page architecture
JP3519662B2 (ja) * 2000-03-14 2004-04-19 松下電器産業株式会社 半導体装置及びその製造方法
JP3647384B2 (ja) * 2000-04-04 2005-05-11 松下電器産業株式会社 薄膜半導体素子およびその製造方法並びに表示パネル
JP2002033483A (ja) * 2000-07-17 2002-01-31 Sony Corp 薄膜半導体装置の製造方法
KR20020042312A (ko) 2000-11-30 2002-06-05 윤종용 반도체 디바이스 및 그 제조방법
US6624043B2 (en) * 2001-09-24 2003-09-23 Sharp Laboratories Of America, Inc. Metal gate CMOS and method of manufacturing the same
KR20030055997A (ko) 2001-12-27 2003-07-04 삼성전자주식회사 얕은 트렌치 아이솔레이션 구조를 갖는 반도체 장치 및 그형성방법
US6858514B2 (en) 2002-03-29 2005-02-22 Sharp Laboratories Of America, Inc. Low power flash memory cell and method
US6867462B2 (en) * 2002-08-09 2005-03-15 Matsushita Electric Industrial Co., Ltd. Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same
GB0229217D0 (en) * 2002-12-14 2003-01-22 Koninkl Philips Electronics Nv Vertical insulated gate transistor and manufacturing method
KR100878498B1 (ko) 2002-12-30 2009-01-15 주식회사 하이닉스반도체 트랜지스터 제조방법
US7018873B2 (en) * 2003-08-13 2006-03-28 International Business Machines Corporation Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate
US6838332B1 (en) * 2003-08-15 2005-01-04 Freescale Semiconductor, Inc. Method for forming a semiconductor device having electrical contact from opposite sides
JP5144001B2 (ja) * 2003-12-30 2013-02-13 三星電子株式会社 多結晶シリコン半導体素子及びその製造方法
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
US7141476B2 (en) * 2004-06-18 2006-11-28 Freescale Semiconductor, Inc. Method of forming a transistor with a bottom gate
KR100617051B1 (ko) * 2004-12-27 2006-08-30 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7470573B2 (en) * 2005-02-18 2008-12-30 Sharp Laboratories Of America, Inc. Method of making CMOS devices on strained silicon on glass
KR100653714B1 (ko) 2005-04-12 2006-12-05 삼성전자주식회사 반도체소자의 제조방법 및 그에 의해 제조된 반도체소자
US7335932B2 (en) * 2005-04-14 2008-02-26 International Business Machines Corporation Planar dual-gate field effect transistors (FETs)
US7192855B2 (en) * 2005-04-15 2007-03-20 Freescale Semiconductor, Inc. PECVD nitride film
US7361534B2 (en) * 2005-05-11 2008-04-22 Advanced Micro Devices, Inc. Method for fabricating SOI device
US7732289B2 (en) * 2005-07-05 2010-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a MOS device with an additional layer
US7326617B2 (en) * 2005-08-23 2008-02-05 United Microelectronics Corp. Method of fabricating a three-dimensional multi-gate device
JP5098261B2 (ja) * 2005-12-09 2012-12-12 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US7635620B2 (en) * 2006-01-10 2009-12-22 International Business Machines Corporation Semiconductor device structure having enhanced performance FET device
US7485508B2 (en) * 2007-01-26 2009-02-03 International Business Machines Corporation Two-sided semiconductor-on-insulator structures and methods of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109950251A (zh) * 2017-12-12 2019-06-28 瑞萨电子株式会社 半导体器件及其制造方法
CN109950251B (zh) * 2017-12-12 2023-10-13 瑞萨电子株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
JP2010520645A (ja) 2010-06-10
EP2122677A1 (en) 2009-11-25
EP2122677A4 (en) 2011-11-23
KR20090125247A (ko) 2009-12-04
US7879663B2 (en) 2011-02-01
WO2008109221A1 (en) 2008-09-12
US20080217705A1 (en) 2008-09-11
TWI414039B (zh) 2013-11-01
TW200903711A (en) 2009-01-16
JP5370161B2 (ja) 2013-12-18
KR101530099B1 (ko) 2015-06-18

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Application publication date: 20100113