CN101542697A - High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same - Google Patents
High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same Download PDFInfo
- Publication number
- CN101542697A CN101542697A CNA2007800279592A CN200780027959A CN101542697A CN 101542697 A CN101542697 A CN 101542697A CN A2007800279592 A CNA2007800279592 A CN A2007800279592A CN 200780027959 A CN200780027959 A CN 200780027959A CN 101542697 A CN101542697 A CN 101542697A
- Authority
- CN
- China
- Prior art keywords
- substrate
- region
- trap
- field oxide
- conduction type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 300
- 239000002019 doping agent Substances 0.000 claims abstract description 47
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 239000010410 layer Substances 0.000 claims description 251
- 238000002955 isolation Methods 0.000 claims description 114
- 229910052751 metal Inorganic materials 0.000 claims description 91
- 239000002184 metal Substances 0.000 claims description 91
- 238000002347 injection Methods 0.000 claims description 87
- 239000007924 injection Substances 0.000 claims description 87
- 238000005516 engineering process Methods 0.000 claims description 62
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 42
- 229920005591 polysilicon Polymers 0.000 claims description 38
- 230000015572 biosynthetic process Effects 0.000 claims description 35
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 230000008569 process Effects 0.000 abstract description 26
- 238000012545 processing Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 description 51
- 238000009792 diffusion process Methods 0.000 description 43
- 230000004888 barrier function Effects 0.000 description 32
- 230000000694 effects Effects 0.000 description 27
- 230000005684 electric field Effects 0.000 description 23
- 125000006850 spacer group Chemical group 0.000 description 21
- 238000009826 distribution Methods 0.000 description 20
- 229910021332 silicide Inorganic materials 0.000 description 18
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 229910052796 boron Inorganic materials 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 17
- 230000008859 change Effects 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 16
- 235000012431 wafers Nutrition 0.000 description 16
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 15
- 238000013461 design Methods 0.000 description 15
- 230000001965 increasing effect Effects 0.000 description 13
- 230000008901 benefit Effects 0.000 description 12
- 230000008602 contraction Effects 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000002513 implantation Methods 0.000 description 10
- 230000003071 parasitic effect Effects 0.000 description 10
- 230000002829 reductive effect Effects 0.000 description 8
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 238000007667 floating Methods 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 230000002441 reversible effect Effects 0.000 description 6
- 150000001638 boron Chemical class 0.000 description 5
- 230000006378 damage Effects 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 5
- 239000008186 active pharmaceutical agent Substances 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000000750 progressive effect Effects 0.000 description 3
- 230000007480 spreading Effects 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- OYNAHELWAOEQBG-JACKDLBFSA-N (z)-but-2-enedioic acid;3-(4-chlorophenyl)-n,n-dimethyl-3-pyridin-2-ylpropan-1-amine;3-[(1r)-1-hydroxy-2-(methylamino)ethyl]phenol;hydrochloride Chemical compound Cl.OC(=O)\C=C/C(O)=O.CNC[C@H](O)C1=CC=CC(O)=C1.C=1C=CC=NC=1C(CCN(C)C)C1=CC=C(Cl)C=C1 OYNAHELWAOEQBG-JACKDLBFSA-N 0.000 description 1
- 101100204059 Caenorhabditis elegans trap-2 gene Proteins 0.000 description 1
- 241001289650 Libythea celtis Species 0.000 description 1
- 206010037660 Pyrexia Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000002772 conduction electron Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002500 effect on skin Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000027950 fever generation Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003121 nonmonotonic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 230000004083 survival effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/098—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being PN junction gate field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66098—Breakdown diodes
- H01L29/66106—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
- H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/866—Zener diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
All low-temperature processes are used to fabricate a variety of semiconductor devices in a substrate the does not include an epitaxial layer. The devices include a non-isolated lateral DMOS, a non-isolated extended drain or drifted MOS device, a lateral trench DMOS, an isolated lateral DMOS, JFET and depletion-mode devices, and P-N diode clamps and rectifiers and junction terminations. Since the processes eliminate the need for high temperature processing and employ ''as-implanted'' dopant profiles, they constitute a modular architecture which allows devices to be added or omitted to the IC without the necessity of altering the processes used to produce the remaining devices.
Description
The cross reference of related application
The application is involved in the application No.10/262 that submitted on September 29th, 2002, and 567, now be U.S. Patent No. 6,855,985, it all provides the mode of quoting to introduce therewith.
Technical field
The present invention relates to the semiconductor chip manufacturing, and relate to particularly that monolithic ground is made, the high pressure in the integrated and electric isolation of semiconductor chip and the method for low voltage dipole, CMOS and DMOS transistor and passive component, and need not the high temperature manufacturing technology steps.
Background technology
In the manufacturing of semiconductor integrated circuit (IC) chip, often need electricity to isolate the device that is formed on the chip surface, especially when these devices during at different voltage power supplies.The transistor that electricity is completely like this isolated for integrated some type needs, and comprises bipolar junction transistor and comprises the transistorized various metal-oxide semiconductor (MOS)s of power DMOS (MOS) transistor.Isolating for the current potential that allows the CMOS control circuit to float during operation far above substrate electric potential fully also is needs.
Be isolated in the manufacturing of simulation, power and composite signal integrated circuits particularly important fully.At many circuit with in using, for the identical chip of the device of other isolation on integrated isolation and high tension apparatus non-isolation can be to need or wish; Its warning is the electrical characteristics that the high tension apparatus manufacturing should not reduce isolation, and the manufacturing step of isolating should not change the characteristic of high tension apparatus unfriendly.There is the whole bag of tricks of doing like this.
The traditional CMOS that makes in P type backing material does not promote the isolation fully of its device because each trap that forms the transistorized body of NOMS (back grid) all by short circuit in substrate electric potential, the most negative typically chip power position.Epitaxy junction is isolated or epi-JI employing N type epitaxial loayer, and it is grown on P type silicon substrate top and is separated into the electric barrel district (tub) that isolates-dark P type isolation diffusion by dark P type isolation diffusion needs high-temperature technology enforcement.High-temperature technology causes the distribution again of dopant atom in substrate and the epitaxial loayer, undesirable compromise and harm during the dissimilar device that causes using a common technology to be made is made.In addition, High temperature diffusion that in epi-JI technology, adopts and extension usually with the wafer diameter and with sub-micron CMOS factory in common advanced person's K cryogenic treatment equipment incompatible.
The benefit of source electrode-body short circuit of isolating
In high pressure or power device, the MOS transistor of integrated source electrode-body short circuit exists the different performance of the MOS transistor that surpasses no source electrode-body short circuit and the advantage of durability.Compare with small signal device with traditional logic, have the power of integrated source electrode-body short circuit or high tension apparatus have surpass have separate with physics away from the tangible advantage that contacts with body of source electrode.
Demand for source electrode-body short circuit in many power devices is the result of its application and power current requirements.The mode of the electric demand of power device is to consider that it is for load with for the topological relation of its power supply in the given application of a kind of quick acquisition.We censure this pass at this is " switch-load topology ".
In Figure 1A and 1B, be connected to the power MOSFET of ground or negative potential and be connected to positive potential or power supply V
CCLoad polyphone.Because MOSFET " switch " is connected to ground, is low-side switch or LSS so we censure it at this topologically, both just it was used as current source.In Figure 1A, use conventional non-isolated CMOS technology, circuit 1 comprises load 3, comprises LSS and the current sensing resistor 4 of NMOS 2.In such technology, in substrate, promptly it is grounded the body contact need of MOSFET 2 by short circuit.
Stride across the voltage that detects resistor in order to measure, current detecting requires the source electrode of NMOS 2 should not be shorted to body and substrate, i.e. V
B≠ V
SVoltage difference between source electrode and the body causes many problems.Particularly, any striding across detected the voltage that resistor 4 sets up out and all increased source electrode to bulk potential, and this increases the threshold voltage (owing to being called as the phenomenon of " bulk effect ") of MOSFET again.High threshold increases conducting resistance again and reduces saturation current simultaneously, influences switch performance unfriendly.Another the undesirable effect that disconnects source electrode and body be drain electrode to body diode 5 in any snowslide or displacement current not by detecting resistor and thereby not being detected.At last, do not have the contact of low resistance body, the snapback then can easily occur and puncture.
Use has the LSS device of integrated source electrode-body short circuit, the NMOS 12 in the circuit 10 of Figure 1B for example, drain electrode is to drain electrode and the source terminal (be reverse bias still in parallel) of body diode 15 inverse parallels in MOSFET, make any electric current that flows through load 13 all be detected in detecting resistor 14, no matter whether this electric current flows through the raceway groove of NMOS 12 or flows through back-biased diode 15.Because regardless of source potential, V
SB=0, be significantly so there is not bulk effect, and transistorized conductive characteristic does not significantly change with electric current.
Source electrode-body short circuit has also improved the snowslide durability by the risk (following discussion) that reduces snapback's effect, if especially source electrode-body short circuit can be distributed on broad area device but not in single position by short circuit together equably.The short circuit of source electrode body is integrated among the large tracts of land NMOS, although common in discrete power device, needs the isolation of P type body and P type substrate in integrated form, this is that traditional cmos can not provide.It is complicated for manufacturing that the technology of such isolation is provided, and often requires the high temperature manufacturing step.
In Fig. 1 C and 1D, be connected to positive potential or power supply V
CCPower MOSFET be connected to the ground or the load of negative potential polyphone.Because MOSFET " switch " is connected to positive supply, we censure it as high side switch or HSS at this topologically, and both just it was used as current source.
Use the CMOS technology of conventional non-isolated, the circuit 20 among Fig. 1 C comprises load 23 and comprises the HSS of NMOS 22.In such technology, the body contact need short circuit of MOSFET 22 is in substrate, and promptly it is grounded.As NMOS conducting and V
SIncrease near V
CCCurrent potential the time, big reverse bias current potential-V
SBStriding across diode 25 sets up.The bulk effect of gained causes that the threshold value of NMOS 22 significantly increases, and makes the gate driving be difficult to provide suitable not damage the thin gate oxide of NMOS 22 to realize low on-resistance.
Use has the device of integrated source electrode-body short circuit, the NMOS32 in the circuit 30 of Fig. 1 D for example, and the electric current in the load 33 is Be Controlled easily, need not to offset because the changes of threshold that bulk effect causes.In such topology, drain to drain electrode and the source terminal maintenance inverse parallel (be reverse bias still in parallel) of body diode 35, and under all normal running conditions, all keep reverse bias for MOSFET.Because source potential V how no matter
SB=0, be significant so there is not bulk effect, and transistorized conductive characteristic does not significantly change with electric current.Source electrode-body short circuit also provides the risk (following discussion) that reduces snapback's effect and has improved the snowslide durability, if especially source electrode-body short circuit can be distributed on broad area device but not in single position by short circuit together equably.。The short circuit of source electrode body is integrated among the large tracts of land NMOS, although common in discrete power device, needs the isolation of P type body and P type substrate in integrated form, this is that traditional cmos can not provide.It is complicated for manufacturing that the technology of such isolation is provided, and often requires the high temperature manufacturing step.
In Fig. 1 E, 1F and 1G, power MOSFET is used as bidirectional switch, and forever is not connected to or just or the source electrode or the drain electrode of negative electrical mains.Because MOSFET " switch " is not attached to any power source can be the AC switch so we censure it at this topologically at either direction blocking current or conducting electric current, or " channel transistor " (pass transistor).
The use traditional cmos is made, the channel transistor 40 among Fig. 1 E comprise respectively have NMOS41 that earth electrode connects and back-biased source electrode to body and drain electrode to body diode 42 and 43.Some is any in channel transistor or AC switch application for term " source electrode " and " drain electrode ", because in any given situation, often can not determine with V
SThe biasing or with V
DWhich terminal of biasing will be corrected.Because it is big to stride across the voltage of diode 42 and 43,, make that it is inferior AC switch so bulk effect can cause the remarkable change of threshold value, conducting resistance and the saturation current of NMOS 41.
The replacement scheme of AC switch that implement to require at least two nmos devices with source electrode-body short circuit is shown in the circuit 45 of Fig. 1 F, wherein nmos pass transistor 46 and 47 and public power V
SPolyphone makes drain electrode to body diode 48 and 49 back-to-back connections.In its closed condition, gate terminal is biased to source terminal V
SAvoid channel conduction thus.Conduction by the inverse parallel body diode is also avoided, because one of two diodes keep reverse bias, regardless of striding across the polarity that this series connected switches applies.
In its conducting state, as long as public grid is biased to more than the source terminal, then AC switch 45 can be at the either direction conduction current, because two transistors all are opened.The AC switch of gained can be by two-way obstruction or two-way admittance.Although voltage V
SBe floated on V
D1And V
D2Between the fact, but because V
SB=0, promptly each transistor has integrated source electrode body short circuit, is significant so there is not bulk effect.Such device can easily be integrated into any technology that isolate or can integrated DMOS device that has fully.In the absence of isolating, such device can not be integrated with other device or circuit monolithic ground.Should also be noted that device can be with public drain electrode but not public source be connected, but still need the source electrode body short circuit isolated.
The shortcoming of AC switch 45 is its high conducting resistance rates, promptly big R
DSA is because two polyphone transistors have shown additional resistance.If switch is in parallel in some way, switch then of the same area is with 1/4th resistance of the back-to-back scheme of display switch 45.
Such switch is illustrated in the circuit 50 of Fig. 1 G, and its nmos device 51 and body bias that combines symmetry produces (BBG) circuit 52.The effect of BBG circuit 52 be the body of biasing NMOS 51 to striding across the most negative current potential that device applies, with reverse bias or drain electrode to body diode 55 or source electrode to body diode 56, depend on it is V
SOr V
DThe terminal corrigendum.In this mode, do not have diodes conduct to occur, and if transistorized grid be biased to bulk potential, device is closed and with two-way obstruction.On the contrary, because device is symmetrical, so if grid is biased to " conducting ", then device is with two-way admittance.Notice that term " drain electrode " and " source electrode " is to be used for the identification circuit element arbitrarily and only.
The BBG circuit that illustrates as an example uses cross-linked nmos pass transistor 53 and 54 with the bulk potential V on definite and the biasing NMOS51
B, but in doing like this, they self must comprise the source electrode body short circuit with substrate isolation.Although, still need to isolate being integrated among the IC with other circuit so switch 50 does not use for example DMOS transistor of the preferred enforcement of AC switch 45.
Suppress snapback's punch-through effect
Except the demand of the source electrode body short circuit of integrated nmos device and isolation, another restriction of traditional cmos is that it can not be avoided in undesirable MOSFET work, especially the snapback's punch-through effect in the nmos pass transistor.
Snapback's puncture refers to the phenomenon that causes negative resistance in device, and for the scope of a few thing condition, " decline " of ability is kept in the increase of electric current corresponding to transistorized voltage here.Negative resistance is particularly problematic in power circuit, causes excessive current, vibration and unsteadiness, electrical noise, local pyrexia, thermal runaway and even device failure.
In power electronics, require to avoid at all costs the method for negative resistance, comprise and use the certain device structure that relates to unusual design and processes method, intentionally reduction or restriction are applied to maximum voltage or the electric current on the device, and by other circuit and methods for using them.Unless device is overheated, negative resistance normally or the conductivity modulation that causes of parasitic bipolar conduction, ionization by collision or the result of both some combinations.
For example, in Fig. 2 A, comprise that the lightly doped drain NMOS 60 of P type substrate 61, P+ substrate 62, N+ drain electrode 64, N-drift region 65, MOS insulated gate electrode 69 and N+ source electrode 63 puts on its drain electrode at some positive voltage bias～Vcc of its conducting state sorrow.Schematically being covered on the device, is drain diode 59, its representative or by snowslide, the drain electrode that causes by ionization by collision or by junction leakage to the substrate diode electric current.Main carrier substrate electric current, or show ohmic voltage drop, the resistance substrate R that is schematically contacted respectively in " holes " that P type substrate 61 flows
DBAnd R
SBRepresentative.Because resistance substrate, so be arranged in the voltage V of the gained of the body substrate below the source electrode 63
BTo be increased to than the high voltage of earth terminal that is connected to P+ contact 62.If this voltage is near several 1/10th volts, then N+ district 63 can begin to inject electronics, and promptly minority carrier enters in substrate 61, and electronics by the most positive current potential extremely of the bidimensional electric field attracts in the device, drains 64 at this situation N+ naturally.This electrical conductivity mechanism is comprised parasitic npn bipolar transistor 66 representatives of N+ collector electrode 64, P type substrate-based 61 and N+ emitter 63.Be lower than simple P-N junction diode (because current gain) because the voltage of bipolar transistor is kept ability, thus NPN66 keep voltage be lower than NMOS self and voltage with the snapback to lower value, BV
CER-bipolar collector electrode is described to the voltage of emitter and have the symbol of resistive, non-short circuit, base stage contact.
In another mechanism that causes the snapback shown in the sectional view of Fig. 2 B is ionization by collision in the drain electrode at MOSFET.NMOS is biased to high voltage V in this situation
CCReverse bias comprises that the drain electrode of N+ drain electrode 64 and P type substrate 61 ties substrate thus.Voltage crosses and is in 0V (substrate), V
1, V
2, V
3, V
4And V
5 Equipotential line 71 shown in depletion region descend, each curve press the size increase of voltage potential.The N drift region exhausts under such bias condition, and the permission equipotential line strides across the junction boundary between N drift region and the substrate.
Ideally, these equipotential lines should be opened along the drift region linear interval, the center of the drift region of half voltage that applies between grid 69 and N+ drain electrode 64.But because surface charge and other inevitable skin effect, equipotential line self does not distribute equably, but " bunches up " at gate edge, causes the local higher electric field in the end of drift region.Worse, high electric field physics is positioned at the district near high current density.Have the high drain potential saturation condition of conduction current simultaneously at device,, below grid, flow subsequently along with it leaves from the surface near the edge of the drift region 65 that exhausts by the indicated primary current path of arrow 72.The product of high current density and high electric field causes ionization by collision, and promptly local charge carrier produces, and is produced by the collision of the atomic structure of fast electronics and crystal.Collision is moved atom constraint valence electron together, and is converted into conduction electrons more freely, and this is also quickened by the high electric field in part again.
The ionization by collision of gained is represented the concentric contour of generation rate of increase expressed at this.Because ionization by collision produces electron-hole pair, so cause two undesirable effects.At first electronics is accelerated to the high energy with respect to crystal, promptly becomes on their energy " heat ", and can be swept gate oxide and damage dielectric.Second phenomenon is that the hole stream that produces contributes to and strides across resistance substrate R
SBAdditional voltage drop, worsen NPN snapback effect.
Under higher ionization by collision speed and high electric current, additional phenomenon occurs.In such situation, the charge carrier of generation is by introducing the local conductivity that enough additional charge begin to change the drift region, and promptly it begins to change the local space neutral charge.Superfluous electronics attracts superfluous hole, and this plays the increase that similar drift is mixed.Higher effective is mixed and have been reduced expansion and enter exhausting of N-layer and force equipotential line " to bunch up " more, essence increase the drift region the edge internal field and further increase ionization by collision.The result is another reason of negative resistance, because more ionization by collision causes high internal field and contributes to higher electric current.In addition, two negative resistance effects can occur simultaneously, react to each other in the even not foreseeable mode of complexity.Regardless of mechanism, the result is the drain voltage decline that NMOS can maintain given electric current.
Aspect electric, snapback's phenomenon is drain current I in Fig. 2 C
DTo drain voltage V
DSFigure 75 shown in.By curve 76 shown desirable device breakdown BV
DSSCan be significantly greater than by curve 77 shown snapback's voltage BV
CER, even be 2 times or bigger on voltage.If drain electrode is driven into snowslide with high electric current, keep voltage BV simultaneously
DSS, then it can collapse back suddenly BV
CER, cause that electric current increases and the breaking-up device.If NMOS closes as current source work or from opening to switch to, then snapback's outbreak can be caused that the substrate leakage of increase worsens owing to ionization by collision.Curve 78,79,80 and 81 shows device at BV
CEROn any voltage work in addition all can not use.
A reason of snapback's outbreak is between N+ source electrode 63 and the body contact and following resistance substrate R
SB68 is excessive, if especially substrate is lightly doped.Another effect is that the parasitic NPN gain is excessive, because there are not enough elementary charges in the light dope substrate.A kind of tangible method that reduces the adverse effect of NPN transistor is to increase substrate to mix, but unfortunately does the electric field that has also increased drain electrode like this, causes more ionization by collision and substrate current.
Snapback's effect is schematically expressed by the parasitic bipolar relevant with MOSFET is shown sometimes.For example, the circuit 85 among Fig. 2 D shows NMOS 86 with parasitic NPN 87 and nonlinear emitter to base stage short-circuit resistance device 88.Similarly, PMOS comprises parasitic PNP, but because PNP ratio of gains NPN gain is much lower, and because the impact ionization rate of hot hole induction is more much lower than electron ionization rate, so compared with in NMOS, the snapback is a problem of smaller in PMOS.
Tradition DMOS makes
Not increasing a kind of method that drain electric suppresses the snapback by additional channel doping and lower resistance substrate is by forming the DMOS field-effect transistor.DMOS, a title, wherein letter " D " representative two (being used for double diffusion) originally, be configured, wherein to mix be not uniformly for raceway groove below the grid or body, but concentrated or localization near the source side of grid, to avoid increasing unfriendly near the electric field strength the drain region.In this way, raceway groove concentration can be adjusted and not influence ionization by collision or drain voltage puncture voltage.
The DMOS field-effect transistor can be for isolating or non-isolation type.In conventional art, epitaxial deposition is used in the requirement of isolation, normally the N type extension of growth on P type substrate top.
As shown in Fig. 3 A, N type epitaxial loayer 92 grows in P type substrate 91 top and goes up the DMOS device 90 of isolating to form, and DMOS device 90 also comprises grid polycrystalline silicon 98, gate oxide 99, N+ drain electrode contact 94, N+ source electrode 96, for the contact 97 of P+ body and the P type " body " or the PB district 93 of DMOS transistor uniqueness.N drift region 95 is optionally and can be required, if epi dopant is enough to realize low conducting resistance.Adjoin the drift region part at grid, extra N drift doping can be added to optimize trading off between puncture and the resistance, the restriction of ionisation effect but maintenance is collided.
In the form that substitutes, N type epitaxial loayer can be substituted by P type epitaxial loayer or substrate, but work is enforceable for device in such N drift region.But, do not have N type epitaxial loayer, then DMOS do not isolated and its P type body electrical short in ground, promptly short circuit is in substrate.
Tradition DMOS is manufactured among cross section Figure 100 and 105 of Fig. 3 B and 3C and is illustrated.As shown, thus epitaxial loayer 92 patterned photoresists 101 cover and inject to form shallow-layer 102 by boron in low energy.Be infused in low energy and carry out, typically 50 to 100keV, and near the surface perpendicular to wafer, for example, only 3 degree off-axis have the lateral penetration that is restricted below grid 98.
Inject and at high temperature to be driven into for a long time subsequently, i.e. diffusion with horizontal expansion dopant grid 98 below, ties 93 thereby form, as shown in Fig. 3 C.Diffusion spend any time between 7 to 24 hours, requires above 1050 ℃ and typically 1100 ℃ or higher high temperature, and be a kind of and many modern low temperature manufacturing facilities and the inconsistent technology of wafer diameter.The progress of diffusion is as shown in Fig. 3 C, and by at moment t
1, t
2And t
3Diffusion exemplify, the progress of diffusion is laterally all occurring with vertical, wherein transverse width is about 80% of the vertical junction degree of depth.In the version that illustrates, the body diffusion self alinment is in grid, because it is injected into after grid forms.
If require low temperature process, another autoregistration manufacture method that then forms the DMOS device is shown in Fig. 3 D.In this technology, body is infused in high energy to carry out, typically at the hundreds of thousands electron-volt, but more importantly with precipitous angle, for example with 45 °, with guarantee the body dopant grid 98 below lateral penetration to enough degree, to center on N+ source electrode 96 fully.Laterally injection method is complicated and is undesirable for manufacturing, need carry out 4 times with all 4 gate orientation on the cover wafers because inject.Make that at injection period rotation wafer evenly injection is difficult.
Another DMOS manufacture method is in order to form for example at the non-self aligned DMOS 120 shown in Fig. 3 E to 3G.In Fig. 3 E, shallow boron injection 129 is formed at the epitaxial loayer 122 of 128 masks of patterned photoresist.Inject subsequently as spreading for a long time shown in Fig. 3 F at high temperature.P type island region vertically and laterally spreads for a long time, and is shown as curve 123, and curve 123 has been expressed the moment t that is increasing
1, t
2, t
3And t
4P-N knot.At last in Fig. 3 G, grid 125 and following gate oxide 126 are located in the top at the edge of knot 124, make knot on the surface between gate edge 127A and 127B.Because not autoregistration, so the relative position of grid 125 and knot 124 suffers mask misalignment during manufacture.
In above-mentioned each situation, the dopant-concentration profile that High temperature diffusion technology causes the dullness in DMOS tagma to descend, the highest concentration is in the surface of wafer.Unfortunately such distribution means surface field than the height in the body (bulk) that leaves the surface, is unfavorable for making the durable device of anti-the snowslide.
Conventional junction is isolated manufacturing
It is further complicated that the complete electricity that the high temperature manufacturing that relates in the DMOS system is made makes the employing epitaxy junction isolate the realization circuit is isolated required step.
In the traditional prior art processes as Fig. 4 A to 4I is shown, P type substrate 131 injects by photoresist 132 masks and with arsenic or antimony 133, and then injects by photoresist 134 masks and with boron 135, shown in Fig. 4 C.Inject and under high temperature, spread subsequently, high sometimes to 1200 ℃, and continue to grow to 24 hours, enter substrate and before epitaxial growth, leave the surface to spread the antimony that slowly moves.Between such diffusion period, oxide 138 growth exempts from horizontal doping from the degassing of buried layer to protect the surface.Oxidation also is used to help to define the pattern in the wafer, is used for follow-up mask alignment, because the oxide growth rate of antimony NBL layer 136A top is faster than the growth rate of boron PBL layer 137A top.
After buried layer diffusion, oxide is removed top silicon layer thus as being stripped from and carrying out the HCL acid etching in position when epitaxial growth begins shown in Fig. 4 E, to improve bonding and to reduce crystal defect in the epitaxial loayer.Epitaxially grown result is shown in Fig. 4 F, and wherein epitaxial loayer covers NBL 136B and the PBL 137B that now is expanded, and the both upwards diffuses into epitaxial loayer during its high growth temperature.
Then, as shown in Fig. 4 G and the 4H, high dose phosphorus is injected 140 and is introduced into by mask 141, is following the high dose boron injection 142 of pass through photoresist mask 143.After long-time high temperature isolation diffusion, P type isolated area 145 is connected with part P type buried layer PBL 137C.Similarly, N type heavy district diffusion 144 contacts with buried layer NBL 136C.The thickness that the degree of depth of diffusion and required time are depended on epitaxial loayer 139 in technology and other follow-up High temperature diffusion.Thereby High temperature diffusion also cause buried layer further extending transversely and upwards diffusion form than its processing step formerly promptly bigger 137C and 136C as the size of 137B and 136B.
The clean epitaxial thickness of the diffusion also will the change of any DMOS body all junction depths and buried layer top, all make manufacturing process complexity and specific to concrete epitaxial thickness.Because epitaxial thickness is determined the rated voltage of device, so whole technology and corresponding design criterion all are that voltage is specific.
The manufacturing of low temperature module is applicable to high voltage device
As described earlier, be used to make, isolation and traditional extension of integrated high voltage device and the problem of high-temperature technology and manufacture method be that each high-temperature technology causes that dopant distributes again, influences each high voltage and voltage devices.Use-these manufacturing works that major diameter wafer and modern sub-micron wafer-fabs (fab) have also been got rid of in the high temperature manufacturing have that the high density transistor is integrated, the ability of large chip and high yield and low manufacturing cost.
Needed is the technology in the bag district of floating of a kind of integrated high voltage and DMOS transistor AND gate low voltage CMOS, bipolar transistor, diode and the passive electric circuit element of isolating fully, and it eliminates the demand for high-temperature technology and extension.Ideally, such manufacturing process should adopt that " injection former state " dopant profiles-this is that final dopant profiles keeps the dopant profiles that significantly do not changed from its initial dopant profiles by any subsequent wafer treatment step.Ideally, technology should be built in the module architectures, and wherein device can be added or be omitted and the processing step of correspondence is added or removed to integrated flow process, and does not change operable other device in the technology component inventory.
Summary of the invention
According to the present invention, series of process is used to the bag district of floating that isolates fully of integrated high voltage and DMOS transistor and low voltage cmos, bipolar transistor, diode and passive electric circuit element.Described technology has eliminated for the needs of high-temperature technology and extension and employing " injection former state " dopant profiles-this is that final dopant profiles keeps not by the dopant profiles of any subsequent wafer treatment step from the remarkable change of its initial dopant profiles.Integrate, described technology forms module architectures, and its permission is added or is omitted for the IC device and adds or remove the processing step of correspondence for integrated flow process, is used to produce the technology that other IC goes up device and need not to change.
Advantageously, described technology is in the formation that does not have to form and do not comprise on the substrate of extension epitaxial loayer.
Use these low temperature process, the high voltage of many uniquenesses and power device can and be integrated in the IC with the modular manner manufacturing.What comprised is the lateral DMOS of non-isolation, the extension drain electrode or the drift MOS of non-isolation stop, the lateral DMOS of lateral trench DMOS, isolation, JFET and depletion device, and the P-N diode clamp and rectifier and the knot petiolarea that are used for the low voltage component under high pressure, floated with respect to substrate.
The technology of making the DMOS device of non-isolation comprises the injection of the conformal drift region of passing field oxide layer; In the drain region in the injection of the drain region of first end of field oxide layer; Formation at the grid of second end of field oxide layer; With in injection near the tagma of second end of field oxide layer; Injection with source area in the tagma.Drift and tagma can be injected with chain and form, to produce non-Gauss's vertical dopant profile.The DMOS of non-isolation can be manufactured with drain electrode center form.In one embodiment, field oxide layer can be omitted and drift and tagma can be injected with chain and make, to produce non-Gauss's vertical dopant profile.In another series of embodiment, lateral DMOS and Zener (Zener) diode clamp forms together, to produce the more durable device of anti-the snowslide.Device can also form with the drain electrode of extending, and grid can or cannot be around drain electrode.
Make the extension drain electrode of non-isolation or the technology of drift MOS device and can produce the drain electrode central component, the drain electrode of its extension is self-aligned to grid, and grid can be around drain electrode.Device can form in non-Gauss's trap.In alternate embodiment, device is asymmetric and grid does not center on drain electrode.CMOS is to using this unsymmetric structure manufacturing.
The technology of making lateral trench DMOS (LTDMOS) can comprise the formation of trench-gate, can extend to injection near the drift layer of the bottom of groove, inject the formation of the body of former state, preferably use the chain injection of energy and DM and the formation of source electrode and drain region.This device can be made with trench-gate center form.LTDMOS can comprise can be by the dark drain region that conformal drift region centered on.Device can be made with drain electrode center form.By appropriate layout in the surface field oxide of semi-conducting material part, device can be included in groove and drain near have the conformal drift region in deep.
The technology of the lateral DMOS of make isolating typically comprises the injection with the deep layer of substrate conductivity type opposite.Inject deep layer by the opening that passes in the field oxide layer, deep layer can be the form of dish, and its edge extends upwardly to the edge of field oxide layer, to form the bag district that isolates.The tagma can be used chain to inject in the isolation pocket district and is injected into.The drift region also can be injected in the bag district.As an alternative, field oxide layer can be omitted, and deep layer is smooth substantially in this case.The bag district that isolates can use from the trap of the injection of semiconductor surface extension downwards and overlapping deep layer and form.Lateral DMOS can be with respect to the tagma symmetry.
The technology of making junction field effect transistor (JFET) can comprise and the injection of the drift region of substrate conductivity type opposite and the injection in source electrode, drain electrode and body (grid) district in the drift region.Source electrode is identical with the conduction type of drift region with the drain region; Body (grid) is identical with the conduction type of substrate.The drain region can comprise that dark chain injects.
The technology of making the depletion type MOS device can be included in the semiconductor surface top and form grid, injects the drift region that is self-aligned to grid, and injects source electrode and drain region.This technology can also comprise uses chain to inject so that form dark drain region.In alternate embodiment, the drift region is injected into prior to the formation of grid, and thereby is not self-aligned to grid.In another embodiment, dark conformal drift region is injected into prior to the formation of grid.Each previous embodiment can be modified to comprise surface shielding down, with outbreak and the inhibition snapback effect that reduces the conduction of NPN parasitic bipolar.Depletion device can also be with the form manufacturing of isolating fully, and its dark separator is overlapped by the annular sidewall isolation well, and it also can play dark drain electrode effect.
The technology of making diode can comprise to be used multiple or chain injects to form male or female, forms wherein than the deep specific surface portion higher district of concentration thus.The diode of isolating can be by injecting deep layer and in abutting connection with deep layer and around the annular sidewall in anode and cathodic region.
Technology of the present invention also can be used to form the petiolarea edge, and its P type bag district high pressure that is used for isolating is floated on the substrate.The variant of technology is included in interlayer dielectric or formation metal or polysilicon field plate are gone up in the field oxide layer top.The N trap that forms the sidewall of isolation structure can extend below field oxide layer.Another embodiment comprises the edge of overlapping N trap and the polysilicon field plate with the part of extending above field oxide layer.In another embodiment, petiolarea comprises the dark N drift region that is connected to the N trap and extends below interlayer dielectric or field oxide layer.In certain embodiments, forming the dark N floor at the end of isolation structure extends laterally to outside the isolation pocket district.
Description of drawings
Figure 1A-1G is the schematic diagram of employed various nmos switch loads (switch-load) topology in high pressure and power application: Figure 1A shows the low-side switch (LSS) of the body with ground connection; Figure 1B shows low-side switch isolation or discrete (LSS) of the source electrode-body short circuit with one; Fig. 1 C shows the high side switch (HSS) of the body with ground connection; Fig. 1 D shows high side switch isolation or discrete (HSS) of the source-body short circuit with one; What Fig. 1 E showed body with ground connection passes through transistor (pass transisitor); Fig. 1 F shows AC switch isolation or discrete of the source-body short circuit with one; Fig. 1 G shows the AC switch of the isolation with body bias generator.
Fig. 2 A-2D shows the various aspects of snapback in the lateral MOS device.Fig. 2 A is the sectional view with schematic overlapping device of parasitic NPN; Fig. 2 B shows the phenomenon of ionization by collision in the device shown in Fig. 2 A; Fig. 2 C is the I of the electrical characteristics of device
D-V
DSFigure; Fig. 2 D is the schematic illustration of device.
Fig. 3 A-3G shows the traditional handicraft of making lateral dmos device structure.Fig. 3 A shows the sectional view of complete device; Fig. 3 B shows the autoregistration body and injects; Fig. 3 C shows the body diffusion; Fig. 3 D shows the formation of using the autoregistration body that tilts to inject; Fig. 3 E shows non-self aligned body and injects; Fig. 3 F shows the stage of body diffusion; Fig. 3 G shows the formation of non-self aligned grid.
Fig. 4 A-4I is the sectional view series that the traditional handicraft that the high temperature knot of epitaxial loayer isolates is shown.
Fig. 5 A-5C illustrates the sectional view series that the low temperature of the lateral DMOS of non-isolation is made.
Fig. 6 shows the sectional view of the lateral DMOS of the non-isolation with non-Gauss P type trap and conformal N type drift region.
Fig. 7 is the sectional view with non-Gauss P type trap and lateral DMOS of the non-isolation of the drift region that comprises conformal N type chain injection trap.
Fig. 8 is the sectional view with non-Gauss P type trap and lateral DMOS of the non-isolation of even N type drift region.
Fig. 9 is the sectional view with non-Gauss P type trap and lateral DMOS of the non-isolation of the drift region that comprises uniform N type chain injection trap.
Figure 10 A-10D is the sectional view that has as the lateral DMOS of the non-isolation of the non-Gauss P type trap of DMOS body and the drain electrode of snowslide clamp.In Figure 10 A, DMOS has shallow N type drift region.In Figure 10 B, DMOS has the even N moldeed depth drift region of extending as drain electrode.In Figure 10 C, DMOS has the conformal N type drift region of extending as drain electrode.In Figure 10 D, DMOS has the conformal N type trap that extends as drain electrode.
Figure 11 A-11D shows the each side of the snowslide clamp of the non-isolation lateral DMOS that uses P body (or P yl).Figure 11 A is the sectional view of device.Figure 11 B is the schematic illustration of device.Figure 11 C shows the electrical characteristics I of device
D-V
DSThe equipotential that Figure 11 D shows in the device under high pressure distributes.
Figure 12 is the sectional view of extension drain electrode PMOS of the non-isolation of drain electrode (graded drain) with gradient.
Figure 13 is the sectional view of NMOS of extension drain electrode of non-isolation with drain electrode of gradient.
Figure 14 is the sectional view of the extension drain electrode CMOS of non-isolation.
Figure 15 A-15C illustrates the sectional view series that lateral trench DMOS makes.
Figure 16 A and 16B are respectively sectional view and vertical view, show the structure of the channel lateral DMOS with evenly dark N type drift drain electrode.
Figure 17 A-17F shows the variant of channel lateral DMOS.Figure 17 A shows and puts the P body of N trap drain electrode.Figure 17 B illustrates the field minimum oxide spacing of P body and the drain electrode of N trap.Figure 17 C shows the even drift region of extension.Figure 17 D shows the conformal drift region of extension.Figure 17 E shows the N trap drain electrode of overlapping P body.Figure 17 F shows the device with the drain electrode of N trap.
Figure 18 A-18C shows the structure of the channel lateral DMOS that is centered on by drain electrode.Figure 17 A is a sectional view.Figure 17 B is the plane graph with device of the body width that has reduced.Figure 17 C is the plane graph of the device of source electrode with stagger arrangement-body contact.
Figure 19 A-19C is the sectional view series that the lateral DMOS manufacturing of isolation is shown.
Figure 20 is the sectional view of lateral DMOS with isolation of conformal dark drift drain region.
Figure 21 is the sectional view of lateral DMOS with isolation of the N trap that the chain as the drift drain region injects.
Figure 22 is the sectional view of lateral DMOS with isolation of shallow N drift drain region.
Figure 23 is the sectional view with high pressure JFET of evenly dark drift drain region.
Figure 24 is the sectional view with depletion type NMOS of shallow LDD.
Figure 25 is the sectional view with depletion type NMOS of evenly dark drift drain region.
Figure 26 is the sectional view with depletion type NMOS of conformal dark drift drain region.
Figure 27 A-27C has the surface variant of the depletion type NMOS of source shielding down.Figure 27 A shows the device with shallow LDD drain electrode.Figure 27 B shows the device with evenly dark drift drain electrode.Figure 27 C shows the device with evenly conformal dark drift drain electrode.
Figure 28 is the sectional view of depletion type nmos device with isolation of shallow LDD.
Figure 29 A-29E is the sectional view of various Zener clamping diodes (Zener clamping diode).Figure 29 A shows N+ with non-isolation to P trap and the N+ device to P base or P body.Figure 29 B illustrates N+ with isolation device to P base or P body.Figure 29 C shows N+ with isolation device to the P trap.Figure 29 D shows the device of the Zener that N trap with many isolation buries the P trap.Figure 29 E shows P+ with isolation device to the N base.
Figure 30 A-30K is the sectional view of the high pressure petiolarea in the P type bag district that isolates.
Embodiment
U.S. Patent No. 6,855,985 have described the full low-temperature preparation method that uses injection former state (as-implanted) knot isolation structure.This method adopts the chain of the dopant that high energy and the oxide by profile inject to inject, thus bipolar, CMOS that realizes isolating fully and DMOS device and need not isolation diffusion, extension or high-temperature technology.
Theme among the application is relevant with above-mentioned patent and pay close attention to the design of clamping diode that the various new or high pressure that improve and DMOS device, snapback avoid, isolate and rectifier and integrated, and the low-voltage device in the bag district that will isolate is floated on the high-tension method more than the substrate electric potential.
The low-temperature preparation method of high tension apparatus described herein is compatible with the module low-temperature preparation method described in aforesaid patent and patent application, but need not to be confined to the module process framework.
Wafer is made
Unless specify, this say the manufacturing of the high pressure described and power device use with at identical process sequence described in the above-mentioned patent.The brief overview of typical process flow comprises:
Field oxide forms
The groove and the trench-gate that comprise planarization form
High energy injects dark drift layer (ND) and forms
Chain injects groove DMOS body (P body) and forms
Phosphorus high energy injects end isolation (DN) and forms
First chain injects non-Gauss N trap (NW1/NW1B) and forms
First chain injects non-Gauss P trap (PW1/PW1B) and forms
Second chain injects non-Gauss N trap (NW2/NW2B) and forms
Second chain injects non-Gauss P trap (PW2/PW2B) and forms
Dual gate oxide and gate electrode form
The N base injects
The P base injects
The one N-LDD injects (NLDD1)
The one P-LDD injects (PLDD1)
The 2nd N-LDD injects (NLDD2)
The 2nd P-LDD injects (PLDD2)
Sidewall spacer forms
ESD injects
N+ injects
P+ injects
Rapid thermal annealing (RTA injects activation)
The multiple layer metal interconnection process
Passivation
Because having used, described technology has dopant profiles few or the injection former state that no dopant distributes again, can carry out with in fact any order so inject, except injecting, preferred P trap and N trap form prior to grid, trench-gate forms and injects prior to the DMOS body, but N-LDD and P-LDD inject and follow grid and form form prior to sidewall spacer, and N+ and P+ inject and follow outside sidewall spacer forms.This technological process is designed to module, therefore can delete one or more processing steps according to this that group device of IC design needs for the manufacturing of given IC.
For example, table 1 has been summarized the preferred embodiment of described injection in this application and the scope of preferred condition.
Table 1
| Inject (nucleic) | Preferred embodiment (energy, dosage) | Preferable range (energy, dosage) |
| DN(P +) | E＝2.0MeV，Q＝2E13cm -2 | E=1.0MeV to 3.0keV, Q=1E12 to 1E14cm -2 |
| ND (the P that drifts about deeply +) | E＝800keV，Q＝2E12cm -2 E＝600keV，Q＝2E12Gm -2 | E=400keV to 1.2MeV, Q=5E11 to 5E12cm -2E=300keV to 900keV, Q=5E11 to 5E12cm -2 |
| P body (B +) | E＝120keV，Q＝2E12cm -2 E＝80keV，Q＝4E12cm -2 | E=60keV to 180keV, Q=5E11 to 5E12cm -2E=40keV to 120keV, Q=1E12 to 1E13cm -2 |
| The one P trap+(B +) | E＝240keV，Q＝1E13cm -2 E＝120keV，Q＝6E12cm -2 | E=120keV to 360keV, Q=5E12 to 5E13cm -2E=60keV to 180keV, Q=1E12 to 1E13cm -2 |
| The one N trap+(P +) | E＝460keV，Q＝5E12cm -2 E＝160keV，Q＝1E12cm -2 | E=230keV to 690keV, Q=1E12 to 1E13cm -2E=80keV to 240keV, Q=5E11 to 5E12cm -2 |
| The 2nd P trap+(B +) | E＝460keV，Q＝1E13cm -2 E＝160keV，Q＝1E12cm -2 | E=230keV to 690keV, Q=5E12 to 5E13cm -2E=80keV to 240keV, Q=5E11 to 5E12cm -2 |
| The 2nd N trap+(P +) | E＝950keV，Q＝1E13cm -2 E＝260keV，Q＝1E12cm -2 | E=500keV to 1.5MeV, Q=5E12 to 5E13cm -2E=130keV to 390keV, Q= |
| 5E11 to 5E12cm -2 | ||
| N base (P +) | E＝300keV，Q＝2E12cm -2 E＝120keV，Q＝9E12cm -2 | E=150keV to 450keV, Q=5E11 to 5E12cm -2E=60keV to 180keV, Q=5E12 to 5E13cm -2 |
| P base (B +) | E＝240keV，Q＝6E12cm -2 E＝100keV，Q＝6E12cm -2 | E=120keV to 360keV, Q=1E12 to 1E13cm -2E=50keV to 150keV, Q=1E12 to 1E13cm -2 |
| NLDD1(P +) | E＝80keV，Q＝2E13cm -2 | E=40keV to 160keV, Q=5E12 to 5E13cm -2 |
| PLDD1(BF 2 +) | E＝80keV，Q＝2E12cm -2 | E=40keV to 160keV, Q=5E11 to 5E12cm -2 |
| NLDD2(P +) | E＝80keV，Q＝6E12cm -2 | E=40keV to 160keV, Q=1E12 to 1E13cm -2 |
| PLDD2(BF 2 +) | E＝100keV，Q＝3E12cm -2 | E=50keV to 150keV, Q=1E12 to 1E13cm -2 |
| N+(As +) | E＝30keV，Q＝5E15cm -2 | E=20keV to 60keV, Q=1E15 to 1E16cm -2 |
| P+(BF 2 +) | E＝30keV，Q＝3E15cm -2 | E=20keV to 60keV, Q=1E15 to 1E16cm -2 |
Several above injections can be used to form the drift region of high tension apparatus potentially, thereby because the total enough low support of implantation dosage both sides exhaust expansion, and before of the outbreak of some situations, allow exhausting fully of layer in avalanche breakdown.The phenomenon that under high pressure reduces the surface field in the device thus by exhausting limited implantation dosage district (or electric charge) fully is also referred to as " RESURF ", the English acronym of the surface field that reduces.In history, term " RESURF " is used for the epitaxial loayer of limited electric charge and LDD, drift region or drain electrode are extended and censured the layer that is injected into.At this, as broad as long between the advantage of shallow LDD and dark drift region, except shallow LDD district typically is self-aligned to the mos gate utmost point and dark high energy injects drift region (for example ND injects) typically prior to the grid formation.
In one embodiment of this invention, more than the table in first and second traps refer to 5V and the 12V P trap that is used to make 5V and 12V CMOS.Term 5V and 12V are not used in restriction but only are used to describe two N type trap concentration that different P type trap concentration is different with two, for example 3V and 15V, 12V and 30V, 1.5V and 3V etc.Usually the trap of low voltage trends towards the more important place doping of more high-tension trap, especially near silicon face, but for the combination that comprises the various injections that dosage is different with energy, be non-Gauss's dopant profiles that chain injects, the trap of low voltage is not necessarily gone up the higher person at peak concentration, mean concentration or total electric charge (dosage) that injects.It is darker that the trap of high voltage also is tending towards being compared to the N trap of low-voltage device.For example in one embodiment, the N trap of 5V CMOS and P trap use the injection of the average expectation scope with 0.4 to 0.5 micron, and the required trap of 12V CMOS has in active area the average expectation scope of the degree of depth between 0.7 to 1.1 micron.The degree of depth below the injection period field oxide has reduced the thickness of layer roughly.Dark N type drift can have in active area similar in appearance to the 12V trap or the darker slightly degree of depth.
Bidimensional Electric Field Distribution when such trap depends on the snowslide outbreak as the applicability of the drain electrode of drift region or extension.In non-gaussian sum reversing dopant profiles, not resembling in comprising the conventional diffusion trap of pure Gauss's dopant profiles, surface field and puncture voltage do not follow concentration simply.
Consistent with this observation, each trap is described by two figure elements in subsequent figure, and the top for example is labeled as first trap of PW1; And bury or bury the P trap than first of the PW1B that is labeled as in deep.In order to bury below the top of trap, buried portion is injected so that arrive the darker degree of depth with higher energy.Typically the buried portion of trap is also used specific surface portion higher implantation dosage and is showed higher peak concentration, promptly dopant profiles will be reversing-in body than higher in surface concentration, although for manufacturing not necessarily.Reversing distributes and cannot use the conventional diffusion knot to be produced, and need not the epitaxial deposition and the diffusion of high temperature buried layer of previously described costliness.
In fact trap can comprise the injection of any amount of different-energy and implantation dosage, so that be created in all useful dopant distribution arbitrarily in low voltage CMOS and the high tension apparatus manufacturing.For the sake of clarity we refer to top and bottom trap uniquely and always, and we describe it all as a trap.For example, PW1 and PW1B constitute first trap (for example, for the 5V device) together, and PW2 and PW2B are formed in more second trap of high voltage operation together.Usually, second trap is mixed lightlyer, can be the candidate preferably as the work of high voltage drift region, if but in fact its surface concentration is higher then poorer.In principle, peak concentration and electric field come across in the semiconductor than the depths in the design high tension apparatus, leave the surface, should cause at the useful more solid device of high voltage.
Use aforementioned technology framework, the high pressure of many uniquenesses and power device are can be with modular manner manufactured and in conjunction with entering IC.These new high tension apparatus comprise the extension drain electrode of the lateral DMOS of non-isolation, non-isolation or the MOS device of drift, the lateral DMOS of lateral trench DMOS, isolation, JFET and depletion device, and the knot petiolarea of P-N diode clamp and rectifier and the low voltage component floated with high voltage with respect to substrate.
The lateral DMOS of non-isolation
Using a class high voltage transistor of use low-temperature preparation method described here manufacturing is the lateral DMOS transistor of non-isolation.
In Fig. 5 A-5C, show the manufacturing of the lateral DMOS transistor 200 of non-isolation with sectional view.Described technology comprises that the energetic ion by the lightly doped N type drift region of the oxide of profile injects.As shown in Fig. 5 A, use LOCOS (for example) is formed at the injection profile field oxide layer 204 in the substrate 201, optionally inject with photoresist 202 masks and with the drift of high energy phosphorus, thereby form conformal drift region 203 heterogeneous, than superficial part 203A below oxide 204 and than deep 203B and 203C below the active area that is not covered by field oxide layer 204.(annotate: as used in this, term " conformal " is censured the district of dopant or floor (a) and is formed by floor (often the being oxide skin(coating)) injection on the surface of semi-conducting material, and (b) its vertical thickness in semi-conducting material and/or the degree of depth change according to the thickness and/or the further feature of superficial layer, are included in any opening that forms in the superficial layer.) do not have injection to penetrate mask 202.The superficial drift region 203A of total mark charge Q of dark active area 203B and 203C is big.The total electrical charge that exists in silicon is provided by following formula:
Wherein at the situation x of active area
1=0, i.e. silicon face.For the injection below field oxide, x
1It is the interface between field oxide and the following silicon.Because it is identical being infused in two districts, the dopant in the silicon below field oxide is than lacking in the active area.Below transition region from oxide-free to through thickness, i.e. beak district, the electric charge that always drifts about has gradient, a kind of artefact of nature of disclosed manufacturing process.
As shown in Fig. 5 B, inject by the ion that passes photoresist mask 205, P trap 206 is introduced into the zone adjacent to drift region 203.In final devices, but this P trap will play the body of lateral DMOS form prior to grid because of it, so it is not self-aligned to transistorized grid.And have its peak concentration near the surface and to reduce the conventional diffusion trap of concentration monotonously different along with the increase of the degree of depth, P type trap 206 forms by the energetic ion injection of boron, and the boron chain injection of preferably injecting by a series of boron that comprise dosage and energy changing forms.Chain injects, though it can comprise any amount of injection, in the drawings with two district diagram-superficial layer PW1 and the surperficial PW1B of lower floor, injects formation by the ion that passes single mask and need not to use extension.In a preferred embodiment, the concentration of darker layer specific surface trap is higher.
In Fig. 5 C, N trap 207 is introduced into the drain region of the DMOS of 203C inside, N type drift region, and reducing transistor drain resistance, and the electric field in the drain electrode that further is shaped is so that the ionization by collision before reducing snowslide.Distribute for fear of the dopant from High temperature diffusion, N trap 207 uses the energetic ion of phosphorus to inject and forms again, and the phosphorus chain injection of preferably injecting by a series of phosphorus that comprise dosage and energy change forms.Chain injects, though it can comprise any amount of injection, in the drawings with two district diagram-superficial layer NW1 and the surperficial NW1B of lower floor, injects formation by the ion that passes single mask and need not to use extension.In a preferred embodiment, the concentration of darker layer specific surface trap is higher.
Though sectional view shows a P trap 206 and a N trap 207, it for example can represent P trap PW1 and the N trap NW1 that is used for 5VCMOS, but also can use CMOS, for example the 2nd P trap of 12V or 20V device optimization and the 2nd N trap, for example PW2 and NW2 for other voltage.
After trap formed, gate oxide 209 was grown, polysilicon layer be deposited and composition so that form grid 208.This grid preferred orientation is in a part of P type trap 206 and a part of drift layer 203 tops, to guarantee suitable transistor action.
Except its full low temperature manufacturing be integrated into the full module process framework, N channel laterally DMOS device 200 also provides the advantage of the lateral DMOS that surpasses the tradition manufacturing, comprises that the less hot carrier that is caused by its lower trap surface concentration produces the surface field that reduces under the pairing grid; By electric field under the surface of the heavily doped raising that causes than the deep of P trap 206, force avalanche breakdown to enter body and leave semi-conductive surface; And the lower conducting resistance of improving gain and being caused by the short length of the grid 208 that is positioned at top part of active area, short grid is injected the subvertical sidewall structures of P trap 206 and is become possibility by chain.In contrast, diffusion trap DMOS requires the bigger lateral dimension of long grid with covering high-temperature diffusion trap.
The example of drain electrode central cross DMOS 220 that uses the drift of non-Gauss P type trap and conformal N type is shown in the sectional view of Fig. 6.Described device comprises conformal drift 223 in field oxide layer 222, N trap drain electrode 235, N+ drain electrode 236, have light dope extend 230 N+ source electrode 228, P+ body contact 229, polysilicon gate 226 and be formed on gate oxide 225 tops on the silicide 227, interlayer dielectric (ILD) 233, metal interconnected 231 and the contact barrier metal 232 that cover.Drift length L
D1, the extremely effectively edge metering of N trap NW1 of edge as from effective grid can be adjusted the puncture voltage with selector, and change manufacturing process indistinctively.In this device, the DMOS body is formed by the P trap 224A and the 224B that can comprise bar how much shapes or annular geometry, and described geometry is surrounded the drain electrode on all or a few side.(annotate: as used in this, term " annular " refers to doped region or other structure that laterally centers on the feature in the IC chip.Annulus or structure can be circle, pros, rectangle, polygon or any other shape, and annulus or other structure can or can not contact with the feature that it laterally centers on.) the P trap on non-Gauss or non-dull distribution that comprises that goes out as shown represented by top PW1 and surperficial bottom PW1B, here PW1B more mixes in the important place than PW1 in a preferred embodiment, and P trap 224A comprises that with 224B dosage a series of chains different with energy inject in alternate embodiment.
Fig. 7 shows the non-isolation lateral DMOS 240 that has non-Gauss P type trap and comprise the drift of the trap that conformal N type chain injects with sectional view.Described device comprises conformal drift 243 in field oxide layer 242, N+ drain electrode 256, have light dope extend 250 N+ source electrode 248, P+ body contact 249, polysilicon gate 246 and be formed on gate oxide 245 tops on cover silicide 247, ILD253, have metal interconnected 251 of contact barrier metal 252.In this device, the DMOS body is formed by the P trap 244A and the 244B that can comprise how much shapes of bar or annular geometry, surrounds drain electrode in all or a few side.Each P trap 244A and 244B are illustrated, it comprises by the non-Gauss of top PW1 and surperficial bottom PW1B representative or non-dull the distribution, here PW1B more mixes in the important place than PW1 in a preferred embodiment, and P trap 244A comprises that with 244B dosage a series of chains different with energy inject in alternate embodiment.
The drift 243 that the N trap that is injected by chain constitutes comprises deep NW1B and than superficial part NW1.Be located in the active area than superficial part NW1, for example 243B.For example the passive region of 243A only comprises deep NW1B, reduces to contact drain resistance and does not increase electric field below the gate oxide 245.Drift length L
D1, to the effective edge of N trap NW1, can be adjusted inapparent change manufacturing process with the puncture voltage of selector from the edge metering of effective grid.Usually, in the drift higher total mark electric charge preferably in low pressure drift drain device.The one N trap and P trap can be substituted by the 2nd N trap and P trap in the combination that changes, and depend on the predetermined voltage range of dopant distribution and device.
Fig. 8 shows the non-isolation lateral DMOS 260 that comprises (under the oxide that is absent from the scene) the non-Gauss P type trap that only forms and the drift of N type in active area with sectional view.Device comprises drift 263, N trap drain electrode 265, N+ drain electrode 276, have light dope extend 270 N+ source electrode 268, P+ body contact 269, polysilicon gate 266, be formed on gate oxide 265 tops on cover silicide 267, ILD 273, have metal interconnected 271 of contact barrier metal 272.In this device, the DMOS body is formed by the P trap 264A and the 264B that can comprise bar how much shapes or annular geometry, surrounds to drain on all or a few side.The P trap 2 that illustrates comprises by the non-Gauss of top PW1 and surperficial bottom PW1B representative or non-dull the distribution, here PW1B more mixes in the important place than PW1 in a preferred embodiment, and P trap 264A comprises that with 264B dosage a series of chains different with energy inject in alternate embodiment.
Source metal interconnection 271A and 271C be illustrated in grid 266 tops and outside extend so that overlap part drift 263.This optional layout allows source metal to play field plate so that reduce to assemble near the electric field of grid end, increases the puncture voltage of DMOS 260 thus.Notice that this layout is optionally and also to be applied in this specification all other DMOS.
Fig. 9 shows with sectional view to have non-Gauss P type trap and comprises that even N type chain injects the non-isolation lateral DMOS 280 of the drift region of trap.Device uses N trap 283, the N+ drain electrode 296 comprise the chain that only is formed at (below the oxide that is absent from the scene) in the active area and to inject, have N+ source electrode 288, P+ body contact 289, polysilicon gate 286 that light dope extends, be formed on gate oxide 285 tops on cover silicide 287, ILD 282, have metal interconnected 291 of contact barrier metal 292.In this device, the DMOS body is formed by the P trap 284A and the 284B that can comprise bar how much shapes or annular geometry, surrounds to drain on all or a few side.Each P trap 284A and 284B are illustrated, comprise by the non-Gauss of top PW1 and surperficial bottom PW1B representative or non-dull the distribution, here PW1B more mixes in the important place than PW1 in a preferred embodiment, and P trap 284A comprises that with 284B dosage a series of chains different with energy inject in alternate embodiment.
Drift is injected N trap 283 by chain and is constituted, comprise by the non-Gauss of top NW1 and surperficial bottom NW1B representative or non-dull the distribution, here NW1B more mixes in the important place than NW1 in a preferred embodiment, and P trap 284A comprises that with 284B dosage a series of chains different with energy inject in alternate embodiment.
From the edge of grid 286 to the drift length L of the edge metering of N+ drain electrode 296
D1Can be adjusted, change manufacturing process with the puncture voltage of selector indistinctively.Usually, in the drift higher total mark electric charge preferably in low pressure drift drain device.The one N trap and P trap can be substituted by the 2nd N trap and P trap in the combination that changes, and depend on the predetermined voltage range of dopant distribution and device.
In Fig. 9, N+ source electrode 288 is illustrated with P+ body contact 289 and separates, and source metal interconnection 291B is illustrated with the metal interconnected 291A of body and separates.This optional layout allows source voltage to be floated on the bulk voltage, in the restriction of source electrode to bulk breakdown voltage (typically being several volts), and can be used to allow to detect the electric current that flows through DMOS 280.Notice that this layout is optionally and can also be applied in this specification all other DMOS device.
Attention only is schematic purpose in the many features shown in Fig. 6-9, and for the improvement of these structures within the scope of the present invention.For example, the light dope source electrode of Fig. 6 extends 230 work for the LDMOS device not to be needed, and wherein this district can be provided in fact better on state characteristic by the alternate embodiment that more heavily doped source electrode extension is substituted.Though in these examples, only shown metal interconnected individual layer, but preferred embodiment comprises the metallized extra play of the conductive resistance that is used to reduce the DMOS device certainly, and also can form source electrode and/or drain electrode field plate, the inside connection (bussing) of grid etc.Metal layer is illustrated and extends into the ILD layer, but other preferred embodiment will use metal bolt (for example tungsten) with contact hole in the filling ILD layer and the planar metallised layer on the top of ILD layer.Field oxide layer is illustrated so that comprise LOCOS, but for example deposition or growth and return oxide constantly, recessed oxide and the alternative structure of non-oxidized substance dielectric substance and also can be used.
Figure 10 A-10D shows the variant of the aforementioned lateral DMOS with Zener diode clamp.This produces the device of more durable anti-snowslide, both just because the puncture voltage that exists of clamp is lowered.The durability that increases causes away from the mos gate utmost point by forcing snowslide to enter the following body silicon of drain electrode.
In the lateral DMOS 300 of Figure 10 A, for example, the Zener clamp comprises the P traps 319 that are positioned at below the N+ drain electrode 311.Identical P trap implantation step can be used to form P trap 319 and P trap 302, non-Gauss's body of lateral DMOS 300.As an alternative, different P trap implantation steps can be used to form P trap 319 and 302.The P trap 319 and 302 that goes out as shown comprises non-Gauss or nonmonotonic distribution, is represented by top PW1 and surperficial bottom PW1B.In a preferred embodiment, PW1B more mixes in the important place than PW1, and comprises that in alternate embodiment the chain of the multiple injection that dosage is different with energy injects.The drain electrode extension comprises the shallow N-drift 310 that also can be used to the 12V nmos device in this device.The remaining element of this device is similar to aforementioned lateral DMOS, comprises N+ source electrode 304, P+ body contact 303, gate oxide 307, polysilicon gate 308, silicide 309, sidewall spacer 306, N-source electrode extension 305, ILD 315, barrier metal 312 and metal interconnected 313.
In Figure 10 B, illustrated and had the snowslide clamp lateral DMOS 320 that high energy injects drift 330 and P trap clamp 334, similar in appearance to the voltage clamp version of the DMOS 260 of Fig. 8.
In Figure 10 C, illustrated and had the snowslide clamp lateral DMOS 340 that conformal high energy injects drift 350 and P trap clamp 342B, similar in appearance to the voltage clamp version of the DMOS 220 of Fig. 6.
In Figure 10 D, illustrated and used P trap clamp 362B and inject another snowslide clamp lateral DMOS 340 of N trap 370A, similar in appearance to the voltage clamp version of the DMOS 240 of Fig. 7 as the chain of drift.
The device that is to be understood that Figure 10 A-10D is depicted as symmetry, and the center line of device is on the right side of figure.But this not necessarily.
Compared with the P trap, the drain voltage clamp also can use more shallow p type island region to realize.In the lateral DMOS 380 of Figure 11 A, for example, the Zener clamp comprises P base or the P bodies 394 that are positioned at below the N+ drain electrode 393.P-trap 382 forms the body of lateral DMOS 380, comprises by the non-Gauss of top PW1 and surperficial bottom PW1B representative or non-dull the distribution.In a preferred embodiment, PW1B more mixes in the important place than PW1, and comprises that in alternate embodiment the chain of the multiple injection that dosage is different with energy injects.The drain electrode extension comprises the shallow N-drift region 392 that also can be used to the 12V nmos device in this device.The remaining element of device comprises N+ source electrode 384, P+ body contact 383, gate oxide 387, grid 388, silicide 389, sidewall spacer 386, N-source electrode extension 385, ILD 391, barrier metal 396 and metal interconnected 395 similar in appearance to the element in aforementioned lateral DMOS device.
The schematic electronic circuit 400 of Figure 11 B schematically shows the notion of integrated lateral DMOS voltage clamp, and NMOS 401 shows N raceway groove DMOS here, and diode 402 representatives are not by the transistorized BV of clamp
DSS, and Zener diode 403 shows integrated drain voltage clamp.
Figure 11 C illustrates the I of voltage clamp lateral DMOS
D-V
DSCharacteristic 410.Family of curves 412,413,414 and 415 representatives are corresponding to the increase drain current that increases gate driving.Under higher electric current, the maximum voltage BV that keeps
CERShown by curve 416, in fact be independent of gate driving.This voltage is markedly inferior to by curve 411 shown closed conditions and punctures BV
DSSFrom BV
DSSPuncture 411 to low BV
CERValue 416 the snapback can cause excessive electric current and device failure.In order to avoid the snapback utterly, be depicted as the Zener breakdown voltage BV of curve 418
Z2Must be set to be lower than BV
CER416.The voltage clamp of this degree is the operating voltage range of deboost clamp lateral DMOS to heavens.But note curve 413 shows significantly negative resistance requires certain levels of current I
D1To start the snapback, be lower than BV
DSSBut be higher than BV
CERBy curve 417 shown clamping voltage BV
Z1Can be enough to realize durable work and need not restraint of labour voltage range significantly.
Figure 11 D is action and its sectional view 430 for the simplification of the influence of equipotential line 438 that the drain voltage clamp is shown.In this device, the voltage that puts in the N+ drain electrode 439 causes that N-drift 440 exhausts, and allows equipotential line 438 to stride across drift region 435 with voltage increment 0, V
1, V
2And V
3Expansion keeps the low electric field near gate oxide 432 and grid 433 thus.The effect of P type layer 437 is the electric fields that increase below the drain electrode 439, equipotential line is pressed together and forces puncture in this district, and this district is away from grid 433.
In a word, voltage-clamp method described herein has improved lateral DMOS snowslide ability by puncture place being moved away grid, thereby the puncture that has reduced device has improved the survival rate that device is subjected to the EOS influence.
Drain MOS is extended in non-isolation
Drain avalanche clamp notion also can be applied to the device outside the lateral DMOS, and described device comprises lightly doped drain (LDD) drain electrode extension MOS transistor.In such device, drain electrode is extended or " drift " L
DLength the length than the sidewall spacer of grid is long usually, typically from half micron length that goes up to tens microns.The lateral DMOS that is centered around the source electrode that grid extends below with more heavily doped trap or body is different, and non-DMOS device adopts laterally trap concentration uniformly, at least in active area.Dopant profiles in P trap described herein and the N trap is to inject former state, and not by needing the traditional means production of long-time High temperature diffusion.Vertical dopant profile in device promptly perpendicular to the surface of wafer, can thereby comprise non-dull distribution of non-gaussian sum that is used to optimize conducting state conducting and closed condition blocking performance.
In this joint, title " non-isolation " refers to and lack the injection that high energy injects the special use that the end below the one or more devices of DN layer-be used to form isolates in device.Do not have DN to inject, any P trap all by electrical short in P type substrate, mean that the body of all non-isolation nmos pass transistors or raceway groove need be grounded.On the other hand, P-channel device is formed in the N trap and naturally and is need not the DN layer by self-isolation.But because the surperficial lower part of N trap portion does not typically have DN layer doping content height, thus the N trap for the substrate current of avoiding autoparasitism PNP conducting (drain electrode of P type should become for N trap forward bias) if ability good not as the DN layer around PMOS N trap.
Figure 12 shows the sectional view that drain electrode PMOS 450 is extended in non-isolation.The device that goes out as shown be symmetry and drain electrode center-mean P+ drain electrode 463 goes out as shown on both sides is centered on by grid 458 (comprising silicide 459), source electrode 454 and N+ trap-contact 453.Device can use how much shapes of bar to be configured or it can constitute totally enclosed rectangle or polygon edge shape.Gate oxide 457 can comprise the first thin gate oxide or be used for the thicker gate oxide of higher voltage devices.The drift length L of autoregistration P-drift layer 462
D1By determining, rather than determined by sidewall spacer 460 from the distance of grid 458 to P+ drain electrode 463.As the result that sidewall spacer 460 exists, lightly-doped source polar region 455 forms.This district can use the existing LDD compatible with low pressure PMOS device to inject and be injected into, and perhaps it can use the special use of optimizing for PMOS 450 to inject.Use has metal interconnected 465 contacts of carrying out by ILD 461 of following barrier metal 464.
As shown, N trap 452A, 452B comprise non-Gauss or non-dull the distribution, by top NW1 and surperficial bottom NW1B representative.In a preferred embodiment, NW1B more mixes in the important place than NW1, and N trap 452A, 452B comprise that the dosage a series of chains different with energy inject in alternate embodiment.Because N trap 452A, 452B form after field oxide layer 456, so its junction depth is more shallow below field oxide, as shown by district 452B, and district 452B can only comprise the part NW1B that buries of N trap significantly.The second trap NW2 with buried portion NW2B can be used to substitute a N trap.
Drain electrode is extended or drift region 462 comprises the preferred shallow injection that forms grid 458 and field oxide layer 456 after, and thereby is self-aligned to these layers fully.As shown, drift region 462 by grid 458 around and contact or in abutting connection with field oxide layer 456 never.
Figure 13 shows the sectional view that extends drain electrode NMOS 470 similar in appearance to the non-isolation of PMOS 450.The NMOS 470 that goes out as shown is symmetry and drain electrode center; Mean that N+ drain electrode 483 is centered on by grid 478 (comprising silicide 479), source electrode 474 and N+ trap-contact 473 in both sides.Device can use how much shapes of bar to be configured or it can constitute the rectangle or the polygon edge shape of complete closed.Gate oxide 477 can comprise the first thin gate oxide or be used for the thicker gate oxide of higher voltage devices.The length L of self aligned N drift region 482
D1Distance by grid 478 to N+ drain electrodes 483 is determined, rather than is passed through sidewall spacer 480.As the result that sidewall spacer 480 exists, lightly-doped source polar region 475 forms.Lightly-doped source polar region 475 can use the existing LDD compatible with the low pressure nmos device to inject and be injected into, and perhaps it can use the special use of optimizing for NMOS 470 to inject.Use has the metal interconnected contact of carrying out by ILD 481 of following barrier metal 484.
As shown, P trap 472A, 472B comprise non-Gauss or non-dull the distribution, by top PW1 and surperficial bottom PW1B representative.In a preferred embodiment, PW1B more mixes in the important place than PW1, and P trap 472A, 472B comprise that the dosage a series of chains different with energy inject in alternate embodiment.Because P trap 472A, 472B form,,, and can only comprise the buried part PW1B of P trap significantly as in district 472B so the joint degree of depth below field oxide 476 is more shallow after field oxide layer 476.The second trap PW2 with buried portion PW2B can be used to substitute a P trap.
Drain electrode is extended or drift region 482 comprises the preferred shallow injection that forms grid 478 and field oxide layer 476 after, and thereby is self-aligned to these layers fully.In the device that illustrates drift region 482 by grid 478 around and contact or in abutting connection with field oxide layer 476 never.
Optionally NB layer 486 comprises or the injection of N body, the injection of N base or another special-purpose injection, and optional NB layer 486 is introduced into around N+ drain electrode 483 so that reduce to center on the surface field of drain electrode by graded concentration.Except reducing surface field, it can also improve transistorized snowslide durability by the drain break down of snowslide under the surface by reducing.
Non-isolation drain electrode extend PMOS 450 and NMOS 470 can be modified for drain electrode wherein not on all sides by device that grid centered on.Figure 14 shows the schematic section of the asymmetric extension drain electrode cmos device that comprises PMOS 500A and NMOS 500B, wherein drain electrode extend on the side adjoins gate and on other one or more sides in abutting connection with field oxide.
Similarly, asymmetrical drift NMOS 500B is formed in the P trap 503 and comprises N+ drain electrode 504B, on a side, and length L
DN1The drift region 509A of N-between two parties between N+ drain electrode and its grid 511B.The 2nd N-drift region 509B of length L DN2 is interposed between drain electrode 504B and the field oxide layer 516.Drift region 509A, drift region 509B extend 508 with source electrode can use identical implantation step, the NLDD2 of above-mentioned flow process and forming for example, perhaps they can form by implantation step separately, should be optimized individually for its concrete function by implantation step separately.The L of drift region 509A and 509B
DN2And L
DN1Also can be optimized separately for its function.For example, the length of drift region 509B and resistivity are important for the BV that determines NMOS, but do not influence the conduction property or the hot carrier reliability (HCI) of device, and the doping of drift region 509A and length are for BV, conducting resistance and HCI implication.In one embodiment, deliberately make the BV of drift region 509B be lower than the BV of the first drift region 509A, make to puncture always away from grid 511B.
In a preferred embodiment, source electrode extend 508 by heavy doping so that low resistance from the source electrode of NMOS to raceway groove is provided, and drift region 509A has different dopant profiles, it is optimized to support drain breakdown voltage and good HCI is provided.In another embodiment, drift region 509A also comprises the second area near the higher-doped of N+ drain region, so that the classification drift region of balance doping preferably between conducting resistance and the HCI to be provided.Drift region 509A also can be injected into so that by allowing most electric current to distribute away from the mobile reversing that improves HCI of the gate oxide-silicon interface of sensitivity by higher energy.
The structure of PMOS 500A and NMOS 500B and manufacturing are similar in appearance to the PMOS and the nmos device of Figure 12 and 13 in addition.P+ injects source electrode 505A and the drain electrode 505B that forms PMOS 500A, and it forms the P trap contact 505C among the NMOS 500B simultaneously.In contrast, N+ is infused in and forms source electrode 504C and drain electrode 504B among the NMOS500B, and it forms N trap contact 504A in PMOS 500A simultaneously.The gate oxide 510A of PMOS 500A and NMOS 500B can be identical with 510B or can be optimized individually.
Also can be used among PMOS 500A and the NMOS 500B at PB layer 466 shown in Figure 12 and 13 and NB layer 486.As an alternative, darker injection can be used to force the following puncture of drain electrode and enter body silicon.In PMOS 500A, optionally can be masked and be injected into N trap 502 in N type district 498, so that increase concentration partly and be reduced in the puncture of the knot that forms between P+ drain electrode 505B and the N trap 502.Similarly, in NMOS 500B, p type island region 499 can be masked and be injected into P trap 503, to increase concentration partly and to be reduced in the puncture of the knot that forms between N+ drain electrode 504B and the P trap 503.
Lateral trench DMOS
Compare with the DMOS transistor with aforesaid " smooth " MOS that has on the top that is positioned at silicon face and below the grid of silicon face, form the MOS raceway groove, lateral trench grid DMOS transistor (LTDMOS) use trench-gate with control perpendicular to rather than be parallel to the side channel current vertically downward of the etched groove of wafer surface.DMOS is different with vertical trench, and channel current vertically passes entire substrate and flows and flow out its dorsal part here, flows back at electric current before the drain electrode contact on the top surface of wafer, and LTDMOS its vertical-channel electric current that leads again laterally enters its drain electrode.LTDMOS than conventional planar MOS transistor three-dimensional many.Trench gate structure although more be difficult to make than planar gate device, gives some advantage for the electrical characteristics of device.
Use 0.4 micron or littler groove opening, the surface area that grid is littler than conventional MOS transistor dissipation especially requires 5 volts of devices of 0.5 to 0.6 micron grid length; Typically require 0.8 micron or 12 volts of bigger devices; With 20 volts or higher voltage requiring until 4 microns even longer grid length.So saving the space is the simple benefit of trench-gate.
Another benefit of LTDMOS is to use a series of chains of different-energy and dosage to inject forming its ability of fully self aligned grid, thereby produces box-shaped and other non-Gauss and/or non-dull dopant distribution and need not high-temperature technology or diffusion for a long time.These unique dopant distribution can be challenged, and to help to reduce to expand into the exhausting of raceway groove, suppress short-channel effect, and suppress the break-through raceway groove and leak and puncture, and the threshold limit changeability.
Compare with the lateral DMOS of conventional construction, the vertical injection of LTDMOS described herein is simple with easily, only spends several seconds to inject whole DMOS body and need not High temperature diffusion.This method is for 12 to 24 hours required High temperature diffusion of DMOS device in Fig. 3 C 105, or the thundering inclination of lateral DMOS 110 is injected in Fig. 3 D, requirement to avoid the direction mismatch of device and gate orientation, is sharp-pointed contrast in accurate wafer rotation of injection period.And different with traditional DMOS device 120 of Fig. 3 G, LTDMOS fully self aligned of the present invention makes puncture and ionization by collision more one make peace and can repeat in grid.
Another benefit of the three-dimensional structure of LTDMOS is the ability of separating district with the district of high electric field of high current density, suppresses among Fig. 2 B ionization by collision and undesirable drift thus and conducts electricity mudulation effect.Device can also be designed so that make gate oxide be subjected to low-down electric field, and for example when device was in avalanche breakdown, grid also only needed to support several volts.The low electric field that strides across grid allows thin gate oxide to be used in the device configuration, and the driving of minimizing grid voltage requires and keeps low on-resistance, both just for high tension apparatus.
Because LTDMOS comprises its tagma in its drain electrode, and comprise its source electrode in its body, institute is so that utilize the short circuit of source electrode body in entire device equably, and need not the substrate of short circuit body to ground connection.Provide the ability of " part " body contact to reduce source electrode-body shunt resistance R
SB, suppress effectively thus or even eliminated snapback's phenomenon of the device 60 among puzzlement Fig. 2 A.
Another advantage is by using full low temperature process, and LTDMOS makes does not influence or influence in addition in the integrated technology the integrated of other bipolar and cmos device, and support device comprise and get rid of and with the processing step of the correspondence of modular manner.Adopt full low temperature process, make and be not limited to the minor diameter wafer.
Figure 15 A to 15C shows some committed steps of making according to the full low temperature of LTDMOS of the present invention.With reference to figure 15A, the manufacturing of LTDMOS 550 begins with etching, oxidation, polysilicon deposition and planarisation step, to produce the trench-gate 552 with polysilicon gate 554 and gate oxide 553 in substrate 551.Dark drift (ND) district 555 is injected by high energy or chain subsequently and introduces, to typically near the degree of depth of the degree of depth of the bottom of groove 552, although the more shallow or darker degree of depth also is fine.The ND district that formation is darker than groove 552 for example, can be used to further to reduce be applied to grid electric field in the employed lateral trench DMOS device at high side switch.
Shown in Figure 15 B, technology also comprises the formation of the P type body 559 that injects former state, and preferred the use changes the chain that boron injects energy and dosage and inject optionally patterned photoresist 556 masks.Body inject can prior to or follow the formation of optional N trap 557, N trap 557 comprises that ideally chain injects non-Gauss N trap, it comprises bottom NW1B and top NW1 at least, here bottom NW1B more mixes in the important place than top NW1 in a preferred embodiment, if especially identical N trap is included as structure and electric device in other device made from channel lateral DMOS.For example, can substitute a N trap, if the 2nd N trap has than the higher mean dose of a N trap if wish the 2nd N trap.
The existence of P type body 559 is divided into two districts with drift region 555, district 555A that shrinks below body 559 and the district 555B that is not shunk by P type body floor.As shown in Figure 15 C, injection is used to form N+ source area 560A and contacts 560C with 560B with drain electrode.Another injection is used to form P+ body contact 561A and 561B.Electric current I is followed the vertical-path under the side direction of groove 552 and is passed the drift region 555A of contraction and expand the horizontal guiding path that enters the drift region 555B that is not retracted subsequently, is used for finally being collected by N+ drain electrode contact 560C.Optionally N trap 557 can help to reduce conducting resistance.
Figure 16 A and 16B show the possible structure of lateral trench DMOS 580, and it comprises non-conformal, dark N type drift region 582.Figure 16 A shows the design of grid center with sectional view, and it comprises trench-gate polysilicon 585 and the gate oxide 584 that is centered on by N+ source electrode 587B, P+ body contact 586B, chain injection P type body 583, ND district 582, N+ drain electrode contact 587A, substrate contact 586A, ILD 590, barrier metal 588 and interconnecting metal 589.
Except the bottom of trench-gate, the drift region 582 that whole grid and drain electrode structure are injected into vertically is included in interior and is laterally surrounded, and injects drift region 582 and comprises not 582A of portion that is shunk by the P body and the 582B of portion that is shunk by P type body 583.The 582B of portion that is retracted that prolongs the Shen from the edge of grid polycrystalline silicon 585 to the edge in P tagma 583 has length L
J(indication JFET class district), and the edge of P body 583 extremely optionally is defined as drift length L in the edge of N trap drain electrode 591
D1These drift region length L extend
JAnd L
D1Arbitrary or two BV that increase LTDMOS, but also increased its conducting resistance.
The outside petiolarea of LTDMOS 580 between drain electrode 591 of N trap and the P substrate 581 comprises length L
D2ND district 582A extension with contacted the length L that 586A retrains by the P+ substrate
D3Substrate zone.The outer end section length does not resemble L
D1The same device electric conductivity that influences of mode of doping and length.Entire device is formed at and need not extension in the P length 581.
Figure 16 B shows the vertical view of LTDMOS 580, LTDMOS580 comprises the P+ substrate ring 602A that surrounds ND district 601, optionally N well region 604A and 604B, N+ drain and contact 605A and 605B, P tagma 603, N+ source area 605C and 605D in abutting connection with P+ body contact zone 602B, groove 609 contacts by contact window 607 with groove polysilicon 608, and wherein polysilicon is positioned on the silicon face top of groove 609 outsides.Source electrode contact 606 is shown as the butt joint that straddles N+ source area 605C and P+ body contact zone 602B and contacts.As an alternative, contact can separate source electrode with body.
Drift length L
D1, L
D2And L
D3For defining doped region is identical.The part that can be repeated with the bigger device of formation is described by the portion that is defined as " unit cell ", as long as ND district 601 and P+ substrate ring 602A also are expanded so that hold bigger device.The drain electrode of N trap also can be surrounded tagma 603 fully.
Figure 17 A and 17B show several drain electrodes center variant of LTDMOS, on the structure similar in appearance to the device of Figure 16 A, except drain electrode by groove around rather than opposite.
Figure 17 A shows drain electrode center LTDMOS 620, and it comprises by P+ body contact zone 627B and 627C, chain and injects N well depth drain region 623 and the N+ drain contact region 628E that P type body 626A, 626B, 626C and 626D, trench-gate polysilicon 625 and gate oxide 624, N+ source area 628A, 628B, 628C, 628D, ILD 631, barrier metal 629, interconnecting metal 630 are centered on.Entire device is formed in non-conformal ND district 622 and the P type substrate 621, need not extension.
Aspect electric, N trap 623 forms the drift region of device, wherein drift length L
D1Edge from the edge of P body 626C to N+ drain contact region 628E is defined.Prolong this drift region and can increase puncture to a certain degree, adopt the doping of higher N trap 623 can cause only having minimum puncture to increase, although the approaching linear increase of transistor drain resistance.The substrate contact injection of device and contact ring and outside petiolarea are not illustrated, but can use similar in appearance to realizing to outer body by extending drift region 622 with the LTDMOS 580 similar designs shown in Figure 16 B at Figure 16 A.
Figure 17 B shows the LTDMOS 640 with conformal drift region.N+ drain contact region 648E, P+ body contact zone 647A and 647B that this device comprises optionally dark drain region 643, centered on by field oxide layer 652, chain injects P type body 646A, 646B, 646C and 646D, trench-gate polysilicon 645 and gate oxide 644, N+ source area 648A, 648B, 648C and 648D, ILD 651, barrier metal 649 and interconnecting metal 650.Entire device is formed in conformal ND district 642A and 642B and the P type substrate 641, need not extension.
Aspect electric, district 642A and 642B form the drift region of device, drift length L here
D1Defined at the edge of drain region 643 extremely deeply from the edge of P body 646C.This can with the same length of the field oxide layer 652 that goes out as shown, but this does not need.The drift region 642A of contraction that extends to the edge of P tagma 646B from gate edge has length L
J(indication JFET class district).Prolong these drift region length L
JAnd L
D1Arbitrary or two BV that can increase LTDMOS still also will increase its conducting resistance.But the substrate contact injection of device and the outside petiolarea of contact ring and device are not illustrated can realize to outside tagma by the design extension ND district 642 of use similar in appearance to the device of Figure 16.
Figure 17 C shows LTDMOS 660, LTDMOS 660 comprises that dark drain region 663 contacts 668C, P+ body contact 667, chain injection P type body 666A and 666B, trench-gate polysilicon 665 and gate oxide 664, N+ source area 668A and 668B, ILD 671, barrier metal 669 and interconnecting metal 670 with the N+ drain electrode that is centered on by drift region 662A.Entire device is formed in high energy injection region 662 and the P type substrate 661, need not extension.Go out as shown, the center of N+ drain electrode 668C is the center line of symmetrical device.
Aspect electric, ND district 662 forms the drift region of device, drift length L here
D1Edge from the edge of optional N trap 663 to P body 666B is defined.Different with the LTDMOS 640 of Figure 17 B, drift region 662 is not injected into by field oxide layer among the LTDMOS 660, so the degree of depth of the gained of drift region 662 is consistent along its whole length substantially.Increase L
D1The BV of LTDMOS 660 can be increased, but also its conducting resistance will be increased.The substrate contact injection of device and contact ring and outside petiolarea are not illustrated, but can be by using similar in appearance to realizing to outside tagma in the design extension drift region 662 shown in Figure 16 A and Figure 16 B.
Figure 17 D shows and comprises that optionally dark drain region 683 contact 688C with the N+ drain electrode that is centered on by conformal drift region 682, the non-contraction flow region 682C below the part that conformal drift region 682 comprises the non-contraction flow region 682A below contraction flow region 682B, the field oxide layer 691 and the oxide skin(coating) 691 of being absent from the scene is following.LTDMOS 680 also comprises P+ body contact 687, and chain injects P type body 686A and 686B, trench-gate polysilicon 685 and gate oxide 684, N+ source area 688A and 688B, ILD 692, barrier metal 689 and interconnecting metal 690.Entire device is formed in conformal injection drift region 682A, 682B, 682C and the P type substrate 681, need not extension.Go out as shown, the center of N+ drain electrode 688C is the center line of symmetrical device.
Aspect electric, drift region 682A forms the drift region of device, drift length L here
D1Edge from the edge of N+ drain electrode contact 688C or optionally dark drain electrode 683 to P body 686B is defined.As shown, the length of field oxide layer 691 can with L
D1Identical, perhaps these length can be significantly different.Increase L
D1Puncture can be increased, but also its conducting resistance will be increased.But the substrate contact injection of device and the outside petiolarea of contact ring and device are not illustrated can be by using similar in appearance to realizing to outside tagma at the design extension drift region of the LTDMOS 580 shown in Figure 16 A and Figure 16 B 682A.
Comprise the N+ drain electrode contact 708E that is centered on by N trap 703 at the LTDMOS 700 shown in Figure 17 E, P+ body contact 707A and 707B, chain inject P type tagma 706A, 706B, 706C and 706D, trench-gate polysilicon 705 and gate oxide 704, N+ source electrode 706A, 706B, 706C and 706D, ILD 711, barrier metal 709 and metal interconnected 710.Entire device is formed at high energy and injects in drift region 702 and the P type substrate 701, need not extension.As shown, the center of N+ drain electrode contact 708E is the center line of symmetrical device.
Aspect electric, the contraction flow region in N trap 703 and ND district 702 forms the drift region of device, drift length L here
D1Edge from the edge of N+ drain electrode contact 708E to P body 706B is defined.The contraction flow region in ND district 702 that extends to the edge of N trap 703 from the edge of grid polycrystalline silicon 705 has length L
JProlong these drift lengths L
JAnd L
D1Arbitrary or both can increase the BV of LTDMOS, but also increase its conducting resistance.Reduce L
D1And/or L
JCan cause that N trap 703 and channel region disturb.
The substrate contact injection of device and contact ring and outside petiolarea are not illustrated, but can be by using similar in appearance to realizing to outside tagma in the design extension drift region 702 of the LTDMOS 580 shown in Figure 16 A and Figure 16 B.
Figure 17 F shows has the N+ drain electrode contact 728E that is centered on by drift region 722, and drift region 722 comprises not by the 722A of portion of P body 726B contraction with by the 722B of portion of P type body 726B contraction.Device also comprises P+ body contact 727B and 727C, and chain injects P type tagma 726A, 726B, 726C and 726D, trench-gate polysilicon 725 and gate oxide 724, N+ source area 728A, 728B, 728C and 728D, ILD 731, barrier metal 729 and interconnecting metal 730.With different at the LTDMOS 700 shown in Figure 17 E, LTDMOS 720 does not comprise the drain electrode of N well depth.Entire device is formed in the P type substrate 721, need not extension.As shown, the center of N+ drain electrode contact 728E is the center line of symmetrical device.
Aspect electric, the drift region of device comprises having the length L that defines to the edge of P body 726B from the edge of N+728E
D1First and the second portion L that defines of the edge from gate edge to P body 726B
JProlong these drift lengths L
JAnd L
D1Arbitrary or both can increase the BV of LTDMOS, but also will increase its conducting resistance.But the substrate contact injection of device and contact ring and outside petiolarea are not illustrated can realize to outside tagma by the design extension ND district 722 of use similar in appearance to the device of Figure 16.
Figure 18 A-18C shows the structure of LTDMOS 760, and LTDMOS 760 comprises the ND district 762 with field oxide layer 771 conformal formation, and it preferably forms by LOCOS technology.As shown, in the sectional view of Figure 18 A, LTDMOS 760 has the design of grid center, and it comprises that trench-gate polysilicon 765, gate oxide 764, N+ source electrode 768B, P+ body contact 767A, chain inject P type body 766, optional N well depth drain region 763, N+ drain electrode contact 768A, substrate contact 767B, ILD772, barrier metal 769 and interconnecting metal 770.
Except the bottom of trench-gate, whole grid is injected into drain electrode structure that the district is vertical to be included in and laterally to be enclosed in the ND district 762, and ND district 762 comprises not the 762A of portion, the 762C that are shunk by P body 766 and 762D and the 762B of portion that is shunk by P type body 766.The contraction flow region that extends to the edge of P type body 766 from gate edge has length L
J(indication JFET class district), and the edge of P body 766 to the edge of N+ drain electrode 768A or optionally dark N trap drain electrode 763 is defined as drift length L
D1ND district 762 is conformal in field oxide layer 771, thereby forms with the more shallow degree of depth and lower electric charge among the district 762C below field oxide layer 711, and forms with the darker degree of depth in drain region 762A and body and gate regions 762B.Prolong L
JAnd L
D1The BV that increases LTDMOS 760 still also increases its conducting resistance.
Outside petiolarea between drain electrode and the P substrate 761 comprises length L
D2Drift region 762D extension with contacted the length L that 767B retrains by the P+ substrate
D3Substrate zone.Outer end section length and doping influence the BV of LTDMOS 760, but do not influence its conductive characteristic.Entire device is formed in the substrate 761, need not extension.
Figure 18 B shows the vertical view of LTDMOS 780, LTDMOS 780 comprises P+ substrate contact 767B, N well region 763, N+ drain electrode contact 768A, the P tagma 766 with the form of the ring that surrounds ND district 762, N+ source area 768B is in abutting connection with P+ body contact 767A, groove 791 contacts by contact window 789 with groove polysilicon 765, and polysilicon is positioned on the top of silicon face in groove 791 outsides here.Source electrode contact 787 is illustrated contact N+ source area 768B, because P+ body contact 767A is narrow along the side that is touched.This design has reduced the length L of width with the contraction flow region 762B of the drift region of correspondence in P tagma 766
JContact 788 contacts that P+ body contact 767A is separated in the end of each finger (finger).As an alternative, source electrode can periodically be interrupted along the grid finger, so that promote additional P+ contact zone.
For defining doped region, drift length L
D1, L
D2And L
D3Be identical.The part description that is defined as " unit cell " can be repeated so that form the part of bigger device, as long as ND district 762 contacts 767B with the P+ substrate and also is expanded, so that hold bigger device.ND district 762 is enclosure body 766 fully also.
In alternate embodiment, P+ and N+ district can be changed along the width of grid, with the contact of supporting to substitute.This scheme is illustrated in Figure 18 C, here with alternate cycle, and the wide portions of source electrode contact 808 contact N+ source area 768B, and the wide portions of body contact 807 contact P+ body contact 767A.Total is comprised in the horizontal footmark of P body 766.This design has reduced the length L of correspondence of the contraction flow region of the width of P body 766 and drift region
J
The residue of this alternate embodiment comprises P+ substrate contact 767B, once more with the form of the ring that surrounds ND district 762, N trap 763, N+ drain electrode contact 768A, by the groove 811 and the groove polysilicon 765 of contact window 809 contacts, polysilicon is positioned on the top of the silicon face outside the groove 811 here.
The lateral DMOS of isolating
Isolating the N channel laterally DMOS that does not have extension requires to use high energy to inject dark N type (DN) layer.The DN layer can be considered to for the substituting of traditional epitaxial cover layer, and it strides across the interface between epitaxial loayer and the following substrate usually, although the DN layer has the characteristic of the uniqueness that itself and its high temperature pioneer is distinguished, especially its formation does not require high-temperature technology.
Figure 19 A to 19C shows and use the DN layer that injects in the manufacturing of the lateral DMOS 840 of isolating, and being injected with profile field oxide layer 844 with preferred use LOCOS process sequence formation is beginning.DN injects and to use photoresist 845 and other suitable mask by mask optionally subsequently, and DN separator 842 is by one or more N type dopants, preferred phosphorus, and the high energy that enters P type substrate 841 injects and forms, and distinguishes 843 to form the bag of isolating.DN layer 842 has the more shallow junction depth below the field oxide layer 844, and the full degree of depth of formation below its active transistor district is to the progressive transition of its degree of depth below the LOCOS oxide.In a preferred embodiment, the sidewall in isolation pocket district self-forming below LOCOS beak transition region.
Shown in Figure 19 B, P type trap 847 injects by the ion that passes photoresist mask 846 and is introduced into the active area that is defined.In resulting devices, but this P trap will play the body of lateral DMOS form prior to grid because of it, so it is not self-aligned to transistorized grid.And have its peak concentration near the surface and to reduce the conventional diffusion trap of concentration monotonously different along with degree of depth increase, P type trap 247 forms by the energetic ion injection of P type dopant, and preferably injects formation by a series of boron doped chain that comprises dosage and energy changing.Chain injects, though it can comprise any amount of injection, in the drawings by two district diagram-superficial layer PW1 and the surperficial PW1B of lower floor, it passes ion injection of single mask and forms and do not use extension.In a preferred embodiment than the doping content height of the doping content specific surface trap of deep layer.P trap 847 can comprise that the P trap that is used for integrated other nmos pass transistor or it can comprise special-purpose the injection.Have the 2nd P trap with the different doping of a P trap, for example PW2 and PW2B, the 2nd P trap, can substitute a P trap.
Dark N type drift (ND) district 849 is by photoresist 848 mask and be infused in described district in the bag district 843 of isolation with high energy optionally in Figure 19 C.If inject by LOCOS oxide 844, then this ND district 849 is conformal in the field oxide distribution, forms " conformal " drift.As an alternative, ND district 849 can only form in active area.In additional embodiments of the present invention, drift can comprise that the shallow N that forms after the polysilicon gate injects, and it is described to extend drain D MOS device as the front in conjunction with non-isolation.Gate oxide, polysilicon gate, N+ source electrode, N+ drain electrode, P trap contact P+ inject and the interconnection (not shown) is added subsequently so that finish the device manufacturing.The N trap that adds also can be used as dark drain electrode or finish the sidewall isolation in P type bag district as required.
Figure 20 shows the symmetric transverse DMOS 860 with the isolation with conformal dark ND district 864 that can use above-mentioned technological process formation.The device that goes out as shown uses N trap 878 to isolate as dark drain electrode contact and as the sidewall than deep 862B of separator 862 at the bottom of the DN in the overlapping active area, and below the oxide skin(coating) 873 that is absent from the scene.The body of the DMOS 860 that isolates comprises as above-mentioned chain and injects P trap 865, is formed in the P type bag district 863 of isolation, be positioned at separator 862 at the bottom of the DN below the oxide skin(coating) 873 that is absent from the scene than on 862 tops, deep.At the bottom of the conformal ND district 864 overlapping DN separator 862 than superficial part 862C, it has more shallow junction depth in the part below field oxide layer 873.
The light doping section 866 that the P+ district 868A that the DMOS 860 of Figure 20 also comprises gate oxide 870, polysilicon gate 871, gate silicide 872, contact P trap and the P+ district 868B, the N+ source area 867A that contact substrate and 867B, N+ drain region 867C and sidewall spacer oxide 869 are following.Metal 875 with barrier metal 874 is by ILD 879 contact devices.
The device that goes out as shown is symmetrical, has the line of symmetry at the center of P+ district 868A.Drift length L
D1, the length of LOCOS oxide 873, the puncture of the knot that influence is isolated, i.e. DMOS drain electrode punctures body, and also influences the conducting resistance of device.But increasing drift length is restricted to by the set maximum voltage of puncture between the part 862A of P trap 865 and DN layer 862 to increase avalanche breakdown.Drift length L
D3, be defined as from the space of N+ drain region 867C to P+ substrate contact 868B, determine of the puncture of the device of isolation to peripheral substrate 861.
Figure 21 shows does not have the isolation of field oxide layer lateral DMOS 880 above the drift region.Chain injects N trap 883 and forms the drift region and play the sidewall isolation, overlaps on the DN separator 882., entire device do not have the existence of field oxide because making in active area, so as in the previous example, device does not use any conformal knot.
The body of the DMOS 880 that isolates comprises the P trap 884 that chain injects, and it is formed at as mentioned above isolates in the P type bag district 885.The light dope N district 886 that the P+ district 888A that device also comprises gate oxide 890, polysilicon gate 891, gate silicide 892, contact P trap 884 and the P+ district 888B, the N+ source area 887A that contact substrate 881 and 887B, N+ drain region 887C and sidewall spacer oxide 889 are following.Metal 895 with barrier metal 894 is by ILD 893 contact devices.
As directed DMOS 880 is symmetrical, has the center line at the center of P+ district 888A.Drift length L
D1, both the space between N+ drain region 887C and the grid 891 influenced the puncture of the knot of isolating, i.e. and DMOS drain electrode punctures body, and also influences the conducting resistance of device.But, increase drift length and be restricted to by the set maximum voltage of puncture between P trap 884 and the DN layer 882 to increase avalanche breakdown.Drift length L
D3, be defined as from the space of N trap 883 to P+ substrates contact 888B, determine of the puncture of the device of isolation to peripheral substrate 881.
Figure 22 shows the isolation lateral DMOS 900 that uses shallow N type district 909A and 909B to form the drift region.Sidewall isolates use N trap 903A and 903B forms, and overlaps on the DN layer 902.Because making, entire device do not have field oxide in active area, so device does not use by any conformal knot that existence produced in the discontinuous field oxide layer of semiconductor surface.
The body of the DMOS that isolates comprises the P trap 904 that chain injects, and it is formed at as mentioned above isolates P type bag district 905.The light dope N district 906 that the P+ district 908A that device also comprises gate oxide 911, polysilicon gate 912, gate silicide 913, contact P trap 904 and the P+ district 908B that contacts substrate 901, N+ source area 907A, N+ drain region 907C and sidewall spacer oxide 910 are following.Metal 916 with barrier metal 915 is by ILD 914 contact devices.
As directed device 900 is not symmetrical, but comprises length L
D1Grid to drain-drift region with equal L
D2And L
D4The space of P trap 904 to the N trap 903A of sum.Drift length L
D1, both the space between N trap 903B and the grid 911 influenced the puncture of isolation junction, i.e. and DMOS drain electrode punctures body, and also influences break-over of device resistance.But, increase drift length and be restricted to by the set maximum voltage of puncture between P trap 904 and the DN layer 902 to increase avalanche breakdown.Drift length L
D2, the length of N drift region 909B, and the Space L between P trap 904 and the N drift region 909B
D4, only but influence punctures does not influence the transistor conductive characteristic.Drift length L
D3, be defined as the length of N drift region 909C and L
D5, the puncture of the device of isolation to peripheral substrate 901 determined in the space of contact 908B from N drift region 909C to substrate.
JFET and depletion type MOS device
Can by the another kind of transistor of technology manufacturing of the present invention normally (normally-on) and depletion mode fet.With (promptly work as V in its gate bias in source electrode
GS=0 o'clock) not conducting of situation enhancement mode or normally close the transistor difference, even normally on transistor also conducts significantly drain current greater than leakage current, i.e. I for zero gate driving
DSS＞0.Depletion device is useful in start-up circuit or when implementing the current stabilization source electrode, especially for the high pressure input power supply bias current of switch power-supplying circuit.In case realize starting and the switching rectifier self-powered, then normally on transistor can be closed so that save energy and improve efficient.
The normally on transistor of making in this technology framework comprises N channel depletion type MOS field-effect transistor (or MOSFET) and N channel junction field-effect transistor (or JFET).N raceway groove normally device exhibits negative threshold value (V
TN＜0) and require in addition bigger negative-grid to source-biased to block drain current or to reduce the size of drain current.Apply the postivie grid current potential and can in restriction, increase drain current.
The grid of depletion-type mos transistor reduces channel current by the channel material that exhausts free carrier, uses electrostatic control with the formation depletion region, so term " field-effect transistor ".Suppose that grid can exhaust channel region fully, then the channel current of device can be suppressed or " pinch off " fully.But if depletion region does not enough come to exhaust fully raceway groove deeply, device will always conduct some electric currents, this be a kind of in power circuit is used undesirable characteristic usually.In stable state, the depth capacity of depletion region is limited by the formation of surface inversion layer.Increasing gate bias does not increase the degree of depth of depletion region to this voltage.
Because MOS transistor has the grid of insulation, improve so its grid can be biased or suppress drain current.For or the gate bias of plus or minus, the maximum guard grating pole tension of MOS depletion mode transistor is subject to the gate oxide voltage that breaks, derate is to about 4MV/cm for the reliability purpose.Although grid can be biased to arbitrary polarity and the non-conducting electric current, gather but not exhaust channel carrier by offset gate and strengthen channel conduction and showed improvement progressive on conductivity and thereby limited benefit arranged.
Compare with depletion-type mos transistor, the PN junction that JFET has used the counter-rotating biasing as grid so that the electrostatic induction depletion region.Similar with mos gate utmost point device, the grid of counter-rotating biasing to body (raceway groove) thus the charge carrier that has exhausted raceway groove suppresses leakage current.Suppose that depletion region can exhaust channel region fully, then the channel current of device can be suppressed or " pinch off " fully.But if depletion region does not enough come to exhaust fully raceway groove deeply, device will always conduct some electric currents, this be a kind of in power circuit is used undesirable characteristic usually.
The maximum gate voltage that suppresses drain current or close JFET is punctured BV by its drain electrode to drain junctions
DGOr grid is to source junction puncture voltage BV
GSLimit.On the contrary, the maximum voltage that strengthens conduction is subjected to the restriction of the forward bias of JFET grid, is 0.6V for silicon PN junction grid promptly.Thereby gather but not the enhancing conduction that exhausts channel carrier is progressive by offset gate, and limited benefit is arranged, especially consider the possible scope that is restricted in strengthening grid.
Depletion type or JFET device is integrated impossible usually in traditional integrated circuit technology, especially under high pressure working.Its manufacturing is usually directed to high-temperature technology and diffusion, and the poorly controlled of MOS threshold value or JFET pinch-off voltage is provided.But device of the present invention does not rely on high-temperature technology and thereby provides outstanding pinch off control and closed condition to leak ability.
Figure 23 shows the high pressure JFET 920 with ND district 922, and it uses low temperature process manufacturing of the present disclosure and preferably use one or more high energy to inject and forms.In this device, N+ district 924A forms the JFET source electrode, N+ district 924B and optionally N trap 923 formation JFET drain electrodes, and P+ district 925B forms the JFET grid via the PN junction that forms with ND district 922.The part in the ND district 922 of shrinking below P+ district 92B plays the JFET raceway groove, and extends to the part formation length L in the ND district 922 of N+ district 924B or optional N trap 923 from P+ district 925B
D1The high pressure drift region.Some grooves shrink from the PN junction appearance that forms between ID district 922 and the P type substrate 921, but this back grid effect is significantly less than the influence of P+ gate regions 925B upper offset.By comprising optional P body or P basic unit 926 as part JFET grid, pinch off can be further adjusted.Grid, source electrode and drain electrode extend through ILD 929 and contact with barrier metal 927 with interconnecting metal 928.
The source voltage of JFET 920 can be floated is the current potential on the substrate, for example as the high-pressure side device, by separating P+ substrate contact region 925A and N+ source area 924A suitably.This distance comprises the length L of the part in ND district 922
D2With distance L from ND district 922 to P+ substrate contact region 925A
D3As shown, device is symmetrical for the center at the line of symmetry of drain electrode N+924B.
Figure 24 shows the depletion type NMOS 940 of (LDD) the drift region 942A that has lightly doped drain.Different with traditional enhancement mode NMOS or lateral DMOS, NMOS 940 does not have around source electrode or otherwise the P trap of encirclement device.Low threshold value is set up by the thickness and the grid material 948 of mix lightly doped substrate 941, gate oxide 947.Adopt the appropriate adjustment of these parameters, 0V to the device threshold voltage of-1V be possible.
Drift region 942 is introduced into subsequently, and be self-aligned to grid 948 and field oxide layer 955 around and surround drain electrode 944B, extend laterally to grid 948, as having length L
D1 N drift region 942A, and extend laterally to field oxide layer 955, as length L
D2N drift region 942B.In order to reduce the electric field at the edge of the drift region of adjoins gate 948 942A, metal field plate 953 can be alternatively extending above the grid 948 and is extending to outside the grid 948 and enter district above the 942A of drift region.
Adopt low concentration P type substrate 941, the punch-through breakdown of avoiding drifting about between drain electrode 942A and the N+ source electrode 944A requires the grid length of polysilicon gate 948 to surpass minimum dimension.Optional high energy injects dark P type (DP) layer 956 also can be used to avoid break-through.This layer part of grid pole 948 that can overlap as shown, perhaps can be extended more (overlapping part 942A) or still less (not extend to outside 954), depends on doped level and device configuration.According to injection condition, the track that DP mixes can extend the VT that goes up the channel region to grid 948 and influence depletion device.
Figure 25 shows the depletion type NMOS960 with ND district 962 of injecting before grid forms.Different with traditional enhancement mode NMOS or lateral DMOS, NMOS 960 does not have around source electrode or otherwise the P trap of encirclement device.Low threshold value is set up by the thickness and the grid material 969 of doping light dope substrate 961, gate oxide 968.Employing is for the appropriate adjustment of these parameters, 0V to the device threshold voltage of-1V be possible.
Depletion type NMOS 960 also comprises N+ source electrode 964A, N+ drain region 964B, optionally dark drain electrode N trap 963, can comprise first or the gate oxide 968 of second grid oxide, grid 969, optionally gate silicide 970, sidewall spacer 967, N source electrode extend 966, P+ substrate contact 965, field oxide layer 970, ILD 971, metal interconnected 973 and barrier metal 972.
The dark ND district 962 of injecting formerly is introduced into, and thereby is not self-aligned to grid 969.Field oxide layer 970 centers on and encirclement drain electrode 964B.ND district 962 is with L
D1Length extend laterally to grid 969, and with length L
D2Extend laterally to field oxide layer 970.In order to reduce the electric field at the edge of the drift region 962 of adjoins gate 969, metal field plate 974 can extend above the grid 964 and extend to outside the grid 964 and enter district above the ND district 962.Adopt low concentration P type substrate 961, avoid the punch-through breakdown between ND district 962 and the N+ source area 964A to require the length of polysilicon gate 969 to equal or exceed minimum dimension.Dark P layer similar in appearance to above-mentioned DP layer 956 also can be included among the NMOS 960.
Figure 26 shows the depletion type NMOS 960 with dark conformal N type drift region 982 of injecting before grid forms.Low threshold value is set by light dope substrate 981 and thin grid 989.As mentioned above, DMOS 980 do not have around source electrode or otherwise surround the P trap of device, so 0V to the device threshold of-1V be possible.
The dark conformal ND district 982 of injecting formerly is introduced into, and thereby be not self-aligned to grid 969, around and surround the 984B that drains, to extend laterally to effective grid 989, as having length L
D1Drift region 982A, length L
D1Length corresponding to field oxide layer 991.The part 982D in ND district 982 not in the face of on the side of grid below field oxide the horizontal expansion length L
D2The degree of depth in the conformal ND district 982 below field oxide layer 991, as shown, more shallow than the 982B portion and the 982C portion that are positioned at the ND district 982 below drain electrode 984B and the grid 989 by the 982A of portion and the 982D in ND district 982.Adopt low concentration P type substrate 981, avoid the deep 982C in ND district 982 and the punch-through breakdown between the N+ source area 984A to require the grid length of polysilicon gate 989 to equal or exceed minimum dimension.DP layer similar in appearance to above-mentioned DP layer 956 also can be included among the NMOS 980.
Figure 27 A-27C shows at Figure 24 to 26 to shown three depletion type nmos devices, and it is modified to comprise shielding under the P type surface.This shielding is included to reduce the outbreak of NPN parasitic bipolar conduction and suppresses snapback's effect.
As the example similar in appearance to the NMOS 940 of Figure 24, Figure 27 A shows has shallow N lightly doped drain (LDD) and the surface depletion type NMOS 1000 of shielding 1002 down.Low threshold value is provided with by light dope substrate 1001 and thin gate oxide 1007.Different with traditional enhancement mode NMOS or lateral DMOS, NMOS 940 does not have the P trap that extends to outside the source electrode or enter the raceway groove below the grid, but it comprises that really the chain that extends to below the N+ source area 1015A injects P trap 1002A and 1002B below LOCOS field oxide layer 1010.According to the doping content of P substrate 1001 and the thickness of gate oxide 1007, will cause the device threshold of 0V to-1V.
Figure 27 B show at the similar depletion type NMOS 1020 of the NMOS shown in Figure 25, have the dark N type drift 1025 of form injecting prior to grid.But low threshold value is provided with is had under the additional surfaces by light dope substrate 1021 and thin gate oxide 1028 and shields 1022.Different with traditional enhancement mode NMOS or lateral DMOS, depletion type NMOS 1020 does not have and extends to outside the source electrode or enter P trap below the grid, but it comprises that really the chain that extends to below the N+ source area 1023A injects P trap 1022A and 1022B below field oxide layer 1034.According to the doping content of P substrate 1021 and the thickness of gate oxide 1028, will cause the device threshold of 0V to-1V.
NMOS 1020 comprises that also N+ drain electrode 1023B, chain inject dark drain electrode N trap 1024, gate oxide level 1028, grid 1029, gate silicide 1030, sidewall spacer 1027, N source electrode and extend 1026 (artefacts of sidewall spacer manufacturing process), inject even ND district 1025, field oxide layer 1034, ILD 1033, metal interconnected 1032 and barrier metal 1031 deeply.
In another variant of the NMOS 980 of Figure 26, the NMOS 1040 of Figure 27 C shows the depletion type NMOS 1040 with the dark conformal ND district 1044A to 1044C that was injected into before grid forms.The surface down shielding 1042 comprise below the LOCOS field oxide layer 1049 P trap 1042A and below N+ source area 1045A horizontal expansion than deep 1042B.Low threshold value is provided with by doped with P substrate 1041 and thin gate oxide 1046.According to the doping content of P substrate 1041 and the thickness of gate oxide 1046, will cause the device threshold of 0V to-1V.
NMOS 1040 also comprise N+ drain region 1045B, chain inject dark drain electrode N trap 1043, grid 1047, optionally gate silicide 1048, sidewall spacer 1053, N source electrode extend 1054, the dark conformal ND district 1044A to 1044C that injects, field oxide layer 1044, ILD 1050, metal interconnected 1052 and barrier metal 1051.
As another embodiment of the present invention, Figure 28 shows the depletion type NMOS 1060 that isolates fully with shallow LDD that forms under no high-temperature technology or diffusion situation.In this device, separator 1062 is isolated overlapping by annular sidewall at the bottom of the DN, and dark drain electrode comprises that N trap 1063A and 1063B, shallow ND district 1068A are self-aligned to grid 1071 and ND district 1068B is self-aligned to LOCOS field oxide layer 1076.Drain electrode is touched by N+ district 1066B, metal 1074 and barrier metal 1073.
P-N diode and knot petiolarea
Another critical function in the power circuit is the needs of clamping voltage on the MOS of sensitivity circuit, unexpectedly damages thin gate oxide to avoid noise spike and finite duration voltage transient.This can finish by using diode, and it can be benchmark with ground or can " float " in the bucket district that isolates, and have the puncture voltage that is lower than protected circuit whatsoever or element.These voltage clamps are commonly called Zener diode, although actual puncture transmission mechanism is an avalanche process, are not quantum mechanical tunneling.Here use term Zener and voltage clamp interchangeably and do not consider the physical mechanism of junction breakdown.
Because the diode that can obtain in traditional integrated circuit technology uses High temperature diffusion to form, so the high surface concentration forced breakdown of gained is near the surface, the snowslide charge carrier is bred the reliability or the voltage stability that can damage responsive oxide and influence device unfriendly here.On the contrary, diode of the present invention uses and adopts the injection former state dopant profiles that high energy and chain inject and need not High temperature diffusion, and show be buried in less in the body silicon can vitiable subsurface avalanche breakdown.
Figure 29 A-29C shows and can adopt the various Zener diodes of making according to technology of the present invention.For example, Figure 29 A shows the N+ with the connection of ground connection anode and buries clamping diode K1 and K2.Diode K1 uses the P trap as anode; Diode K2 uses P base or P tagma as anode.The negative electrode of diode K1 comprises the N+ district 1083 of autoregistration and LOCOS field oxide layer 1087.The anode of K1 comprises P trap 1084, and it has than the little lateral dimension of N+ negative electrode 1083 and laterally is enclosed in the N+ negative electrode 1083.P trap 1084 is connected to by metal interconnected 1090 and the electrode " A " that forms of barrier metal 1089 by the P+ contact 1082 by the opening in ILD 1088.
And have its peak concentration near the surface and along with the conventional diffusion trap of the increase monotone decreasing small concentration of the degree of depth is different, P trap 1084 forms by the energetic ion injection of boron, and the boron chain injection of preferably injecting by a series of boron that comprise dosage and energy changing forms.Chain injects, though it can comprise any amount of injection, in the drawings by illustrated in two districts-superficial layer PW1 and the surperficial PW1B of lower floor, inject formation and do not use extension by the ion that passes single mask.For example, P trap 1084 can be included in the arbitrary of the first or the 2nd P trap described in the table 1.
In diode K2, the p type anode 1087 of injection is formed at below the N+ negative electrode 1087 and laterally is included in the N+ negative electrode 1087, has negative electrode and connects 1090 and be connected A with anode.The P build injects and can comprise that single high-energy boron is injected or chain injects.For example, P trap 1087 can be included in arbitrary P body or the P base described in the table 1.Typically, the main distinction between P body or P base and the P well region is concrete dopant profiles, and the latter has than the former more heavily doped surperficial lower floor.
Use P base or the P tagma isolation version of burying Zener diode as anode has been shown in Figure 29 B.Diode 1100 comprises and comprising and the p type island region 1103 of isolating diode 1100 and the isolation of P substrate 1101.Separator 1102 was isolated with the sidewall isolation N trap 1105A and the 1105B that have annular and vertically overlap on the DN layer 1102 at the bottom of the p type island region 1103 of floating was injected DN by high energy.N+ negative electrode 1106 extends across surface and formation and the isolation structure of DN layer 1102 and the electrically contacting of N trap 1105A and 1105B between the LOCOS field oxide region 1108, by itself and the contacting of N trap 1105A and 1105B.N+ cathodic region 1106 is touched by ILD 1109 and is electrically connected by metal 1111 and the barrier metal 1110 that is designated K.P body or P base anode 1104 is comprised in the p type island region 1103 of isolation and the P+ districts in the segregate p type island region 1103 contact.This P+ contact zone typically is positioned at the third dimension that extends into the page, so it is not illustrated.Contact for the P type substrate 1101 of non-isolation is promoted that by P+ district 1107A and 1107B it forms ring in a preferred embodiment and limits diode 1100.
In Figure 29 C, illustrated and used the isolation version of burying Zener diode of P well region as anode.Zener diode 1120 is formed in the p type island region 1131 of isolation, and it comprises and isolate Zener diode 1120 and P type substrate 1121.Separator 1122 was isolated with the sidewall isolation N trap 1123A and the 1124B that have annular and vertically overlap on the DN layer 1122 at the bottom of the p type island region 1131 of floating was injected DN by high energy.N+ cathodic region 1125 extends across surface and formation and the isolation structure of DN layer 1122 and the electrically contacting of N trap 1123A and 1123B between the LOCOS field oxide region 1129, by itself and the contacting of N trap 1123A and 1123B.The N+ cathodic region is touched by ILD 1130 and is electrically connected by metal 1128 and barrier metal 1127.P trap anode 1124 is comprised in the p type island region 1131 of isolation and the P+ districts in the segregate p type island region 1131 contact, typically (not shown) in the third dimension.Contact for the part of the P substrate 1121 of non-isolation is promoted that by P+ district 1126A and 1126B it forms ring in a preferred embodiment and limits diode 1120.
And have its peak concentration near the surface and along with the conventional diffusion trap of the increase monotone decreasing small concentration of the degree of depth is different, P trap 1124 forms by the energetic ion injection of boron, and the boron chain injection of preferably injecting by a series of boron that comprise dosage and energy changing forms.Chain injects, though it can comprise any amount of injection, in the drawings by illustrated in two districts-superficial layer PW1 and the surperficial PW1B of lower floor, inject formation and do not use extension by the ion that passes single mask.Darker in a preferred embodiment layer specific surface trap more mixes in the important place.As an alternative, P trap 1124 can have different dopant profiles so that realize different puncture voltages.
The Zener diode of burying of obtainable another isolation in technology of the present disclosure shown in the sectional view 1140 of Figure 29 D comprises that N trap in the island of floating that all is included in substrate isolation is to the parallel combination of the bar of P trap knot.Diode comprises the P trap 1144A and 1144B and a plurality of N trap 1143A, the 1143B and the 1143C that are contacted with 1145C by N+ district 1145A, 1145B of a plurality of isolation that contacted with 1146C by P+ district 1146D, and separator 1142 pushed up at the bottom of all were positioned at high energy injection DN.N trap 1143A and 1143C form the loop configuration of isolating whole Zener and substrate 1141.Device is by LOCOS 1149 and P+ substrate ring 1146A and 1146B qualification.The intercommunicated metal 1148 excessively and the barrier metal 1147 of the bar of each Zener diode are promoted.
And have its peak concentration near the surface and along with the conventional diffusion trap of the increase monotone decreasing small concentration of the degree of depth is different, the one P type trap 1144A and 1144B, inject by energetic ion with a N trap 1143A, 1143B and 1143B and to form, and preferably the chain of a series of injections by comprising dosage and energy changing injects and forms.Chain injects, though it can comprise any amount of injection, in the drawings by illustrated in two districts-superficial layer PW1 and NW1 and surperficial PW1B of lower floor and NW1B.In a preferred embodiment, darker layer NW1B and PW1B specific surface trap concentration are higher, and the puncture that causes Zener appears at the position far below the surface.As an alternative, has the 2nd P trap of different dopant profiles and the 2nd N trap can substitute or a P trap or a N trap or both, so that realize different puncture voltages.
The sectional view 1160 of Figure 29 shows isolates P+ the N base is buried Zener diode, and it comprises and comprises and isolate the p type island region 1163 that described P+ to N base is buried Zener diode and described P type substrate 1161.Separator 1162 was isolated with having annular and vertically overlapping on the DN floor 1162 and by sidewall isolation N trap 1165A and 1165B that N+ district 1168A is contacted with 1168B at the bottom of the p type island region 1163 of floating was injected DN by high energy.P+ anode 1167A extend across the surface and form with the p type island region 1163 of isolating electrically contact and with the electrically contacting of the chain injection P trap 1164 that comprises N base 1166.Puncture is determined by the concentration of burying the interface between P+1167A and the N base 1166.The P+ anode is labeled as A, is electrically connected by ILD 1172 contacts and by metal 1170 and barrier metal 1169.N base negative electrode 1166 is contacted by the N+ in the third dimension (not shown).Contact for the P type substrate 1161 of non-isolation is promoted that by P+ district 1167C and 1167B it forms ring in a preferred embodiment and limits described diode.
And have its peak concentration near the surface and along with the conventional diffusion trap of the increase monotone decreasing small concentration of the degree of depth is different, the one P type trap 1164 forms by the energetic ion injection of boron, and the boron chain injection of preferably injecting by a series of boron that comprise dosage and energy changing forms.Chain injects, though it can comprise any amount of injection, in the drawings by illustrated in two districts-superficial layer PW1 and the surperficial PW1B of lower floor, inject formation and do not use extension by the ion that passes single mask.Darker in a preferred embodiment layer specific surface trap concentration is higher, and the puncture that causes Zener diode appears at the position far below the surface.As an alternative, thus the 2nd P trap with different dopant profiles can substitute a P trap realizes different punctures.
Another P-N diode of the present invention is to be used to float the petiolarea of the P type bag district that the isolates high pressure to the substrate in technology.The purposes at the edge of petiolarea is the electric field at the edge that isolates of shaping N type sidewall, and typically sidewall comprises the N trap that overlaps on separator at the bottom of the DN that high energy injects here.
In the embodiment shown in Figure 30 A, segregate P type bag district 1204 is isolated by separator at the bottom of the DN 1202 and N trap 1203 and is centered on by P type substrate 1201 and P+ substrate ring 1205A.In this example, petiolarea is included in the metal field plate 1211 and 1212 of ILD 1210 top horizontal expansions.Petiolarea has the length L that is defined as from the distance of P+ substrate ring 1205A to N trap 1203
D3
In the embodiment shown in Figure 30 B, the P type bag district 1224 of isolation is isolated by separator at the bottom of the DN 1222 and N trap 1223 and is centered on by P type substrate 1221 and P+ substrate ring 1225A.In this example, petiolarea is included in the polysilicon field plate 1231 and 1232 on LOCOS field oxide layer 1230 tops, and metal field plate 1234 and 1235 horizontal expansions above ILD 1233.In other embodiments, only polysilicon or metal field plate can be used to petiolarea or P+ or N trap side.The length of field plate and its spacing are preferably adjusted so that increase the BV of petiolarea.Petiolarea has the length L that is defined as from the distance of P+ substrate ring 1225A to N trap 1223
D3In this embodiment, N trap 1223 is in 1230 times horizontal expansions of LOCOS field oxide layer, the bottom that causes NW1B is near the surface and form than the NW1 of combination and NW1B is more shallow and more lightly doped junction spreading district, and it can play a part to reduce crowded and thereby improve the BV of this petiolarea near the electric field at the edge of DN layer 1222.
In the embodiment shown in Figure 30 C, the P type bag district 1244 of isolation is isolated by separator at the bottom of the DN 1242 and N trap 1243 and is centered on by P type substrate 1241 and P+ substrate ring 1245A.In this embodiment, petiolarea is included in the metal field plate 1251 and 1252 of ILD 1253 and the 1250 top horizontal expansions of LOCOS field oxide layer.Petiolarea has the length L that is defined as from the distance of P+ substrate ring 1245A to N trap 1243
D3In this embodiment, N trap 1243 does not extend below LOCOS field oxide layer 1250.What also be illustrated is optional polysilicon field plate 1254, the edge of its overlapping N trap 1243 and the part that has the part that is positioned at thin-oxide 1255 tops and extend above LOCOS field oxide layer 1250.Combine with metal field plate 1152, polysilicon field plate 1254 allow field plate and below silicon between the formation of dielectric field plate of 3 different-thickness of as many as.
In the embodiment shown in Figure 30 D, the P type bag district 1264 of isolation is isolated by separator at the bottom of the DN 1262 and N trap 1263 and is centered on by P type substrate 1261 and P+ substrate ring 1265.In this embodiment, petiolarea comprises and is connected to N trap 1263 and development length L below field oxide layer 1270
D3And with P+ substrate ring 1265A L spaced apart
D4Dark ND district 1266.Petiolarea can also be included in the metal field plate 1271 and 1272 that extend ILD 1270 tops.
In the embodiment shown in Figure 30 E, the P type bag district 1284 of isolation is isolated by separator at the bottom of the DN 1282 and N trap 1283 and is centered on by P type substrate 1281 and P+ substrate ring 1285A.N trap 1283 can extend below LOCOS field oxide layer 1290, as shown, and so that the first junction spreading district that is formed by NW1B to be provided.In alternate embodiment, N trap 1283 can center on N+ district 1287, as shown, but not horizontal expansion below LOCOS field oxide layer 1290.In this embodiment, petiolarea also comprises and is connected to N trap 1283 and extended distance L below LOCOS field oxide layer 1290
D3And with P+ substrate ring 1285A L spaced apart
D4Conformal dark ND district 1286.Petiolarea can also comprise the metal field plate 1291 and 1292 that overlaps on the ILD 1293.
In the embodiment of Figure 30 F, the P type bag district 1304 of isolation is isolated by separator at the bottom of the DN 1302 and N trap 1303 and is centered on by P type substrate 1301 and P+ substrate ring 1305A.In this embodiment, petiolarea comprises conformal dark ND district 1396, and it is included in has length L in the active area
D3AThe 1306A of portion and below LOCOS field oxide layer 1310, have length L
D3BThe 1306B of portion, and be spaced apart distance L with P+ substrate ring 1305A
D4
In the embodiment of Figure 30 G, the P type bag district 1324 of isolation is isolated by separator at the bottom of the DN 1322 and N trap 1323 and is centered on by P type substrate 1321 and P+ substrate ring 1325.In this embodiment, petiolarea comprises and is connected to development length L below N trap 1323 and the ILD on the scene 1330
D3Shallow N-drift region 1326. P+ substrate ring 1325A and 1326 autoregistrations of N drift region and LOCOS field oxide layer 1331 and be spaced apart distance L
D4
In the embodiment of Figure 30 H, the P type bag district 1344 of isolation is isolated by separator at the bottom of the DN 1342 and N trap 1343 and is centered on by P type substrate 1341A and P+ substrate ring 1345A.In this embodiment, substrate 1341A comprises district 1341B, and it has the length L that is defined as from the distance of P+ substrate ring 1345A to N trap 1343 below LOCOS field oxide layer 1350 and ILD 1351
D3 Separator 1342 extends to outside the N trap 1343 to help to reduce surface field to P+ substrate ring 1345A at the bottom of the part DN.The extension of the DN layer 1342 outside the N trap 1343 is not in this example extended below LOCOS, so the degree of depth of DN layer 1342 basically identical in the petiolarea zone.
In the embodiment of Figure 30 I, the bag district 1364 of isolation is isolated by separator at the bottom of the DN 1362 and N trap 1363 and is centered on by P type substrate 1361A and P+ substrate ring 1365A.In this embodiment, substrate 1361A comprises district 1361B, and it has the length L that is defined as from the distance of P+ substrate ring 1365A to N trap 1363 below ILD 1372 and LOCOS field oxide layer 1370
D3 Part DN layer 1362 extends to outside the N trap 1363 so that help to reduce surface field to P+ substrate ring 1365A.Extending in of DN layer 1362 extended below the partial L OCOS field oxide layer 1370 in this example, thus the degree of depth of DN layer 1362 conformal in the petiolarea zone LOCOS field oxide layer 1370.
In the embodiment of Figure 30 J, the P type bag district 1384 of isolation is isolated by separator at the bottom of the DN 1382 and N trap 1383 and is centered on by P type substrate 1381A and P+ substrate ring 1385A.In this embodiment, substrate 1381A comprises the district 1381B below LOCOS field oxide layer 1390 and the ILD 1391, has the length L between P+ substrate ring 1385A and the N-drift region 1386
D4, and the L between LOCOS field oxide layer 1390 and the N trap 1383
D3 P+ substrate ring 1385A and ND district 1386 are self-aligned to LOCOS field oxide 1390.Part DN layer 1382 extends to outside the N trap 1383 to help to reduce surface field to P+ substrate ring 1385A.DN layer 1382 can be shunk back from LOCOS field oxide layer 1390, make the degree of depth basically identical of DN layer 1382, as shown, or it can be alternatively extends below LOCOS field oxide layer 1390 and makes it have the conformal degree of depth in LOCOS field oxide layer 1390, among the embodiment as Figure 30 I.Shallow ND district 1386 is included as the surperficial petiolarea that extends to LOCOS 1390 from N trap 1383.
In the embodiment of Figure 30 K, the P type bag district 1404 of isolation is isolated by separator at the bottom of the DN 1402 and N trap 1403 and is centered on by P type substrate 1401A and P+ substrate ring 1405A.In this embodiment, substrate 1401A comprises the district 1401B below the ILD 1411.Part DN layer 1402 extends to outside the N trap 1403 so that help to reduce surface field to P+ substrate ring 1405A.Shallow P-drift region 1406 also is included as the surperficial petiolarea that extends to N trap 1403 from P+1405A.Petiolarea has the length L between the edge of P+ substrate ring 1405A and P-drift region 1406
D4, and the distance L between the edge of P-drift region 1406 and N trap 1403
D3
In the various features shown in the petiolarea example of Figure 30 A-30K are examples of petiolarea, itself and process compatible of the present invention and can optimize the BV in segregate district.Its within the scope of the invention with combination from the feature of different figure to reach best petiolarea structure for given enforcement.For example, the multilayer polysilicon of Figure 30 B and 30C and metal field plate, the conformal DN layer of Figure 30 I and the N-drift region of Figure 30 I can be all combined, and many other combinations of element of the present disclosure are possible also.Change shown structure also within the scope of the invention according to known process techniques.For example, can above the single metal layer that illustrates, add metal interconnecting layer, and use the extra play of these layers as field plate.Can also substitute the LOCOS field oxide with the alternative field dielectric scheme of the field oxide that for example deposits and/or be recessed into.
Though described specific embodiments of the invention, be to be understood that these embodiment only are schematically, and nonrestrictive.Is obvious according to many interpolations of broad principles of the present invention or alternative embodiment for those skilled in the art.
Claims (91)
1. technology of in Semiconductor substrate, making lateral DMOS transistor, described substrate be first conduction type and do not comprise epitaxial loayer, described technology comprises:
Surface at described substrate forms field oxide layer;
On the surface of described substrate, form and the first spaced mask layer of described field oxide layer;
The dopant of second conduction type is injected described substrate, thereby form the conformal drift region of second conduction type, described drift region have near first in the zone on first limit of described field oxide layer than the deep, approaching second in the zone on second limit of described field oxide layer than the deep and below described field oxide layer than superficial part;
Form second mask layer than the deep with adjacent to first of described drift region above than the zone of the substrate in deep in first and second of described drift region;
Inject the dopant of first conduction type, thereby form the tagma;
Described drift region first than the deep above and form gate dielectric layer above first the zone in described tagma and described drift region than the substrate between the deep; And
Above described gate dielectric layer, form grid.
2. according to the technology of claim 1, also comprise the dopant that injects second conduction type, thereby in described conformal drift region, form described second trap.
3. according to the technology of claim 1, be included in described gate dielectric layer and part field oxide layer top and form grid.
4. lateral dmos device structure that in the Semiconductor substrate of first conduction type, forms, described substrate does not comprise epitaxial loayer, described device comprises:
In the field oxide layer on the surface of described substrate, described field oxide layer has first and second edges;
Below described field oxide region and extend to the conformal drift region of second conduction type beyond the edge of described field oxide region, described drift region comprises superficial part below the described field oxide region, adjacent to first deep at first edge of described field oxide region with adjacent to second deep at second edge of described field oxide region, described deep extends deeper into substrate than described superficial part;
Be positioned at tagma adjacent to first conduction type on the surface of the substrate in described first deep adjacent to described drift region;
The source area of second conduction type that forms adjacent to the surface of the substrate in the described tagma, described source area separates with first deep of described drift region by channel region;
Cover the gate dielectric layer and the grid of described channel region; With
Adjacent to the drain region of second conduction type on the surface of described substrate, at least a portion drain region is arranged in second deep of described drift region.
5. according to the lateral dmos device structure of claim 4, wherein said drift region comprises the doped region of a vertical series that injects with different-energy.
6. according to the lateral dmos device structure of claim 5, the doping content of darker doped region is than the doping content height of more shallow doped region in the described substrate in the wherein said substrate.
7. according to the lateral dmos device structure of claim 4, wherein said tagma comprises the doped region of a vertical series that injects with different-energy.
8. according to the lateral dmos device structure of claim 7, the doping content of darker doped region is than the doping content height of more shallow doped region in the described substrate in the wherein said substrate.
9. according to the lateral dmos device structure of claim 4, wherein said drain region comprises the doped region of a vertical series that injects with different-energy.
10. according to the lateral dmos device structure of claim 9, the doping content of darker doped region is than the doping content height of more shallow doped region in the described substrate in the wherein said substrate.
11. according to the lateral dmos device structure of claim 4, wherein said drain region be formed in the central opening of described field oxide layer and described source electrode and tagma laterally around described field oxide layer.
12. a lateral dmos device structure that forms in the Semiconductor substrate of first conduction type, described substrate does not comprise epitaxial loayer, and described device comprises:
The drift region of second conduction type, described drift region comprise the doped region of a vertical series that injects with different-energy;
Be positioned at adjacent to the surface of described substrate and adjacent to the tagma of first conduction type of described drift region;
The source area of second conduction type that in described tagma, forms adjacent to the surface of described substrate, described source area is separated with described drift region by channel region;
Cover the gate dielectric layer and the grid of described channel region; With
Be positioned at drain region adjacent to the surface of described substrate and second conduction type that separated with channel region by the described drift region of part.
13. according to the lateral dmos device structure of claim 12, the doping content of darker doped region is than the doping content height of more shallow doped region in the described substrate in the wherein said substrate.
14. according to the lateral dmos device structure of claim 12, the bottom of wherein said drift region knot is smooth.
15. according to the lateral dmos device structure of claim 12, wherein said tagma comprises the doped region of a vertical series that injects with different-energy.
16. according to the lateral dmos device structure of claim 15, in the wherein said tagma in the described substrate doping content of darker doped region than the doping content height of more shallow doped region in the described substrate.
17. a lateral dmos device structure that forms in the Semiconductor substrate of first conduction type, described substrate does not comprise epitaxial loayer, and described device comprises:
The drift region of second conduction type;
Be positioned at adjacent to the surface of described substrate and adjacent to the tagma of first conduction type of described drift region;
The source area of second conduction type that in described tagma, forms adjacent to the surface of described substrate, described source area is separated with described drift region by channel region;
Cover the gate dielectric layer and the grid of described channel region;
Be positioned at drain region adjacent to second conduction type on the surface of described drift region and described substrate;
Be positioned at the dark district of first conduction type below the described drain region, described dark district has the doping content higher than the doping content of described substrate.
18. according to the lateral dmos device structure of claim 17, the dark district of wherein said first conduction type comprises the doped region of a vertical series that injects with different-energy.
19. according to the lateral dmos device structure of claim 18, wherein in described dark district in the described substrate doping content of darker doped region than described substrate in the doping content height of more shallow doped region.
20. according to the lateral dmos device structure of claim 17, wherein said tagma comprises the doped region of a vertical series that injects with different-energy.
21. according to the lateral dmos device structure of claim 20, in the wherein said tagma in the described substrate doping content of darker doped region than the doping content height of more shallow doped region in the described substrate.
22. the lateral dmos device structure according to claim 17 also comprises:
In the field oxide layer of described substrate surface, described field oxide layer has first and second edges; And
23. wherein said drift region is conformal and below described field oxide region, described drift region extends to outside the edge of described field oxide region, described drift region comprises superficial part below the described field oxide region, adjacent to first deep at first edge of described field oxide region with adjacent to second deep at second edge of described field oxide region, described deep extends deeper into described substrate than described superficial part.According to the lateral dmos device structure of claim 22, wherein said drift region comprises the doped region of a vertical series that injects with different-energy.
24. according to the lateral dmos device structure of claim 23, the doping content of darker doped region is than the doping content height of more shallow doped region in the described substrate in the wherein said substrate.
25. the drain MOS FET of an extension comprises:
The field oxide layer that forms on the surface of Semiconductor substrate, the opening that in described field oxide layer, forms, described opening is delimited by the edge of field oxide layer;
The trap of first conduction type that forms in described substrate, described trap comprise at least two doped regions that are injected into, and at least one described doped region is cup-shaped and extends below the opening of described oxide skin(coating);
In described trap, form following district:
Be positioned at drain region adjacent to second conduction type of described substrate surface;
Be positioned at the drift region adjacent to second conduction type of described substrate surface and described drain region, the doping content of described drift region is lower than the doping content of described drain region;
Be positioned at the source area adjacent to second conduction type of described substrate surface, described source area is separated with described drift region by channel region.
Gate dielectric layer above described channel region; With
Grid above described gate dielectric layer.
26. according to the drain MOS FET of the extension of claim 25, wherein said cup-shaped doped region has than the high doping content of doping content that is positioned at least one doped region above the described cup-shaped doped region.
27. according to the drain MOS FET of the extension of claim 25, wherein said drain region is laterally centered on by described channel region.
28. according to the drain MOS FET of the extension of claim 25, also comprise the district that is positioned at second conduction type below the described drain region, the district of described second conduction type extends deeper into described substrate than described drift region.
29. according to the drain MOS FET of the extension of claim 25, wherein said substrate is second conduction type.
30. according to the drain MOS FET of the extension of claim 25, wherein said substrate is first conduction type.
31. one kind forms the drain MOS FET that extends in Semiconductor substrate, described substrate does not comprise epitaxial loayer, and described MOSFET comprises:
In the field oxide layer that the surface of described substrate forms, opening is formed in the described field oxide layer;
The conformal trap that forms in described substrate, described trap comprise superficial part and the deep below described field oxide layer split shed below the described field oxide region, and described deep extends deeper into described substrate than described superficial part;
Tagma adjacent to first conduction type on the surface of substrate described in the described trap;
In the described tagma adjacent to the source area of second conduction type on the surface of described substrate;
In the described trap adjacent to the drain region of second conduction type of described substrate surface;
Cover the grid and the gate dielectric layer on the surface of described substrate in the described trap, described grid covers channel region;
Laterally extend to the first drain electrode extension of second conduction type of described channel region from described drain electrode; With
Laterally second drain electrode that extends to second conduction type at the edge the opening of described field oxide from described drain electrode is extended;
The length that wherein said first drain electrode is extended is different with the length that described second drain electrode is extended.
32., comprise also that laterally the source electrode that extends to second conduction type of described channel region from described source area extends according to the drain MOS FET of the extension of claim 31.
33. according to the drain MOS FET of the extension of claim 31, wherein said substrate is that trap second conduction type and described is first conduction type.
34. according to the drain MOS FET of the extension of claim 33, wherein said trap comprises the doped region of a vertical series that injects with different-energy.
35. according to the drain MOS FET of the extension of claim 34, also comprise below the described drain region heavily doped region of first conduction type in the described trap, described heavily doped region has than the high doping content of doping content around the part of the trap of described heavily doped region.
36. according to the drain MOS FET of the extension of claim 31, its described substrate and described trap are first conduction types.
37. according to the drain MOS FET of the extension of claim 36, wherein said trap comprises the doped region of a vertical series that injects with different energy.
38. according to the drain MOS FET of the extension of claim 37, also comprise the heavily doped region of second conduction type in the described trap below the described drain region, described heavily doped region has than the high doping content of doping content around the part of the trap of described heavily doped region.
39. a lateral trench DMOS device that forms in the Semiconductor substrate of first conductivity-type, described substrate portion does not comprise epitaxial loayer, and described device comprises:
In the field oxide layer that the surface of described substrate forms, described field oxide layer has first and second openings;
Be formed at the groove in the described substrate, extend downwards on the surface from described substrate in first opening of described groove in described field oxide layer, and described groove comprises grid and gate dielectric layer;
The tagma of first conduction type that forms adjacent to the groove in first opening in the described field oxide layer;
The source area of second conduction type that in described tagma, forms adjacent to the groove in the surperficial of described substrate and described first opening in described field oxide layer;
Form the drain region of second conduction type in described second opening in described field oxide layer adjacent to the surface of substrate; With
The conformal drift region of second conduction type of the described groove of adjacency, described tagma and described drain region, described drift region comprises first and second deeps below first and second openings described in the described field oxide layer respectively, with described field oxide layer below superficial part, described deep extends deeper into described substrate than described superficial part.
40. according to the lateral trench DMOS device of claim 39, wherein said drain region comprises the doped region of a vertical series that injects with different-energy.
41. lateral trench DMOS device according to claim 40, wherein said drain region be conformal and in described field oxide layer adjacent to horizontal expansion below the part of the field oxide of described second opening, described drain region comprises the superficial part below the part of deep below second opening in the described field oxide layer and described field oxide layer, and described deep extends deeper into described substrate than described superficial part.
42. according to the lateral trench DMOS device of claim 39, wherein said tagma comprises the doped region of a vertical series that injects with different-energy.
43. according to the lateral trench DMOS device of claim 39, wherein said drift region comprise described drain region with described tagma opposite side on petiolarea portion.
44. according to the lateral trench DMOS device of claim 39, wherein each described source area and tagma comprise a plurality of wider parts along described groove, the wider part of described source area and the wider part in described tagma are alternately.
45. a lateral dmos device structure that forms in the Semiconductor substrate of first conduction type, described substrate does not comprise epitaxial loayer, and described device comprises:
The tagma of described first conduction type that forms adjacent to the surface of described substrate;
The source area of second conduction type that in the tagma, forms adjacent to the surface of described substrate;
Cover the grid and the gate dielectric layer of the raceway groove of described substrate;
Adjacent to the surface formation of described substrate and the drain region of horizontal second conduction type that separates with described tagma, described channel region is between described drain region and described source area; With
The separator of second conduction type of horizontal expansion below described tagma, described channel region and described drain region, described separator has the coboundary of the surface underneath of described substrate;
Wherein said tagma comprises the doped region of a vertical series that injects with different-energy.
46. according to the lateral dmos device structure of claim 45, wherein said drain region comprises the doped region of a vertical series that injects with different-energy.
47., also be included in the field oxide layer of the substrate surface in the zone between described drain region and the tagma according to the lateral dmos device structure of claim 45.
48. lateral dmos device structure according to claim 47, wherein said drain region is conformal and horizontal expansion below the part of described field oxide layer, described drain region comprises superficial part and the deep below described oxide skin(coating) not below the part of described field oxide layer, and described deep extends deeper into described substrate than described superficial part.
49. lateral dmos device structure according to claim 47, the conformal drift region that also comprises second conduction type between described drain region and described channel region, described drift region comprises superficial part and the deep below described field oxide layer not below the part of described field oxide layer, and described deep extends deeper into described substrate than described superficial part.
50. lateral dmos device structure according to claim 47, wherein said separator is conformal, described separator comprises first deep below the described drain region, second deep below the described tagma, with described field oxide layer below superficial part, described first and second deeps extend deeper into described substrate than described superficial part.
51. according to the lateral dmos device structure of claim 50, wherein said grid improves above the edge of described field oxide layer.
52. a lateral dmos device structure that forms in the Semiconductor substrate of first conduction type, described substrate portion comprises epitaxial loayer, and described device comprises:
The tagma of first conduction type that forms adjacent to the surface of described substrate, described tagma comprises the doped region of a vertical series that mixes with different-energy;
In the described tagma adjacent to the source area of second conduction type on the surface of described substrate;
Drain region adjacent to second conduction type on the surface of described substrate;
The grid and the gate dielectric layer of described substrate surface top, described grid covers the channel region of described substrate, and described channel region is between described drain region and source area;
In first drift region of extending from described drain region towards the direction of described channel region;
In second drift region that the direction of leaving described channel region is extended from described drain region; With
Below described body and drain region, be embedded in the isolated area of the injection of second conduction type in the described substrate.
53. according to the lateral dmos device structure of claim 52, wherein said drain region comprises the doped region of a vertical series that injects with different-energy.
54. a JFET device that forms in the Semiconductor substrate of first conduction type, described substrate does not comprise epitaxial loayer, and described device comprises:
The trap of second conduction type;
In the described trap adjacent to the drain region of described second conduction type on the surface of described substrate;
Adjacent to the source area of described second conduction type on the surface of described substrate, described source area and described drain region are by spaced in the described trap;
Adjacent to the gate regions of described first conduction type on the surface of described substrate, described gate region is between described source area and drain region in the described trap; With
Channel region between the bottom of the bottom of described gate regions and described trap;
Wherein said trap comprises the doped region of a vertical series that injects with different-energy.
55. according to the JFET device of claim 54, wherein said drain region comprises the doped region of a vertical series that injects with different-energy.
56. according to the JFET device of claim 54, wherein said gate regions comprises the doped region of a vertical series that injects with different-energy.
57. a depletion type MOS FET who forms in the Semiconductor substrate of first conduction type with background doped concentration, described substrate does not comprise epitaxial loayer, and described MOSFET comprises:
Source area adjacent to second conduction type on the surface of described substrate;
Adjacent to the surface of described substrate and the drain region of horizontal and isolated second conduction type of described source area; With
Cover the grid and the gate dielectric layer of the channel region of described substrate, described channel region is between described source electrode and drain region;
The doping content of wherein said channel region is a background doped concentration.
58. according to the depletion type MOS FET of claim 57, also comprise the drift region of described second conduction type, the horizontal expansion of described drift region is so that connect described drain region and described channel region.
59. depletion type MOS FET according to claim 58, also be included in the field oxide layer of described substrate surface, described drift region and described field oxide layer are conformal, and second one of the described drift region below described field oxide layer is not shallow to make first ratio below the described field oxide layer.
60. according to the depletion type MOS FET of claim 59, second described channel region of adjacency of wherein said drift region.
61. according to the depletion type MOS FET of claim 60, wherein said field oxide layer is in abutting connection with described drain region.
62. according to the depletion type MOS FET of claim 61, wherein said drain region comprises the doped region of a vertical series that injects with different-energy.
63. according to the depletion type MOS FET of claim 57, the district is avoided in the injection break-through that also comprises first conduction type, described break-through is avoided distinguishing to have than the high doping content of described background doped concentration and is buried in the substrate below the described source area.
64. according to the depletion type MOS FET of claim 63, wherein said break-through avoids distinguishing the position that extends to below the described channel region.
65. according to the depletion type MOS FET of claim 64, wherein said break-through avoids distinguishing the position that extends to below the described drift region.
66. according to the depletion type MOS FET of claim 63, wherein said break-through avoids distinguishing the position that does not extend to below the described channel region.
67. depletion type MOS FET according to claim 57, the separator that also comprises the injection of described second conduction type, described separator is buried in the substrate below described source electrode, raceway groove and the drain region, and described separator has the coboundary of the surface underneath of described substrate.
68. a diode that forms in the P type semiconductor substrate, described substrate does not comprise epitaxial loayer, and described diode comprises:
N type cathode layer adjacent to the surface of described substrate;
Below the described cathode layer and adjacent to the p type anode district of described cathode layer and
Be buried in the isolated area that the N type in the described substrate injects below the described anode region.
69. according to the diode of claim 68, wherein said anode region comprises the doped region of a vertical series that mixes with different-energy, the vertical dopant profile of described anode region is reversed.
70., also comprise from the surface extension downwards of described substrate and the N type sidewall that merges with described isolated area according to the diode of claim 68.
71. according to the diode of claim 70, wherein said N type sidewall comprises the doped region of a vertical series that mixes with different-energy.
72. the edge petiolarea in the Semiconductor substrate of a conduction type, described substrate does not comprise epitaxial loayer, and described edge petiolarea comprises:
The separator of the injection of second conduction type of in described substrate, burying, described separator has the coboundary of the surface underneath of described substrate; With
The sidewall trap of described second conduction type that extends downwards from the surface of described substrate and merge with the separator of described injection, described separator and sidewall trap form the isolation pocket district of described substrate together.
73. the edge petiolarea according to claim 72 also comprises:
Be positioned at the outside in described isolation pocket district and laterally and the substrate ring of described first conduction type on the isolated surface adjacent to described substrate of described sidewall trap;
Cover the interlayer dielectric on the surface of described substrate;
By first Metal Contact that first opening in the described interlayer dielectric and described sidewall trap electrically contact, described first Metal Contact is included on the surface of described interlayer dielectric the first field plate portion to the horizontal expansion of described substrate ring; With
With second Metal Contact that described substrate ring electrically contacts, described second Metal Contact is included on the surface of described interlayer dielectric the second field plate portion to the horizontal expansion of described sidewall trap.
74., also comprise adjacent to the surface of described substrate and sidewall trap and in the district of described second conduction type that extends towards the direction of described substrate ring according to the petiolarea of claim 73.
75. according to the petiolarea of claim 73, also be included in the field oxide layer on the surface of the described substrate below the described interlayer dielectric, the described segregate bag district outside of described field oxide layer between described sidewall trap and substrate ring.
76. according to the petiolarea of claim 75, wherein said sidewall trap comprises the doped region of a vertical series that injects with different-energy, the vertical dopant profile of N type sidewall is reversed.
77. according to the petiolarea of claim 76, the horizontal expansion below the part of described field oxide layer of wherein said sidewall trap.
78., also comprise the 3rd conductive field plate between described field oxide layer and the described interlayer dielectric according to the petiolarea of claim 77.
79. petiolarea according to claim 78, also comprise the 4th conductive field plate between described field oxide layer and the described interlayer dielectric, described the 3rd field plate is below the first field plate portion of described first Metal Contact, and described the 4th field plate is below second field plate of described second Metal Contact.
80. according to the petiolarea of claim 79, wherein each third and fourth field plate comprises polysilicon.
81., also comprise adjacent to the surface of described substrate and sidewall trap and in the district of second conduction type that extends towards the direction of described substrate ring according to the petiolarea of claim 77.
82. the petiolarea according to claim 75 also comprises:
Lip-deep second oxide skin(coating) of the described substrate of described sidewall trap top; With
On described second oxide skin(coating) and the 3rd conductive field plate that above the edge of described field oxide layer, improves.
83. according to the petiolarea of claim 73, also comprise the field oxide layer on the surface of the described substrate below the described interlayer dielectric, described field oxide layer is positioned at adjacent to described substrate ring and extends the part of described distance towards described sidewall trap.
84. 3 petiolarea according to Claim 8, comprise also that adjacent to the surface of described substrate and sidewall trap and in the district of second conduction type that extends towards the direction of described substrate ring described district and described field oxide layer are conformal and comprise superficial part and the deep below described field oxide layer not below the described field oxide layer.
85. 3 petiolarea according to Claim 8 also comprises adjacent to the surface of described substrate and extends to the district of described second conduction type of described sidewall trap from described field oxide layer.
86. according to the petiolarea of claim 73, wherein said separator in the direction of described substrate ring from the horizontal expansion of described sidewall trap.
87. 6 petiolarea according to Claim 8 comprises that also the field oxide layer on the surface of the described substrate below the described interlayer dielectric, described field oxide layer are positioned at adjacent to described substrate ring and extend the part of described distance towards described sidewall trap.
88. 7 petiolarea according to Claim 8, the edge of wherein said separator is below the edge of described field oxide layer.
89. 7 petiolarea according to Claim 8, wherein said separator extends below described field oxide layer and is conformal with described field oxide layer, and described separator comprises shallow district and the dark district below described field oxide layer not below the described field oxide layer.
90. 7 petiolarea according to Claim 8 also comprises adjacent to described substrate surface and extends to the district of described second conduction type of described sidewall trap from described field oxide layer.
91. 6 petiolarea according to Claim 8 also comprises the drift region of described first conduction type that extends in the direction of described sidewall trap adjacent to the surface of described substrate ring and described substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/443,745 | 2006-05-31 | ||
| US11/443,745 US7719054B2 (en) | 2006-05-31 | 2006-05-31 | High-voltage lateral DMOS device |
| PCT/US2007/012686 WO2007142937A2 (en) | 2006-05-31 | 2007-05-30 | High-voltage bipolar-cmos-dmos integrated circuit devices and modular methods of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101542697A true CN101542697A (en) | 2009-09-23 |
| CN101542697B CN101542697B (en) | 2012-01-25 |
Family
ID=38789105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007800279592A Expired - Fee Related CN101542697B (en) | 2006-05-31 | 2007-05-30 | Methods of forming the same high-voltage bipolar-CMOS-DMOS integrated circuit devices and its module |
Country Status (7)
| Country | Link |
|---|---|
| US (7) | US7719054B2 (en) |
| EP (1) | EP2044622A4 (en) |
| JP (1) | JP5321840B2 (en) |
| KR (10) | KR101298339B1 (en) |
| CN (1) | CN101542697B (en) |
| TW (1) | TWI374508B (en) |
| WO (1) | WO2007142937A2 (en) |
Cited By (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054785A (en) * | 2010-11-04 | 2011-05-11 | 电子科技大学 | Manufacturing method of high-voltage BCD semiconductor device |
| CN102437187A (en) * | 2010-09-29 | 2012-05-02 | 万国半导体股份有限公司 | Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method |
| CN102487082A (en) * | 2010-12-02 | 2012-06-06 | 上海华虹Nec电子有限公司 | Horizontal-groove metal-oxide semiconductor device |
| CN102612753A (en) * | 2009-11-30 | 2012-07-25 | 松下电器产业株式会社 | Bidirectional switch |
| CN102723304A (en) * | 2012-05-31 | 2012-10-10 | 日银Imp微电子有限公司 | Preparation method of N-trap high-voltage gate driving chip for directly driving power device |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN103208523A (en) * | 2011-08-01 | 2013-07-17 | 成都芯源系统有限公司 | High voltage device and method of manufacturing the same |
| CN103247623A (en) * | 2012-02-03 | 2013-08-14 | 爱思开海力士有限公司 | Semiconductor devices and methods of manufacturing the same |
| CN103367449A (en) * | 2012-04-06 | 2013-10-23 | 三星电子株式会社 | Semiconductor devices including guard ring and related semiconductor systems |
| CN103456732A (en) * | 2012-05-30 | 2013-12-18 | 旺宏电子股份有限公司 | Schottky diode with strengthened breakdown voltage |
| CN103839891A (en) * | 2012-11-26 | 2014-06-04 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103996680A (en) * | 2013-02-20 | 2014-08-20 | 台湾积体电路制造股份有限公司 | High voltage transistor structure and method |
| CN104167360A (en) * | 2013-05-16 | 2014-11-26 | 无锡华润上华半导体有限公司 | Laterally-diffused metal oxide semiconductor device and manufacture method thereof |
| CN104425595A (en) * | 2013-08-21 | 2015-03-18 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacture method thereof |
| CN105280718A (en) * | 2014-07-02 | 2016-01-27 | 台湾积体电路制造股份有限公司 | Junction gate field-effect transistor (jfet), semiconductor device and method of manufacturing |
| CN105428322A (en) * | 2014-09-15 | 2016-03-23 | 英飞凌科技奥地利有限公司 | Iii-v semiconductor material based ac switch |
| CN105720101A (en) * | 2014-12-19 | 2016-06-29 | 联发科技股份有限公司 | Semiconductor device and fabrication method thereof |
| CN103208523B (en) * | 2011-08-01 | 2016-11-30 | 成都芯源系统有限公司 | High voltage device and method of manufacturing the same |
| CN106876464A (en) * | 2016-12-29 | 2017-06-20 | 西安电子科技大学 | A kind of lateral double diffusion metal oxide semiconductor FET |
| CN107017247A (en) * | 2015-12-22 | 2017-08-04 | 万国半导体股份有限公司 | Transient Voltage Suppressor with low breakdown voltage |
| CN107785305A (en) * | 2016-08-31 | 2018-03-09 | 无锡华润上华科技有限公司 | The device of integrated depletion type junction field effect transistor |
| CN108475678A (en) * | 2016-01-21 | 2018-08-31 | 德克萨斯仪器股份有限公司 | It is self-aligned to the drift region injection of the field release oxide with side wall dielectric |
| US10262903B2 (en) | 2017-06-22 | 2019-04-16 | Globalfoundries Inc. | Boundary spacer structure and integration |
| CN109891749A (en) * | 2016-03-22 | 2019-06-14 | 密克罗奇普技术公司 | The high pressure transmission of standard BCD technique/reception switch |
| CN110212900A (en) * | 2019-06-10 | 2019-09-06 | 桂林电子科技大学 | A kind of double trap CMOS complementary switch for eliminating bulk effect and substrate leakage |
| CN110620111A (en) * | 2018-06-20 | 2019-12-27 | 格芯新加坡私人有限公司 | Extended Drain MOSFET (EDMOS) |
| US10658477B2 (en) | 2013-05-13 | 2020-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions |
| CN111279477A (en) * | 2017-12-21 | 2020-06-12 | 德州仪器公司 | High voltage lateral junction diode device |
| CN111430346A (en) * | 2020-03-30 | 2020-07-17 | 电子科技大学 | Power integrated semiconductor device |
| CN111785774A (en) * | 2020-06-15 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | CMOS device in BCD process and manufacturing method thereof |
Families Citing this family (233)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9019670B2 (en) * | 1999-11-10 | 2015-04-28 | Texas Instruments Incorporated | Bi-directional ESD protection circuit |
| US7812403B2 (en) * | 2002-08-14 | 2010-10-12 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuit devices |
| US7667268B2 (en) | 2002-08-14 | 2010-02-23 | Advanced Analogic Technologies, Inc. | Isolated transistor |
| US8089129B2 (en) | 2002-08-14 | 2012-01-03 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
| US7902630B2 (en) * | 2002-08-14 | 2011-03-08 | Advanced Analogic Technologies, Inc. | Isolated bipolar transistor |
| US20080197408A1 (en) * | 2002-08-14 | 2008-08-21 | Advanced Analogic Technologies, Inc. | Isolated quasi-vertical DMOS transistor |
| US7939420B2 (en) | 2002-08-14 | 2011-05-10 | Advanced Analogic Technologies, Inc. | Processes for forming isolation structures for integrated circuit devices |
| US7825488B2 (en) | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
| US7956391B2 (en) | 2002-08-14 | 2011-06-07 | Advanced Analogic Technologies, Inc. | Isolated junction field-effect transistor |
| US7834421B2 (en) * | 2002-08-14 | 2010-11-16 | Advanced Analogic Technologies, Inc. | Isolated diode |
| US8513087B2 (en) | 2002-08-14 | 2013-08-20 | Advanced Analogic Technologies, Incorporated | Processes for forming isolation structures for integrated circuit devices |
| US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
| US7511932B1 (en) * | 2002-11-14 | 2009-03-31 | Altera Corporation | ESD protection structure |
| US8212315B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
| US8212316B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
| US8253196B2 (en) | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
| US8253197B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
| US7230302B2 (en) | 2004-01-29 | 2007-06-12 | Enpirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
| US8253195B2 (en) * | 2004-01-29 | 2012-08-28 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
| US8212317B2 (en) * | 2004-01-29 | 2012-07-03 | Enpirion, Inc. | Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same |
| US7498652B2 (en) * | 2004-04-26 | 2009-03-03 | Texas Instruments Incorporated | Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof |
| WO2007052196A1 (en) * | 2005-11-02 | 2007-05-10 | Nxp B.V. | Method of manufacturing a semiconductor device |
| US7626243B2 (en) * | 2006-08-04 | 2009-12-01 | Advanced Analogic Technologies, Inc. | ESD protection for bipolar-CMOS-DMOS integrated circuit devices |
| JP4337852B2 (en) * | 2006-08-30 | 2009-09-30 | セイコーエプソン株式会社 | ORGANIC ELECTROLUMINESCENT DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE |
| JP4611270B2 (en) * | 2006-09-27 | 2011-01-12 | Ｏｋｉセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
| KR100867977B1 (en) | 2006-10-11 | 2008-11-10 | 한국과학기술원 | Machine to analyze tissue perfusion using concentration of indocyanine green in blood and a method for analysing tissue perfusion using the same |
| US7989890B2 (en) | 2006-10-13 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral power MOSFET with high breakdown voltage and low on-resistance |
| US7476591B2 (en) * | 2006-10-13 | 2009-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral power MOSFET with high breakdown voltage and low on-resistance |
| US7667242B1 (en) * | 2006-10-23 | 2010-02-23 | Northrop Grumman Systems Corporation | Systems and methods for maximizing breakdown voltage in semiconductor devices |
| US7601990B2 (en) * | 2006-10-25 | 2009-10-13 | Delphi Technologies, Inc. | Method and apparatus for electrostatic discharge protection having a stable breakdown voltage and low snapback voltage |
| US8497167B1 (en) * | 2007-01-17 | 2013-07-30 | National Semiconductor Corporation | EDS protection diode with pwell-nwell resurf |
| US7709329B2 (en) * | 2007-02-20 | 2010-05-04 | Texas Instruments Incorporated | High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications |
| US7795681B2 (en) * | 2007-03-28 | 2010-09-14 | Advanced Analogic Technologies, Inc. | Isolated lateral MOSFET in epi-less substrate |
| US7737526B2 (en) * | 2007-03-28 | 2010-06-15 | Advanced Analogic Technologies, Inc. | Isolated trench MOSFET in epi-less semiconductor sustrate |
| US7781834B2 (en) * | 2007-07-03 | 2010-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust ESD LDMOS device |
| US7652329B2 (en) * | 2007-07-13 | 2010-01-26 | Semiconductor Components Industries, Llc | Vertical MOS transistor and method therefor |
| US7719076B2 (en) * | 2007-08-10 | 2010-05-18 | United Microelectronics Corp. | High-voltage MOS transistor device |
| CN100592533C (en) * | 2007-10-15 | 2010-02-24 | 天钰科技股份有限公司 | Transversely diffused metal oxide transistor |
| US20090115018A1 (en) * | 2007-11-01 | 2009-05-07 | Alpha & Omega Semiconductor, Ltd | Transient voltage suppressor manufactured in silicon on oxide (SOI) layer |
| JP4700043B2 (en) * | 2007-11-07 | 2011-06-15 | Ｏｋｉセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
| US7649224B2 (en) * | 2007-12-13 | 2010-01-19 | Sanyo Electric Co., Ltd. | DMOS with high source-drain breakdown voltage, small on- resistance, and high current driving capacity |
| KR100935269B1 (en) * | 2007-12-27 | 2010-01-06 | 주식회사 동부하이텍 | Image Sensor and Methof for Manufacturing Thereof |
| US8664728B2 (en) * | 2008-01-14 | 2014-03-04 | Volterra Semiconductor Corporation | Power transistor with protected channel |
| JP5439725B2 (en) * | 2008-02-20 | 2014-03-12 | サンケン電気株式会社 | Semiconductor switching device |
| SE533026C2 (en) * | 2008-04-04 | 2010-06-08 | Klas-Haakan Eklund | Field effect transistor with isolated gate connected in series with a JFET |
| CN102037548B (en) * | 2008-04-28 | 2014-04-23 | 意法半导体有限公司 | MOSFET with integrated field effect rectifier |
| US8174071B2 (en) * | 2008-05-02 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage LDMOS transistor |
| US20090283843A1 (en) * | 2008-05-13 | 2009-11-19 | Micrel, Inc. | NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness |
| US8389366B2 (en) * | 2008-05-30 | 2013-03-05 | Freescale Semiconductor, Inc. | Resurf semiconductor device charge balancing |
| JP2010010408A (en) * | 2008-06-27 | 2010-01-14 | Sanyo Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| JP4587003B2 (en) * | 2008-07-03 | 2010-11-24 | セイコーエプソン株式会社 | Semiconductor device |
| US7768071B2 (en) * | 2008-07-09 | 2010-08-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stabilizing breakdown voltages by forming tunnels for ultra-high voltage devices |
| US7960786B2 (en) | 2008-07-09 | 2011-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Breakdown voltages of ultra-high voltage devices by forming tunnels |
| JP5353093B2 (en) * | 2008-07-15 | 2013-11-27 | 株式会社デンソー | Manufacturing method of semiconductor device |
| JP5183336B2 (en) * | 2008-07-15 | 2013-04-17 | 富士フイルム株式会社 | Display device |
| US7906810B2 (en) * | 2008-08-06 | 2011-03-15 | United Microelectronics Corp. | LDMOS device for ESD protection circuit |
| US7777282B2 (en) * | 2008-08-13 | 2010-08-17 | Intel Corporation | Self-aligned tunneling pocket in field-effect transistors and processes to form same |
| JP2010066331A (en) * | 2008-09-09 | 2010-03-25 | Fujifilm Corp | Display apparatus |
| US8089095B2 (en) * | 2008-10-15 | 2012-01-03 | Semiconductor Components Industries, Llc | Two terminal multi-channel ESD device and method therefor |
| AT507187B1 (en) | 2008-10-23 | 2010-03-15 | Helmut Dr Buchberger | INHALER |
| US20100102379A1 (en) * | 2008-10-29 | 2010-04-29 | United Microelectronics Corp. | Lateral diffused metal oxide semiconductor device |
| JP2010118556A (en) * | 2008-11-13 | 2010-05-27 | Furukawa Electric Co Ltd:The | Semiconductor device and its manufacturing method |
| JP5172654B2 (en) * | 2008-12-27 | 2013-03-27 | 株式会社東芝 | Semiconductor device |
| US8193559B2 (en) * | 2009-01-27 | 2012-06-05 | Infineon Technologies Austria Ag | Monolithic semiconductor switches and method for manufacturing |
| DE102009006885B4 (en) * | 2009-01-30 | 2011-09-22 | Advanced Micro Devices, Inc. | A method of creating a stepped well implant for asymmetric transistors having small gate electrode pitches and semiconductor devices |
| US8378422B2 (en) * | 2009-02-06 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection device comprising a plurality of highly doped areas within a well |
| US20100213507A1 (en) * | 2009-02-20 | 2010-08-26 | Ching-Chung Ko | Lateral bipolar junction transistor |
| US8674454B2 (en) | 2009-02-20 | 2014-03-18 | Mediatek Inc. | Lateral bipolar junction transistor |
| US9184097B2 (en) * | 2009-03-12 | 2015-11-10 | System General Corporation | Semiconductor devices and formation methods thereof |
| US8232603B2 (en) * | 2009-03-19 | 2012-07-31 | International Business Machines Corporation | Gated diode structure and method including relaxed liner |
| EP2234144B1 (en) * | 2009-03-25 | 2018-08-22 | ABB Schweiz AG | Method for manufacturing a power semiconductor device |
| US20100244152A1 (en) * | 2009-03-27 | 2010-09-30 | Bahl Sandeep R | Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor |
| US7897995B2 (en) * | 2009-04-07 | 2011-03-01 | Mediatek Inc. | Lateral bipolar junction transistor with reduced base resistance |
| CN101521203B (en) * | 2009-04-07 | 2010-08-04 | 电子科技大学 | Semiconductor transverse device and high-voltage device |
| WO2010120704A2 (en) * | 2009-04-13 | 2010-10-21 | Maxpower Semiconductor Inc. | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges |
| US8847307B2 (en) | 2010-04-13 | 2014-09-30 | Maxpower Semiconductor, Inc. | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges |
| CN103219382B (en) | 2009-04-30 | 2015-07-22 | 松下电器产业株式会社 | Semiconductor element, semiconductor device, and power converter |
| TWI471977B (en) * | 2009-05-15 | 2015-02-01 | Xintec Inc | Power mosfet package |
| US8207580B2 (en) * | 2009-05-29 | 2012-06-26 | Power Integrations, Inc. | Power integrated circuit device with incorporated sense FET |
| WO2011021361A1 (en) * | 2009-08-19 | 2011-02-24 | パナソニック株式会社 | Semiconductor element, semiconductor device, and electric power converter |
| DE102009039247B9 (en) * | 2009-08-28 | 2012-01-26 | Austriamicrosystems Ag | Semiconductor body with a connection cell |
| US8507988B2 (en) * | 2009-10-02 | 2013-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage devices, systems, and methods for forming the high voltage devices |
| JP5784269B2 (en) * | 2009-11-11 | 2015-09-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8575702B2 (en) * | 2009-11-27 | 2013-11-05 | Magnachip Semiconductor, Ltd. | Semiconductor device and method for fabricating semiconductor device |
| US8390071B2 (en) * | 2010-01-19 | 2013-03-05 | Freescale Semiconductor, Inc. | ESD protection with increased current capability |
| US8242566B2 (en) * | 2010-01-19 | 2012-08-14 | Freescale Semiconductors, Inc. | Stacked ESD protection |
| JP5432750B2 (en) | 2010-02-01 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| US8304831B2 (en) * | 2010-02-08 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus of forming a gate |
| CN102194860B (en) * | 2010-03-05 | 2012-08-22 | 中芯国际集成电路制造(上海)有限公司 | Green transistors |
| DE102010014370B4 (en) * | 2010-04-09 | 2021-12-02 | X-Fab Semiconductor Foundries Ag | LDMOS transistor and LDMOS component |
| TWI395315B (en) * | 2010-04-26 | 2013-05-01 | Richtek Technology Corp | Structure in a high-voltage path of an ultra-high voltage device for providing esd protection |
| JP2011238771A (en) * | 2010-05-11 | 2011-11-24 | Hitachi Ltd | Semiconductor device |
| US8399924B2 (en) * | 2010-06-17 | 2013-03-19 | Texas Instruments Incorporated | High voltage transistor using diluted drain |
| US8576029B2 (en) | 2010-06-17 | 2013-11-05 | General Electric Company | MEMS switching array having a substrate arranged to conduct switching current |
| US7977742B1 (en) | 2010-08-20 | 2011-07-12 | Monolithic Power Systems, Inc. | Trench-gate MOSFET with capacitively depleted drift region |
| US8664720B2 (en) * | 2010-08-25 | 2014-03-04 | Infineon Technologies Ag | High voltage semiconductor devices |
| US8476684B2 (en) * | 2010-09-29 | 2013-07-02 | Analog Devices, Inc. | Field effect transistors having improved breakdown voltages and methods of forming the same |
| US8896064B2 (en) | 2010-10-18 | 2014-11-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrostatic discharge protection circuit |
| TWI408810B (en) * | 2010-11-29 | 2013-09-11 | Macronix Int Co Ltd | Low on-resistance resurf mos transistor |
| US8518782B2 (en) | 2010-12-08 | 2013-08-27 | International Business Machines Corporation | Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure |
| US8513106B2 (en) * | 2010-12-09 | 2013-08-20 | International Business Machines Corporation | Pseudo butted junction structure for back plane connection |
| CN102130060B (en) * | 2010-12-24 | 2013-02-20 | 日银Imp微电子有限公司 | Method for producing high-voltage grid drive chip for directly driving power device |
| US20120175679A1 (en) * | 2011-01-10 | 2012-07-12 | Fabio Alessio Marino | Single structure cascode device |
| US8536648B2 (en) * | 2011-02-03 | 2013-09-17 | Infineon Technologies Ag | Drain extended field effect transistors and methods of formation thereof |
| AT510837B1 (en) | 2011-07-27 | 2012-07-15 | Helmut Dr Buchberger | INHALATORKOMPONENTE |
| JP5734725B2 (en) * | 2011-04-27 | 2015-06-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US8436418B2 (en) * | 2011-06-20 | 2013-05-07 | United Microelectronics Corp. | High-voltage semiconductor device with electrostatic discharge protection |
| US8754476B2 (en) * | 2011-07-19 | 2014-06-17 | Richtek Technology Corporation, R.O.C. | High voltage device and manufacturing method thereof |
| RU2636649C9 (en) | 2011-09-06 | 2018-04-06 | Бритиш Америкэн Тобэкко (Инвестментс) Лимитед | Device and method for heating smoking material |
| US8507981B2 (en) * | 2011-10-12 | 2013-08-13 | United Microelectronics Corp. | Method of manufacturing NMOS transistor with low trigger voltage |
| US9117687B2 (en) * | 2011-10-28 | 2015-08-25 | Texas Instruments Incorporated | High voltage CMOS with triple gate oxide |
| US8530298B2 (en) * | 2011-11-01 | 2013-09-10 | Texas Instruments Incorporated | Radiation hardened integrated circuit |
| US9287253B2 (en) | 2011-11-04 | 2016-03-15 | Synopsys, Inc. | Method and apparatus for floating or applying voltage to a well of an integrated circuit |
| US8723178B2 (en) | 2012-01-20 | 2014-05-13 | Monolithic Power Systems, Inc. | Integrated field effect transistors with high voltage drain sensing |
| US9478456B2 (en) * | 2012-03-06 | 2016-10-25 | Freescale Semiconductor, Inc. | Semiconductor device with composite drift region |
| US8592274B2 (en) * | 2012-03-27 | 2013-11-26 | Alpha And Omega Semiconductor Incorporated | LDMOS with accumulation enhancement implant |
| US9236472B2 (en) * | 2012-04-17 | 2016-01-12 | Freescale Semiconductor, Inc. | Semiconductor device with integrated breakdown protection |
| US20130285136A1 (en) * | 2012-04-25 | 2013-10-31 | Macronix International Co., Ltd. | Schottky diode with enhanced breakdown voltage |
| US8853780B2 (en) * | 2012-05-07 | 2014-10-07 | Freescale Semiconductor, Inc. | Semiconductor device with drain-end drift diminution |
| US8704279B2 (en) | 2012-05-25 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded JFETs for high voltage applications |
| US9190535B2 (en) | 2012-05-25 | 2015-11-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bootstrap MOS for high voltage applications |
| US9653459B2 (en) * | 2012-07-03 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOSFET having source region formed in a double wells region |
| US8921934B2 (en) * | 2012-07-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with trench field plate |
| US10290702B2 (en) | 2012-07-31 | 2019-05-14 | Silanna Asia Pte Ltd | Power device on bulk substrate |
| US8928116B2 (en) | 2012-07-31 | 2015-01-06 | Silanna Semiconductor U.S.A., Inc. | Power device integration on a common substrate |
| US9412881B2 (en) | 2012-07-31 | 2016-08-09 | Silanna Asia Pte Ltd | Power device integration on a common substrate |
| US9142613B2 (en) | 2012-08-23 | 2015-09-22 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US9054149B2 (en) * | 2012-09-06 | 2015-06-09 | Freescale Semiconductor, Inc. | Semiconductor device with diagonal conduction path |
| US9059008B2 (en) * | 2012-10-19 | 2015-06-16 | Freescale Semiconductor, Inc. | Resurf high voltage diode |
| CN103855208A (en) * | 2012-11-28 | 2014-06-11 | 北大方正集团有限公司 | High-voltage LDMOS integrated device |
| US20140159130A1 (en) | 2012-11-30 | 2014-06-12 | Enpirion, Inc. | Apparatus including a semiconductor device coupled to a decoupling device |
| CN103855210A (en) * | 2012-12-03 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof |
| US9006820B2 (en) | 2012-12-19 | 2015-04-14 | Alpha And Omega Semiconductor Incorporated | Vertical DMOS transistor |
| TWI470791B (en) * | 2012-12-28 | 2015-01-21 | Macronix Int Co Ltd | High voltage junction field effect transistor structure |
| JP2014138091A (en) * | 2013-01-17 | 2014-07-28 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method of the same |
| US9231121B2 (en) * | 2013-01-17 | 2016-01-05 | Monolithic Power Systems, Inc. | High voltage circuit layout structure |
| US9490322B2 (en) | 2013-01-23 | 2016-11-08 | Freescale Semiconductor, Inc. | Semiconductor device with enhanced 3D resurf |
| JP6115243B2 (en) * | 2013-03-28 | 2017-04-19 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP2014212156A (en) * | 2013-04-17 | 2014-11-13 | セイコーエプソン株式会社 | Semiconductor device, and method of manufacturing the same |
| US9041127B2 (en) | 2013-05-14 | 2015-05-26 | International Business Machines Corporation | FinFET device technology with LDMOS structures for high voltage operations |
| CN103280460B (en) * | 2013-05-22 | 2016-09-07 | 矽力杰半导体技术(杭州)有限公司 | Inject and form high voltage PMOS transistor and the manufacture method thereof with superposition drift region |
| JP6004109B2 (en) * | 2013-07-19 | 2016-10-05 | 日産自動車株式会社 | Semiconductor device and manufacturing method thereof |
| TWI511294B (en) * | 2013-07-25 | 2015-12-01 | Vanguard Int Semiconduct Corp | Semiconduvtor device and methods for forming the same |
| KR101941295B1 (en) * | 2013-08-09 | 2019-01-23 | 매그나칩 반도체 유한회사 | A semicondcutor device |
| CN103606562B (en) * | 2013-09-03 | 2017-01-04 | 北京大学深圳研究院 | Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer |
| JP6221648B2 (en) * | 2013-11-06 | 2017-11-01 | セイコーエプソン株式会社 | Semiconductor device |
| JP6244177B2 (en) * | 2013-11-12 | 2017-12-06 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
| JP6252122B2 (en) * | 2013-11-13 | 2017-12-27 | 富士通株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| CN104637935B (en) * | 2013-11-14 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | It is integrated with the power transistor array structure of electrostatic discharge protective circuit |
| US9773902B2 (en) * | 2013-11-25 | 2017-09-26 | Vanguard International Semiconductor Corporation | Trench-gate semiconductor device and method for forming the same |
| US9818868B2 (en) * | 2013-11-25 | 2017-11-14 | Texas Instruments Incorporated | Metal oxide semiconductor and method of making |
| US9536938B1 (en) | 2013-11-27 | 2017-01-03 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
| US9673192B1 (en) | 2013-11-27 | 2017-06-06 | Altera Corporation | Semiconductor device including a resistor metallic layer and method of forming the same |
| US10020739B2 (en) | 2014-03-27 | 2018-07-10 | Altera Corporation | Integrated current replicator and method of operating the same |
| US9245996B2 (en) | 2014-01-02 | 2016-01-26 | United Microelectronics Corp. | Lateral double-diffused metal-oxide-semiconudctor transistor device and layout pattern for LDMOS transistor device |
| US9070766B1 (en) * | 2014-01-27 | 2015-06-30 | Macronix International Co., Ltd. | Semiconductor device and method of forming the same |
| US9543379B2 (en) | 2014-03-18 | 2017-01-10 | Nxp Usa, Inc. | Semiconductor device with peripheral breakdown protection |
| CN104979389B (en) * | 2014-04-01 | 2018-04-17 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacture method |
| US9978635B2 (en) | 2014-04-01 | 2018-05-22 | Vanguard International Semiconductor Corporation | Method and apparatus for semiconductor device with reduced device footprint |
| KR102177257B1 (en) | 2014-04-15 | 2020-11-10 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| GB201407426D0 (en) | 2014-04-28 | 2014-06-11 | Batmark Ltd | Aerosol forming component |
| US9263436B2 (en) * | 2014-04-30 | 2016-02-16 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
| US9337310B2 (en) | 2014-05-05 | 2016-05-10 | Globalfoundries Inc. | Low leakage, high frequency devices |
| EP4024474A3 (en) * | 2014-06-18 | 2022-10-26 | INTEL Corporation | Extended-drain structures for high voltage field effect transistors |
| US20150372134A1 (en) * | 2014-06-23 | 2015-12-24 | Macronix International Co., Ltd. | Semiconductor structure and method for manufacturing the same |
| US10199465B2 (en) * | 2014-06-24 | 2019-02-05 | General Electric Company | Cellular layout for semiconductor devices |
| TWI548029B (en) | 2014-10-27 | 2016-09-01 | 漢磊科技股份有限公司 | Semiconductor device and method of operating the same and structure for supressing current leakage |
| US11088031B2 (en) | 2014-11-19 | 2021-08-10 | Key Foundry Co., Ltd. | Semiconductor and method of fabricating the same |
| KR101885942B1 (en) * | 2014-11-19 | 2018-08-07 | 매그나칩 반도체 유한회사 | Semiconductor and Method of fabricating the same |
| US9590053B2 (en) * | 2014-11-25 | 2017-03-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methodology and structure for field plate design |
| US11164970B2 (en) | 2014-11-25 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact field plate |
| US10756208B2 (en) | 2014-11-25 | 2020-08-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated chip and method of forming the same |
| GB2533135B (en) | 2014-12-11 | 2020-11-11 | Nicoventures Holdings Ltd | Aerosol provision systems |
| US9559199B2 (en) | 2014-12-18 | 2017-01-31 | Silanna Asia Pte Ltd | LDMOS with adaptively biased gate-shield |
| US11171215B2 (en) | 2014-12-18 | 2021-11-09 | Silanna Asia Pte Ltd | Threshold voltage adjustment using adaptively biased shield plate |
| US10050115B2 (en) * | 2014-12-30 | 2018-08-14 | Globalfoundries Inc. | Tapered gate oxide in LDMOS devices |
| US9553143B2 (en) * | 2015-02-12 | 2017-01-24 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
| US10103627B2 (en) | 2015-02-26 | 2018-10-16 | Altera Corporation | Packaged integrated circuit including a switch-mode regulator and method of forming the same |
| KR101975630B1 (en) * | 2015-04-03 | 2019-08-29 | 매그나칩 반도체 유한회사 | Semiconductor Structure having a Junction Field Effect Transistor and a High Voltage Transistor and Method for Manufacturing the same |
| US10784372B2 (en) * | 2015-04-03 | 2020-09-22 | Magnachip Semiconductor, Ltd. | Semiconductor device with high voltage field effect transistor and junction field effect transistor |
| CN106158921B (en) * | 2015-04-10 | 2019-07-23 | 无锡华润上华科技有限公司 | Has the transverse diffusion metal oxide semiconductor field effect pipe of RESURF structure |
| CN104966734A (en) * | 2015-05-06 | 2015-10-07 | 深圳市海泰康微电子有限公司 | Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor used for high frequency circuit design and preparation method thereof |
| KR102389294B1 (en) * | 2015-06-16 | 2022-04-20 | 삼성전자주식회사 | Semiconductor device and fabricating method thereof |
| GB201511359D0 (en) | 2015-06-29 | 2015-08-12 | Nicoventures Holdings Ltd | Electronic vapour provision system |
| GB201511349D0 (en) | 2015-06-29 | 2015-08-12 | Nicoventures Holdings Ltd | Electronic aerosol provision systems |
| GB201511358D0 (en) | 2015-06-29 | 2015-08-12 | Nicoventures Holdings Ltd | Electronic aerosol provision systems |
| DE102015110490A1 (en) * | 2015-06-30 | 2017-01-05 | Infineon Technologies Austria Ag | Semiconductor devices and a method of forming a semiconductor device |
| KR102032221B1 (en) * | 2015-11-10 | 2019-10-16 | 서강대학교산학협력단 | Capacitorless 1t dram cell device using tunneling field effect transistor, fabrication method thereof and memory array using the same |
| BR112018071824B1 (en) | 2016-04-27 | 2023-01-10 | Nicoventures Trading Limited | SUB-ASSEMBLY, SYSTEM, METHOD FOR MANUFACTURING A VAPORIZER AND ELECTRONIC STEAM DELIVERY DEVICE |
| US9871135B2 (en) | 2016-06-02 | 2018-01-16 | Nxp Usa, Inc. | Semiconductor device and method of making |
| CN107564901B (en) * | 2016-06-30 | 2020-03-13 | 中芯国际集成电路制造（天津）有限公司 | LDMOS device with ESD protection function and layout thereof |
| TWI614811B (en) * | 2016-08-18 | 2018-02-11 | 世界先進積體電路股份有限公司 | Semiconductor devices and methods for manufacturing the same |
| CN106206677B (en) * | 2016-08-25 | 2019-09-27 | 电子科技大学 | The junction termination structures of lateral high voltage power device |
| US9899515B1 (en) | 2016-10-31 | 2018-02-20 | International Business Machines Corporation | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain |
| US20180138307A1 (en) * | 2016-11-17 | 2018-05-17 | Globalfoundries Inc. | Tunnel finfet with self-aligned gate |
| US10861843B2 (en) | 2016-12-21 | 2020-12-08 | Texas Instruments Incorporated | Electrostatic discharge protection device |
| US10056260B2 (en) | 2017-01-05 | 2018-08-21 | Vanguard International Semiconductor Corporation | Schottky diode with dielectrically isolated diffusions, and method of manufacturing the same |
| US9905687B1 (en) | 2017-02-17 | 2018-02-27 | Nxp Usa, Inc. | Semiconductor device and method of making |
| US10083897B2 (en) | 2017-02-20 | 2018-09-25 | Silanna Asia Pte Ltd | Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact |
| US9923059B1 (en) | 2017-02-20 | 2018-03-20 | Silanna Asia Pte Ltd | Connection arrangements for integrated lateral diffusion field effect transistors |
| TWI711159B (en) * | 2017-03-28 | 2020-11-21 | 聯華電子股份有限公司 | Semiconductor memory device |
| US9954098B1 (en) | 2017-04-26 | 2018-04-24 | Macronix International Co., Ltd. | Semiconductor structure and method of manufacturing the same |
| US10468485B2 (en) * | 2017-05-26 | 2019-11-05 | Allegro Microsystems, Llc | Metal-oxide semiconductor (MOS) device structure based on a poly-filled trench isolation region |
| US20190131404A1 (en) * | 2017-10-30 | 2019-05-02 | Analog Devices Global Unlimited Company | Low gate current junction field effect transistor device architecture |
| US10636873B2 (en) * | 2017-11-22 | 2020-04-28 | Vanguard International Semiconductor Corporation | Method of fabricating semiconductor device |
| US10580890B2 (en) | 2017-12-04 | 2020-03-03 | Texas Instruments Incorporated | Drain extended NMOS transistor |
| US10424661B1 (en) | 2018-04-04 | 2019-09-24 | Silanna Asia Pte Ltd | Avalanche robust LDMOS |
| CN109037337A (en) * | 2018-06-28 | 2018-12-18 | 华为技术有限公司 | A kind of power semiconductor and manufacturing method |
| CN108962890B (en) * | 2018-07-27 | 2021-07-30 | 深圳市南硕明泰科技有限公司 | Integrated semiconductor device |
| CN108817764A (en) * | 2018-08-15 | 2018-11-16 | 广州文冲船厂有限责任公司 | A kind of welding box beam equipment and welding method |
| CN111326578B (en) * | 2018-12-13 | 2022-08-02 | 中芯集成电路（宁波）有限公司 | Gate drive integrated circuit |
| CN109671706B (en) * | 2018-12-25 | 2021-03-16 | 电子科技大学 | P-type epitaxy-based JCD integrated device and preparation method thereof |
| CN109686736B (en) * | 2018-12-25 | 2021-02-26 | 电子科技大学 | N-type epitaxy based JCD integrated device and preparation method thereof |
| US11211484B2 (en) * | 2019-02-13 | 2021-12-28 | Monolithic Power Systems, Inc. | Vertical transistor structure with buried channel and resurf regions and method of manufacturing the same |
| JP7157691B2 (en) * | 2019-03-20 | 2022-10-20 | 株式会社東芝 | semiconductor equipment |
| US11011528B2 (en) | 2019-05-08 | 2021-05-18 | International Business Machines Corporation | Asymmetric gate edge spacing for SRAM structures |
| KR102265031B1 (en) * | 2019-07-25 | 2021-06-14 | 주식회사 키 파운드리 | Semiconductor Device with Controllable Channel Length and Manufacturing Method thereof |
| TWI698017B (en) * | 2019-09-17 | 2020-07-01 | 瑞昱半導體股份有限公司 | High voltage semiconductor device and manufacturing method thereof |
| US11227921B2 (en) * | 2019-11-22 | 2022-01-18 | Nxp Usa, Inc. | Laterally-diffused metal-oxide semiconductor transistor and method therefor |
| US10910478B1 (en) | 2020-03-04 | 2021-02-02 | Shuming Xu | Metal-oxide-semiconductor field-effect transistor having enhanced high-frequency performance |
| CN111354798B (en) * | 2020-03-16 | 2022-07-01 | 上海晶丰明源半导体股份有限公司 | Bidirectional asymmetric dual-channel switch device and manufacturing method thereof |
| US11411086B2 (en) * | 2020-03-17 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Field plate and isolation structure for high voltage device |
| CN111354799B (en) * | 2020-04-10 | 2022-07-01 | 上海晶丰明源半导体股份有限公司 | Bidirectional asymmetric double-channel switch device and manufacturing method thereof |
| US11393921B2 (en) * | 2020-08-26 | 2022-07-19 | Vanguard International Semiconductor Corporation | High-voltage semiconductor device |
| US11133797B1 (en) * | 2020-11-24 | 2021-09-28 | Diodes Incorporated | Bootstrap circuit for gate driver |
| CN112821366B (en) * | 2020-12-30 | 2022-08-12 | 思瑞浦微电子科技（苏州）股份有限公司 | Bidirectional electrostatic protection circuit |
| TWI776413B (en) * | 2021-03-05 | 2022-09-01 | 全宇昕科技股份有限公司 | Integrated power element |
| US12068376B2 (en) * | 2021-08-05 | 2024-08-20 | Taiwan Semiconductor Manufacturing Company Limited | Metal field plates |
| US11942542B2 (en) | 2021-09-29 | 2024-03-26 | Vanguard International Semiconductor Corporation | Semiconductor device and fabrication method thereof |
| TWI821798B (en) * | 2021-11-23 | 2023-11-11 | 世界先進積體電路股份有限公司 | Semiconductor device and fabrication method thereof |
| US20230197846A1 (en) * | 2021-12-17 | 2023-06-22 | Infineon Technologies Austria Ag | Power semiconductor device and methods of producing a power semiconductor device |
| US11855139B2 (en) | 2022-01-10 | 2023-12-26 | Globalfoundries U.S. Inc. | Extended drain field effect transistor with trench gate(s) and method |
| CN117096153B (en) * | 2023-10-18 | 2024-01-19 | 荣湃半导体（上海）有限公司 | ESD integrated MOSFET device and preparation method thereof |
Family Cites Families (66)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US552105A (en) * | 1895-12-31 | Harry e | ||
| US4345265A (en) | 1980-04-14 | 1982-08-17 | Supertex, Inc. | MOS Power transistor with improved high-voltage capability |
| US4411058A (en) | 1981-08-31 | 1983-10-25 | Hughes Aircraft Company | Process for fabricating CMOS devices with self-aligned channel stops |
| US5055417A (en) | 1987-06-11 | 1991-10-08 | National Semiconductor Corporation | Process for fabricating self-aligned high performance lateral action silicon-controlled rectifier and static random access memory cells |
| US5218228A (en) | 1987-08-07 | 1993-06-08 | Siliconix Inc. | High voltage MOS transistors with reduced parasitic current gain |
| JPH02102575A (en) * | 1988-10-11 | 1990-04-16 | Nec Corp | Semiconductor device |
| US5156989A (en) | 1988-11-08 | 1992-10-20 | Siliconix, Incorporated | Complementary, isolated DMOS IC technology |
| US5204545A (en) | 1989-11-22 | 1993-04-20 | Mitsubishi Denki Kabushiki Kaisha | Structure for preventing field concentration in semiconductor device and method of forming the same |
| US5374843A (en) * | 1991-05-06 | 1994-12-20 | Silinconix, Inc. | Lightly-doped drain MOSFET with improved breakdown characteristics |
| JP2965783B2 (en) * | 1991-07-17 | 1999-10-18 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| DE69225552T2 (en) | 1991-10-15 | 1999-01-07 | Texas Instruments Inc., Dallas, Tex. | Lateral double-diffused MOS transistor and method for its production |
| US5376816A (en) * | 1992-06-24 | 1994-12-27 | Nec Corporation | Bi-cmos integrated circuit device having buried region use in common for bipolar and mos transistors |
| US5539238A (en) | 1992-09-02 | 1996-07-23 | Texas Instruments Incorporated | Area efficient high voltage Mosfets with vertical resurf drift regions |
| US5422508A (en) | 1992-09-21 | 1995-06-06 | Siliconix Incorporated | BiCDMOS structure |
| JP2978345B2 (en) | 1992-11-26 | 1999-11-15 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
| US5349225A (en) * | 1993-04-12 | 1994-09-20 | Texas Instruments Incorporated | Field effect transistor with a lightly doped drain |
| US6278162B1 (en) | 1993-06-30 | 2001-08-21 | Integrated Device Technology, Inc. | ESD protection for LDD devices |
| US5426325A (en) | 1993-08-04 | 1995-06-20 | Siliconix Incorporated | Metal crossover in high voltage IC with graduated doping control |
| JP3383377B2 (en) | 1993-10-28 | 2003-03-04 | 株式会社東芝 | Vertical normally-on type power MOSFET having a trench structure and method of manufacturing the same |
| US5817546A (en) | 1994-06-23 | 1998-10-06 | Stmicroelectronics S.R.L. | Process of making a MOS-technology power device |
| US5486718A (en) | 1994-07-05 | 1996-01-23 | Motorola, Inc. | High voltage planar edge termination structure and method of making same |
| US5521105A (en) | 1994-08-12 | 1996-05-28 | United Microelectronics Corporation | Method of forming counter-doped island in power MOSFET |
| US5698458A (en) | 1994-09-30 | 1997-12-16 | United Microelectronics Corporation | Multiple well device and process of manufacture |
| US5585294A (en) | 1994-10-14 | 1996-12-17 | Texas Instruments Incorporated | Method of fabricating lateral double diffused MOS (LDMOS) transistors |
| US5541439A (en) | 1994-11-17 | 1996-07-30 | Xerox Corporation | Layout for a high voltage darlington pair |
| US5640497A (en) | 1995-01-23 | 1997-06-17 | Woolbright; Phillip Alexander | Layout redesign using polygon manipulation |
| US5998837A (en) | 1995-06-02 | 1999-12-07 | Siliconix Incorporated | Trench-gated power MOSFET with protective diode having adjustable breakdown voltage |
| US5777362A (en) | 1995-06-07 | 1998-07-07 | Harris Corporation | High efficiency quasi-vertical DMOS in CMOS or BICMOS process |
| EP0789401A3 (en) * | 1995-08-25 | 1998-09-16 | Matsushita Electric Industrial Co., Ltd. | LD MOSFET or MOSFET with an integrated circuit containing thereof and manufacturing method |
| JPH0992728A (en) * | 1995-09-21 | 1997-04-04 | Mitsubishi Electric Corp | Complementary mosfet transistor and fabrication thereof |
| US5973367A (en) * | 1995-10-13 | 1999-10-26 | Siliconix Incorporated | Multiple gated MOSFET for use in DC-DC converter |
| US6734496B2 (en) | 1996-01-22 | 2004-05-11 | Fuji Electric Co., Ltd. | Semiconductor device |
| GB2309336B (en) | 1996-01-22 | 2001-05-23 | Fuji Electric Co Ltd | Semiconductor device |
| US5966599A (en) | 1996-05-21 | 1999-10-12 | Lsi Logic Corporation | Method for fabricating a low trigger voltage silicon controlled rectifier and thick field device |
| WO1998014994A1 (en) | 1996-09-30 | 1998-04-09 | Lsi Logic Corporation | Semiconductor fabrication |
| US6207994B1 (en) * | 1996-11-05 | 2001-03-27 | Power Integrations, Inc. | High-voltage transistor with multi-layer conduction region |
| JP3393544B2 (en) * | 1997-02-26 | 2003-04-07 | シャープ株式会社 | Method for manufacturing semiconductor device |
| US5909103A (en) | 1997-07-24 | 1999-06-01 | Siliconix Incorporated | Safety switch for lithium ion battery |
| US6429481B1 (en) * | 1997-11-14 | 2002-08-06 | Fairchild Semiconductor Corporation | Field effect transistor and method of its manufacture |
| JP3641547B2 (en) | 1998-03-25 | 2005-04-20 | 株式会社豊田中央研究所 | Semiconductor device including lateral MOS element |
| US6072216A (en) | 1998-05-01 | 2000-06-06 | Siliconix Incorporated | Vertical DMOS field effect transistor with conformal buried layer for reduced on-resistance |
| US6063678A (en) * | 1998-05-04 | 2000-05-16 | Xemod, Inc. | Fabrication of lateral RF MOS devices with enhanced RF properties |
| KR100272176B1 (en) | 1998-09-30 | 2000-12-01 | 김덕중 | Method fabricating bicdmos device |
| FR2785090B1 (en) * | 1998-10-23 | 2001-01-19 | St Microelectronics Sa | POWER COMPONENT CARRYING INTERCONNECTIONS |
| DE69806484D1 (en) | 1998-11-17 | 2002-08-14 | St Microelectronics Srl | Method of making a vertical channel MOSFET |
| KR100281908B1 (en) | 1998-11-20 | 2001-02-15 | 김덕중 | Semiconductor device and manufacturing method |
| EP1166363B1 (en) | 1999-03-01 | 2011-06-29 | GENERAL SEMICONDUCTOR, Inc. | Trench dmos transistor structure having a low resistance path to a drain contact located on an upper surface |
| JP3443355B2 (en) * | 1999-03-12 | 2003-09-02 | 三洋電機株式会社 | Method for manufacturing semiconductor device |
| US6225181B1 (en) * | 1999-04-19 | 2001-05-01 | National Semiconductor Corp. | Trench isolated bipolar transistor structure integrated with CMOS technology |
| KR100300069B1 (en) * | 1999-05-10 | 2001-09-26 | 김영환 | Semiconductor device and fabrication method of thereof |
| US6274898B1 (en) | 1999-05-21 | 2001-08-14 | Vantis Corporation | Triple-well EEPROM cell using P-well for tunneling across a channel |
| US6271552B1 (en) * | 1999-10-04 | 2001-08-07 | Xemod, Inc | Lateral RF MOS device with improved breakdown voltage |
| US6489653B2 (en) | 1999-12-27 | 2002-12-03 | Kabushiki Kaisha Toshiba | Lateral high-breakdown-voltage transistor |
| US6835627B1 (en) | 2000-01-10 | 2004-12-28 | Analog Devices, Inc. | Method for forming a DMOS device and a DMOS device |
| US6417554B1 (en) * | 2000-04-27 | 2002-07-09 | International Rectifier Corporation | Latch free IGBT with schottky gate |
| US6468847B1 (en) | 2000-11-27 | 2002-10-22 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
| TW511269B (en) | 2001-03-05 | 2002-11-21 | Taiwan Semiconductor Mfg | Silicon-controlled rectifier device having deep well region structure and its application on electrostatic discharge protection circuit |
| JP4665141B2 (en) * | 2001-06-29 | 2011-04-06 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| US6552597B1 (en) | 2001-11-02 | 2003-04-22 | Power Integrations, Inc. | Integrated circuit with closely coupled high voltage output and offline transistor pair |
| US6686627B2 (en) * | 2001-12-26 | 2004-02-03 | Sirenza Microdevices, Inc. | Multiple conductive plug structure for lateral RF MOS devices |
| US6900091B2 (en) * | 2002-08-14 | 2005-05-31 | Advanced Analogic Technologies, Inc. | Isolated complementary MOS devices in epi-less substrate |
| US7719054B2 (en) | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
| US6855985B2 (en) * | 2002-09-29 | 2005-02-15 | Advanced Analogic Technologies, Inc. | Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology |
| DE10309400B4 (en) | 2003-03-04 | 2009-07-30 | Infineon Technologies Ag | Semiconductor device with increased dielectric strength and / or reduced on-resistance |
| US7126166B2 (en) | 2004-03-11 | 2006-10-24 | Semiconductor Components Industries, L.L.C. | High voltage lateral FET structure with improved on resistance performance |
| US7061057B2 (en) | 2004-06-16 | 2006-06-13 | Cree Microwave, Llc | Laterally diffused MOS transistor having N+ source contact to N-doped substrate |
-
2006
- 2006-05-31 US US11/443,745 patent/US7719054B2/en not_active Expired - Fee Related
-
2007
- 2007-05-30 KR KR1020087031001A patent/KR101298339B1/en active IP Right Grant
- 2007-05-30 EP EP07809223A patent/EP2044622A4/en not_active Withdrawn
- 2007-05-30 CN CN2007800279592A patent/CN101542697B/en not_active Expired - Fee Related
- 2007-05-30 JP JP2009513242A patent/JP5321840B2/en not_active Expired - Fee Related
- 2007-05-30 WO PCT/US2007/012686 patent/WO2007142937A2/en active Application Filing
- 2007-05-30 KR KR1020127033564A patent/KR101268804B1/en not_active IP Right Cessation
- 2007-05-30 KR KR1020127033563A patent/KR101260639B1/en not_active IP Right Cessation
- 2007-05-30 KR KR1020127033560A patent/KR101267770B1/en not_active IP Right Cessation
- 2007-05-30 KR KR1020127033558A patent/KR20130006714A/en active IP Right Grant
- 2007-05-30 KR KR1020127033561A patent/KR101245932B1/en not_active IP Right Cessation
- 2007-05-30 KR KR1020137012927A patent/KR101415490B1/en active IP Right Grant
- 2007-05-30 KR KR1020127033559A patent/KR101267695B1/en not_active IP Right Cessation
- 2007-05-30 KR KR1020137012928A patent/KR101415419B1/en active IP Right Grant
- 2007-05-30 KR KR1020137010016A patent/KR101340188B1/en active IP Right Grant
- 2007-05-31 TW TW096119624A patent/TWI374508B/en not_active IP Right Cessation
- 2007-11-05 US US11/982,792 patent/US7683426B2/en not_active Expired - Fee Related
- 2007-11-05 US US11/982,803 patent/US7683453B2/en not_active Expired - Fee Related
- 2007-11-05 US US11/982,781 patent/US7812393B2/en not_active Expired - Fee Related
- 2007-11-05 US US11/982,780 patent/US7489007B2/en not_active Expired - Fee Related
- 2007-11-05 US US11/982,793 patent/US7605428B2/en not_active Expired - Fee Related
- 2007-11-05 US US11/982,764 patent/US7576391B2/en not_active Expired - Fee Related
Cited By (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102612753A (en) * | 2009-11-30 | 2012-07-25 | 松下电器产业株式会社 | Bidirectional switch |
| CN102437187A (en) * | 2010-09-29 | 2012-05-02 | 万国半导体股份有限公司 | Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method |
| CN102437187B (en) * | 2010-09-29 | 2015-07-01 | 万国半导体股份有限公司 | Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method |
| CN102054785B (en) * | 2010-11-04 | 2012-11-07 | 电子科技大学 | Manufacturing method of high-voltage BCD semiconductor device |
| CN102054785A (en) * | 2010-11-04 | 2011-05-11 | 电子科技大学 | Manufacturing method of high-voltage BCD semiconductor device |
| CN102487082A (en) * | 2010-12-02 | 2012-06-06 | 上海华虹Nec电子有限公司 | Horizontal-groove metal-oxide semiconductor device |
| CN103208523A (en) * | 2011-08-01 | 2013-07-17 | 成都芯源系统有限公司 | High voltage device and method of manufacturing the same |
| CN103208523B (en) * | 2011-08-01 | 2016-11-30 | 成都芯源系统有限公司 | High voltage device and method of manufacturing the same |
| CN102738215A (en) * | 2011-08-18 | 2012-10-17 | 成都芯源系统有限公司 | Lateral double-diffused metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN103247623A (en) * | 2012-02-03 | 2013-08-14 | 爱思开海力士有限公司 | Semiconductor devices and methods of manufacturing the same |
| CN103247623B (en) * | 2012-02-03 | 2017-05-03 | 爱思开海力士有限公司 | Semiconductor devices and methods of manufacturing the same |
| CN103367449A (en) * | 2012-04-06 | 2013-10-23 | 三星电子株式会社 | Semiconductor devices including guard ring and related semiconductor systems |
| CN103456732B (en) * | 2012-05-30 | 2016-06-15 | 旺宏电子股份有限公司 | There is the Schottky diode strengthening breakdown voltage |
| CN103456732A (en) * | 2012-05-30 | 2013-12-18 | 旺宏电子股份有限公司 | Schottky diode with strengthened breakdown voltage |
| CN102723304A (en) * | 2012-05-31 | 2012-10-10 | 日银Imp微电子有限公司 | Preparation method of N-trap high-voltage gate driving chip for directly driving power device |
| CN102723304B (en) * | 2012-05-31 | 2014-07-16 | 日银Imp微电子有限公司 | Preparation method of N-trap high-voltage gate driving chip for directly driving power device |
| CN103839891A (en) * | 2012-11-26 | 2014-06-04 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103996680B (en) * | 2013-02-20 | 2016-12-28 | 台湾积体电路制造股份有限公司 | High voltage transistor structure and method thereof |
| US10269959B2 (en) | 2013-02-20 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage transistor structure and method |
| US11107916B2 (en) | 2013-02-20 | 2021-08-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage transistor structure |
| US9799766B2 (en) | 2013-02-20 | 2017-10-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage transistor structure and method |
| US11935950B2 (en) | 2013-02-20 | 2024-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage transistor structure |
| CN103996680A (en) * | 2013-02-20 | 2014-08-20 | 台湾积体电路制造股份有限公司 | High voltage transistor structure and method |
| US10658477B2 (en) | 2013-05-13 | 2020-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Junction gate field-effect transistor (JFET) having source/drain and gate isolation regions |
| CN104167360B (en) * | 2013-05-16 | 2017-05-31 | 无锡华润上华半导体有限公司 | Transverse diffusion metal oxide semiconductor device and its manufacture method |
| CN104167360A (en) * | 2013-05-16 | 2014-11-26 | 无锡华润上华半导体有限公司 | Laterally-diffused metal oxide semiconductor device and manufacture method thereof |
| CN104425595A (en) * | 2013-08-21 | 2015-03-18 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacture method thereof |
| CN105280718A (en) * | 2014-07-02 | 2016-01-27 | 台湾积体电路制造股份有限公司 | Junction gate field-effect transistor (jfet), semiconductor device and method of manufacturing |
| CN105428322A (en) * | 2014-09-15 | 2016-03-23 | 英飞凌科技奥地利有限公司 | Iii-v semiconductor material based ac switch |
| CN105720101A (en) * | 2014-12-19 | 2016-06-29 | 联发科技股份有限公司 | Semiconductor device and fabrication method thereof |
| CN107017247A (en) * | 2015-12-22 | 2017-08-04 | 万国半导体股份有限公司 | Transient Voltage Suppressor with low breakdown voltage |
| CN108475678B (en) * | 2016-01-21 | 2023-08-15 | 德克萨斯仪器股份有限公司 | Drift region implant self-aligned to field relief oxide with sidewall dielectric |
| CN108475678A (en) * | 2016-01-21 | 2018-08-31 | 德克萨斯仪器股份有限公司 | It is self-aligned to the drift region injection of the field release oxide with side wall dielectric |
| CN109891749A (en) * | 2016-03-22 | 2019-06-14 | 密克罗奇普技术公司 | The high pressure transmission of standard BCD technique/reception switch |
| CN109891749B (en) * | 2016-03-22 | 2023-03-31 | 密克罗奇普技术公司 | High-voltage transmitting/receiving switch of standard BCD (binary coded decimal) process |
| CN107785305A (en) * | 2016-08-31 | 2018-03-09 | 无锡华润上华科技有限公司 | The device of integrated depletion type junction field effect transistor |
| CN106876464A (en) * | 2016-12-29 | 2017-06-20 | 西安电子科技大学 | A kind of lateral double diffusion metal oxide semiconductor FET |
| US10262903B2 (en) | 2017-06-22 | 2019-04-16 | Globalfoundries Inc. | Boundary spacer structure and integration |
| CN111279477A (en) * | 2017-12-21 | 2020-06-12 | 德州仪器公司 | High voltage lateral junction diode device |
| CN111279477B (en) * | 2017-12-21 | 2024-08-09 | 德州仪器公司 | High voltage lateral junction diode device |
| CN110620111A (en) * | 2018-06-20 | 2019-12-27 | 格芯新加坡私人有限公司 | Extended Drain MOSFET (EDMOS) |
| CN110212900A (en) * | 2019-06-10 | 2019-09-06 | 桂林电子科技大学 | A kind of double trap CMOS complementary switch for eliminating bulk effect and substrate leakage |
| CN111430346A (en) * | 2020-03-30 | 2020-07-17 | 电子科技大学 | Power integrated semiconductor device |
| CN111430346B (en) * | 2020-03-30 | 2023-07-07 | 电子科技大学 | Power integrated semiconductor device |
| CN111785774A (en) * | 2020-06-15 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | CMOS device in BCD process and manufacturing method thereof |
| CN111785774B (en) * | 2020-06-15 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | CMOS device in BCD process and manufacturing method thereof |
Also Published As
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101542697B (en) | Methods of forming the same high-voltage bipolar-CMOS-DMOS integrated circuit devices and its module | |
| US9601612B2 (en) | MOSFET having dual-gate cells with an integrated channel diode | |
| KR100867574B1 (en) | Power device and method for manufacturing the same | |
| KR100932137B1 (en) | Structure of Horizontal DMOS Device and Manufacturing Method Thereof | |
| US9887288B2 (en) | LDMOS device with body diffusion self-aligned to gate | |
| US10886418B2 (en) | Split-gate JFET with field plate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120125 Termination date: 20190530 |