CN107785305A - The device of integrated depletion type junction field effect transistor - Google Patents
The device of integrated depletion type junction field effect transistor Download PDFInfo
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- CN107785305A CN107785305A CN201610796651.5A CN201610796651A CN107785305A CN 107785305 A CN107785305 A CN 107785305A CN 201610796651 A CN201610796651 A CN 201610796651A CN 107785305 A CN107785305 A CN 107785305A
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- effect transistor
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- junction field
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- 230000005669 field effect Effects 0.000 title claims abstract description 30
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 238000009413 insulation Methods 0.000 claims abstract description 10
- 230000000903 blocking effect Effects 0.000 claims abstract description 9
- 239000007943 implant Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000000926 separation method Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention relates to a kind of device of integrated depletion type junction field effect transistor, including JFET areas, power device area, located at the device back side the first conduction type drain electrode and located at drain electrode towards the first conductivity regions on the positive face of device, the shared drain electrode in JFET areas and power device area and the first conductivity regions, the intersection in JFET areas and power device area includes the isolation well of the second conduction type and the insulation implant blocking layer located at isolation well surface formed with isolation structure, isolation structure.The present invention is isolated in the intersection in JFET areas and power device area using the isolation well of a second deeper conduction type, it is set there are enough junction depths when pushing away trap, so leakage path lengthens significantly, serve good isolation effect, the lateral separation of the isolation well can accomplish very short, greatly save the area of whole integrated device.The isolation well can be mutually compatible with junction terminal extension technology, without increasing extra reticle.
Description
Technical field
The present invention relates to semiconductor fabrication, more particularly to a kind of device of integrated depletion type junction field effect transistor
Part.
Background technology
Integrated high voltage junction field effect transistor (the Junction Field-Effect on high-pressure process platform
Transistor, JFET) for nowadays smart-power IC field a kind of advanced exploitation with conceiving, it can be greatly promoted
The ON state performance of longitudinal power device, and significantly reduce chip area, meet the main flow of current smart power device manufacture
Trend.
The high pressure of traditional structure, which integrates JFET, has better simply technique to realize, but it turns into isolating for power device
One difficult point.In operation principle, it is desirable to which when JFET power cut-offs are off under state, power device, which is in, to be opened just
Normal working condition, now electric current drain electrode is flowed to by the longitudinal channel of power device, isolation structure seeks to prevent current direction
JFET, that is, prevent from leaking electricity.The requirement of isolation is not influence the service behaviour and shape of power device after JFET device is integrated with
The positive work of state, i.e. power device is simultaneously without electric leakage, and breakdown point is fixed when reversely exhausting, and stable breakdown voltage is constant.Tradition collection
Partition method into JFET is to pull open enough distances by N- epitaxial layers in the intersection of JFET and power device.With distance
Lengthen, current pathway is longer and less flows to JFET areas, so as to reach the effect of shielding electric leakage.The problem of this method is
Area of isolation occupies substantial amounts of area and increases the area of whole integrated chip, causes waste, while compatibility is not high,
The problems such as reliability can be brought.
The content of the invention
Based on this, it is necessary to provide a kind of device of integrated depletion type junction field effect transistor.
A kind of device of integrated depletion type junction field effect transistor, the device include JFET areas, power device area, set
Drained in the drain electrode of first conduction type at the device back side and located at described towards first on the positive face of the device
The drain electrode and the first conductivity regions, the JFET areas and work(are shared by conductivity regions, the JFET areas and power device area
Formed with isolation structure, the isolation structure includes the isolation well of the second conduction type and located at described the intersection of rate device region
The insulation implant blocking layer on isolation well surface.
In one of the embodiments, the material of the insulation implant blocking layer is silica.
In one of the embodiments, the JFET areas and power device area include the well region of the second conduction type, institute
The well depth for stating isolation well is more than the well depth of the well region, ion concentration is less than the ion concentration of the well region.
In one of the embodiments, the well depth of the isolation well is 8.5 microns~13.5 microns.
In one of the embodiments, the device is vertical DMOS field-effect transistor
VDMOS。
In one of the embodiments, the power device area also includes grid, in the well region in power device area
The ohmic contact regions of the VDMOS source electrodes of first conduction type and the second conduction type in the well region in power device area.
In one of the embodiments, the grid is planar gate, and the both ends of the grid respectively extend to a VDMOS source electrodes
Surface.
In one of the embodiments, the grid is trench gate, the grid being located between two adjacent VDMOS source electrodes
First conductivity regions are extended downward through the well region.
In one of the embodiments, the JFET areas also include the first conductive-type being located between the two adjacent well regions
The channel region of type.
In one of the embodiments, first conduction type is N-type, and second conduction type is p-type, described
One conductivity regions are N-type epitaxy layer.
The device of above-mentioned integrated depletion type junction field effect transistor, used in the intersection in JFET areas and power device area
The isolation well of one the second deeper conduction type is isolated, and it is had enough junction depths, such drain circuit when pushing away trap
Footpath lengthens significantly, serves good isolation effect, and the lateral separation of the isolation well can accomplish very short, greatly save whole
The area of integrated device.The isolation well can be mutually compatible with junction terminal extension technology, you can utilizes the termination environment of power device
Second conductive type of trap is completed, without increasing extra photoetching as isolation well on the Process ba- sis of traditional power device
Version, the cost of technique productions is not improved, be advantageous to improve the competitiveness of product in market.Insulation injection is set on the surface of isolation well
It barrier layer, can prevent overtension from opening field pipe, while shield ion implanting, while ensure that good isolation also
Improve the reliability of power device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, embodiment will be described below
In the required accompanying drawing used be briefly described, it should be apparent that, drawings in the following description be only the present invention some
Embodiment, for those of ordinary skill in the art, on the premise of not paying creative work, can also be attached according to these
Figure obtains the accompanying drawing of other embodiment.
Fig. 1 is the section of the device of the integrated depletion type junction field effect transistor using planar gate structure in an embodiment
Structural representation；
Fig. 2 is the section of the device of the integrated depletion type junction field effect transistor using trench gate structure in an embodiment
Structural representation；
Fig. 3 is a kind of traditional integrated JFET VDMOS and above-mentioned integrated depletion type junction field effect transistor device
Breakdown voltage comparison diagram.
Embodiment
For the ease of understanding the present invention, the present invention is described more fully below with reference to relevant drawings.In accompanying drawing
Give the preferred embodiment of the present invention.But the present invention can realize in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, the purpose for providing these embodiments is made to the disclosure more thorough and comprehensive.
Unless otherwise defined, all of technologies and scientific terms used here by the article is with belonging to technical field of the invention
The implication that technical staff is generally understood that is identical.Term used in the description of the invention herein is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein " and/or " include one or more phases
The arbitrary and all combination of the Listed Items of pass.
It should be noted that when element is referred to as " being fixed on " another element, it can be directly on another element
Or there may also be element placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " on ",
" under ", "left", "right" and similar statement for illustrative purposes only.
Semiconductor applications vocabulary used herein is the technical words that those skilled in the art commonly use, such as p-type
And N-type impurity, to distinguish doping concentration, P+ type is easily represented to the p-type of heavy dopant concentration, the P of doping concentration during p-type represents
Type, P-type represent the p-type that concentration is lightly doped, and N+ types represent the N-type of heavy dopant concentration, the N-type of doping concentration, N- during N-type represents
Type represents the N-type that concentration is lightly doped.
Fig. 1 is the section of the device of the integrated depletion type junction field effect transistor using planar gate structure in an embodiment
Structural representation, in the present embodiment, definition N-type are the first conduction type, and p-type is the second conduction type, and junction field is brilliant
Body pipe (Junction Field-Effect Transistor, JFET) is integrated in vertical DMOS field
On effect transistor (Vertical Double-diffused MOSFET, VDMOS).As shown in fig. 1, device is pressed into structure
It is divided into JFET areas and VDMOS areas, the leakage of the shared N-type located at the device back side (i.e. face directed downwardly in Fig. 1) in JFET areas and VDMOS areas
Pole 310, and the N-type region 309 located at drain electrode 310 positive (i.e. face in Fig. 1 upward).In the present embodiment, drain electrode 310 is that N+ leaks
Pole, N-type region 309 are N- epitaxial layers (can also directly use N-type substrate in other embodiments), the drift region as VDMOS.
In the present embodiment, the intersection in JFET areas and VDMOS areas includes the isolation well of p-type formed with isolation structure, the isolation structure
305 and the insulation implant blocking layer 304 located at the surface of isolation well 305.
The device of above-mentioned integrated depletion type junction field effect transistor, used in the intersection in JFET areas and power device area
The isolation well 305 of one the second deeper conduction type is isolated, and it is had enough junction depths when pushing away trap, is so leaked electricity
Path lengthens significantly, serves good isolation effect, and the lateral separation of the isolation well 305 can accomplish very short, greatly save
The area of whole integrated device.The isolation well 305 can be mutually compatible with junction terminal extension technology, you can utilizes power device
Second conductive type of trap of termination environment is completed, without increase as isolation well 305 on the Process ba- sis of traditional power device
Extra reticle, the cost of technique productions is not improved, be advantageous to improve the competitiveness of product in market.In the table of isolation well 305
Face sets insulation implant blocking layer 304, can prevent overtension from opening field pipe, while shields ion implanting, ensure that
The reliability of power device is also improved while good isolation.
In one of the embodiments, the material of insulation implant blocking layer 304 is silica.Field oxygen can specifically be used
Layer is as insulation implant blocking layer 304.
In the embodiment shown in fig. 1, JFET areas include well region 307, JFET gate ohmics contact 308 and channel region 306；
VDMOS areas include well region 307, VDMOS source electrodes 302 and ohmic contact regions 303.Wherein well region 307 is p-well, P+ JFET grid
Pole Ohmic contact 308 is in p-well, and JFET grid is in JFET gate ohmics contact 308.N+ channel region 306 is located at
Between the two adjacent well regions 307 in JFET areas.N+ VDMOS source electrodes 302 and P+ ohmic contact regions 303 are located at the trap in VDMOS areas
In area 307.The both ends of the grid 301 of plane respectively extend to the surface of a VDMOS source electrodes 302.
In the embodiment shown in fig. 1, the well depth of isolation well 305 is more than the well depth of well region 307, ion concentration is less than well region
307 ion concentration.
Further, the implantation concentration of isolation well 305 is 1.5E13cm-2~2.2E13cm-2, well depth be 8.5 microns~
13.5 microns.
Fig. 3 is a kind of traditional integrated JFET VDMOS and above-mentioned integrated depletion type junction field effect transistor device
Breakdown voltage comparison diagram.Abscissa is drain voltage Vd in figure, and ordinate is drain current Id.Traditional breakdown voltage design
It is worth the VDMOS for 600V after JFET is integrated with, breakdown voltage drops to 450V or so, is applied to cause considerable influence,
And the device of above-mentioned integrated depletion type junction field effect transistor, breakdown point are stable, breakdown voltage may remain in 600V.
Fig. 2 is the section of the device of the integrated depletion type junction field effect transistor using trench gate structure in an embodiment
Structural representation.In this embodiment, the grid 401 being located between two adjacent VDMOS source electrodes extends first downward through well region
Conductivity regions.
Embodiment described above only expresses the several embodiments of the present invention, and its description is more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that come for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of device of integrated depletion type junction field effect transistor, the device includes JFET areas, power device area, is located at
The drain electrode of first conduction type at the device back side and led located at the drain electrode towards first on the positive face of the device
The drain electrode and the first conductivity regions, the JFET areas and power are shared by electric class area, the JFET areas and power device area
The intersection of device region is formed with isolation structure, it is characterised in that the isolation structure includes the isolation well of the second conduction type
With the insulation implant blocking layer located at the isolation well surface.
2. the device of integrated depletion type junction field effect transistor according to claim 1, it is characterised in that the insulation
The material of implant blocking layer is silica.
3. the device of integrated depletion type junction field effect transistor according to claim 1, it is characterised in that the JFET
Area and power device area include the well region of the second conduction type, the well depth of the isolation well be more than the well depth of the well region and every
Ion concentration from trap is less than the ion concentration of the well region.
4. the device of integrated depletion type junction field effect transistor according to claim 3, it is characterised in that the isolation
The well depth of trap is 8.5 microns~13.5 microns.
5. the device of integrated depletion type junction field effect transistor according to claim 3, it is characterised in that the device
It is vertical DMOS field-effect transistor VDMOS.
6. the device of integrated depletion type junction field effect transistor according to claim 5, it is characterised in that the power
Device region also includes grid, the VDMOS source electrodes of the first conduction type in the well region in power device area and located at power
The ohmic contact regions of the second conduction type in the well region of device region.
7. the device of integrated depletion type junction field effect transistor according to claim 6, it is characterised in that the grid
For planar gate, the both ends of the grid respectively extend to the surface of a VDMOS source electrodes.
8. the device of integrated depletion type junction field effect transistor according to claim 6, it is characterised in that the grid
For trench gate, the grid being located between two adjacent VDMOS source electrodes extends first conductive-type downward through the well region
Type area.
9. the device of integrated depletion type junction field effect transistor according to claim 3, it is characterised in that the JFET
Area also includes the channel region for the first conduction type being located between the two adjacent well regions.
10. the device of the integrated depletion type junction field effect transistor according to any one in claim 1-9, its feature
It is, first conduction type is N-type, and second conduction type is p-type, and first conductivity regions are N-type extension
Layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610796651.5A CN107785305A (en) | 2016-08-31 | 2016-08-31 | The device of integrated depletion type junction field effect transistor |
| PCT/CN2017/096653 WO2018040871A1 (en) | 2016-08-31 | 2017-08-09 | Device for integrated depletion junction field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610796651.5A CN107785305A (en) | 2016-08-31 | 2016-08-31 | The device of integrated depletion type junction field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107785305A true CN107785305A (en) | 2018-03-09 |
Family
ID=61299994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610796651.5A Pending CN107785305A (en) | 2016-08-31 | 2016-08-31 | The device of integrated depletion type junction field effect transistor |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107785305A (en) |
| WO (1) | WO2018040871A1 (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4325180A (en) * | 1979-02-15 | 1982-04-20 | Texas Instruments Incorporated | Process for monolithic integration of logic, control, and high voltage interface circuitry |
| US6111283A (en) * | 1998-11-13 | 2000-08-29 | United Semiconductor Corp. | Triple well structure |
| US20030168698A1 (en) * | 2002-03-05 | 2003-09-11 | Samsung Electronics Co., Ltd. | Semiconductor devices with multiple isolation structure and methods for fabricating the same |
| CN1866542A (en) * | 2005-05-18 | 2006-11-22 | 崇贸科技股份有限公司 | MOS field effect transistor with isolating structure and making method thereof |
| CN101542697A (en) * | 2006-05-31 | 2009-09-23 | 先进模拟科技公司 | High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same |
| CN102034820A (en) * | 2010-01-28 | 2011-04-27 | 崇贸科技股份有限公司 | Semiconductor device |
| CN103022035A (en) * | 2012-01-20 | 2013-04-03 | 成都芯源系统有限公司 | Integrated circuit and method for manufacturing integrated circuit |
| CN103872137A (en) * | 2014-04-04 | 2014-06-18 | 厦门元顺微电子技术有限公司 | Enhanced type, depletion type and current induction integrated VDMOS power device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7939863B2 (en) * | 2008-08-07 | 2011-05-10 | Texas Instruments Incorporated | Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process |
| US9184237B2 (en) * | 2013-06-25 | 2015-11-10 | Cree, Inc. | Vertical power transistor with built-in gate buffer |
-
2016
- 2016-08-31 CN CN201610796651.5A patent/CN107785305A/en active Pending
-
2017
- 2017-08-09 WO PCT/CN2017/096653 patent/WO2018040871A1/en active Application Filing
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4325180A (en) * | 1979-02-15 | 1982-04-20 | Texas Instruments Incorporated | Process for monolithic integration of logic, control, and high voltage interface circuitry |
| US6111283A (en) * | 1998-11-13 | 2000-08-29 | United Semiconductor Corp. | Triple well structure |
| US20030168698A1 (en) * | 2002-03-05 | 2003-09-11 | Samsung Electronics Co., Ltd. | Semiconductor devices with multiple isolation structure and methods for fabricating the same |
| CN1866542A (en) * | 2005-05-18 | 2006-11-22 | 崇贸科技股份有限公司 | MOS field effect transistor with isolating structure and making method thereof |
| CN101542697A (en) * | 2006-05-31 | 2009-09-23 | 先进模拟科技公司 | High-voltage bipolar-CMOS-DMOS integrated circuit devices and modular methods of forming the same |
| CN102034820A (en) * | 2010-01-28 | 2011-04-27 | 崇贸科技股份有限公司 | Semiconductor device |
| CN103022035A (en) * | 2012-01-20 | 2013-04-03 | 成都芯源系统有限公司 | Integrated circuit and method for manufacturing integrated circuit |
| CN103872137A (en) * | 2014-04-04 | 2014-06-18 | 厦门元顺微电子技术有限公司 | Enhanced type, depletion type and current induction integrated VDMOS power device |
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| Publication number | Publication date |
|---|---|
| WO2018040871A1 (en) | 2018-03-08 |
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