WO2018040871A1 - Device for integrated depletion junction field-effect transistor - Google Patents

Device for integrated depletion junction field-effect transistor Download PDF

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WO2018040871A1
WO2018040871A1 PCT/CN2017/096653 CN2017096653W WO2018040871A1 WO 2018040871 A1 WO2018040871 A1 WO 2018040871A1 CN 2017096653 W CN2017096653 W CN 2017096653W WO 2018040871 A1 WO2018040871 A1 WO 2018040871A1
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region
conductivity type
well
power device
jfet
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PCT/CN2017/096653
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French (fr)
Chinese (zh)
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顾炎
程诗康
张森
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a device for integrating depletion junction field effect transistors.
  • JFET junction-effect transistor
  • the traditional high-voltage integrated JFET has a simpler process, but its isolation from power devices has become a difficult point.
  • the power device is in the normal working state.
  • the current flows to the drain through the longitudinal channel of the power device, and the isolation structure is to prevent the current from flowing to the JFET, that is, to prevent Leakage.
  • the requirement of isolation is that after the JFET device is integrated, the working performance and state of the power device are not affected, that is, the power device is working in the forward direction without leakage, and the breakdown point is fixed and the breakdown voltage is stable when the reverse is depleted.
  • the traditional integrated JFET isolation method is to pull a sufficient distance through the N-epitaxial layer at the junction of the JFET and the power device. As the distance is lengthened, the longer the current path, the less the flow to the JFET region, thereby achieving the effect of shielding leakage.
  • the problem with this method is that the isolation area occupies a large area and increases the area of the integrated chip, resulting in waste, and the compatibility is not high, which brings reliability and other problems.
  • a device for integrating a depletion junction field effect transistor is provided.
  • a device for integrating a depletion junction field effect transistor the device being divided into a JFET region and a power device region, the device comprising: a drain, being a first conductivity type; and a first conductivity type region, disposed at the a drain facing the front side of the device, the JFET region and the power device region sharing the drain and the first conductivity type region; and an isolation structure including an isolation well of a second conductivity type and being disposed in the isolation The insulation of the well surface is implanted into the barrier layer, the first conductivity type and the second conductivity type being opposite.
  • the device for integrating the depletion-type junction field effect transistor is isolated at the junction of the JFET region and the power device region by a deeper isolation type of the second conductivity type, and has a sufficient junction depth when pushing the well. In this way, the leakage path is greatly lengthened, and the isolation effect is good.
  • the lateral distance of the isolation well can be made short, which greatly saves the area of the integrated device.
  • the isolation well can be compatible with junction termination extension technology, that is, the second conductivity type well of the termination region of the power device can be used as an isolation well, which is completed on the basis of the conventional power device process without adding an additional lithographic plate. Increasing the cost of process production is conducive to improving the market competitiveness of products.
  • An insulating injection barrier layer is disposed on the surface of the isolation well to prevent the voltage from being too high to turn on the field tube, and shielding the ion implantation, thereby ensuring good isolation and improving the reliability of the power device.
  • FIG. 1 is a cross-sectional structural view of a device using an integrated depletion junction field effect transistor having a planar gate structure in an embodiment
  • FIG. 2 is a cross-sectional structural view showing a device of an integrated depletion junction field effect transistor using a trench gate structure in an embodiment
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • JFET Junction Field-Effect Transistor
  • VDMOS vertical double-diffused MOSFET
  • the drain 310 is an N+ drain
  • the N-type region 309 is an N- epitaxial layer (in other embodiments, an N-type substrate can also be used directly) as a drift region of the VDMOS.
  • an isolation structure is formed at the junction of the JFET region and the VDMOS region, and the isolation structure includes a P-type isolation well 305 and an insulating injection blocking layer 304 disposed on the surface of the isolation well 305.
  • the device with integrated depletion junction field effect transistor is isolated at the junction of the JFET region and the power device region by a deeper isolation well 305 of the second conductivity type, which achieves sufficient junction depth when pushing the well. Therefore, the leakage path is greatly lengthened and has a good isolation effect.
  • the lateral distance of the isolation well 305 can be made short, which greatly saves the area of the entire integrated device.
  • the isolation well 305 can be compatible with junction termination extension technology, that is, the second conductivity type well of the termination region of the power device can be used as the isolation well 305, which is completed on the basis of the conventional power device process without adding an additional lithography plate. , not to increase the cost of process production, is conducive to improving the market competitiveness of products.
  • An insulating injection blocking layer 304 is disposed on the surface of the isolation well 305 to prevent the voltage from being too high to turn on the field tube while shielding the ion implantation, thereby ensuring good isolation and improving the reliability of the power device.
  • the insulating implant barrier layer 304 is made of silicon dioxide. Specifically, a field oxide layer can be used as the insulating injection blocking layer 304.
  • the JFET region includes a well region 307, a JFET gate ohmic contact 308, and a channel region 306;
  • the VDMOS region includes a well region 307, a VDMOS source 302, and an ohmic contact region 303.
  • the well region 307 is a P well, the P+ JFET gate ohmic contact 308 is disposed in the P well, and the JFET gate is disposed on the JFET gate ohmic contact 308.
  • the channel region 306 of N+ is disposed between two adjacent well regions 307 of the JFET region.
  • N+ VDMOS source 302 and P+ ohmic contact region 303 are provided in well region 307 of the VDMOS region. Both ends of the planar gate 301 extend to the surface of a VDMOS source 302.
  • the well depth of the isolation well 305 is greater than the well depth of the well region 307, and the ion concentration is less than the ion concentration of the well region 307.
  • the isolation well 305 has an implantation concentration of 1.5E13 cm -2 to 2.2 E13 cm -2 and a well depth of 8.5 ⁇ m to 13.5 ⁇ m.
  • Figure 3 is a conventional integrated JFET VDMOS with the above integrated depletion junction field effect A breakdown voltage comparison diagram of a device of a transistor, wherein curve A represents a conventional structure, and curve B represents the device of the above integrated depletion junction field effect transistor, the abscissa is the drain voltage Vd, and the ordinate is the drain current Id.
  • the traditional breakdown voltage design value of 600V VDMOS after the integration of JFET the breakdown voltage drops to about 450V, which has a great impact on its application, and the above-mentioned integrated depletion junction field effect transistor device, breakdown The point is stable and the breakdown voltage can be kept at 600V.
  • FIG. 2 is a cross-sectional structural view of a device of an integrated depletion junction field effect transistor employing a trench gate structure in an embodiment.
  • the gate 401 interposed between the sources of two adjacent VDMOS extends down through the well region to the first conductivity type region.

Abstract

A device for an integrated depletion junction field-effect transistor, comprising a junction field-effect transistor (JFET) region, a power device region, a drain electrode (310) of a first conductivity-type provided on the back-side of a device, and a first conductivity-type region (309) provided on the surface of the drain electrode (310) facing the front of the device, the JFET region and the power device region sharing the drain electrode (310) and the first conductivity-type region (309), an isolation structure being formed at a junction between the JFET region and the power device region, the isolation structure comprising an isolation well (305) of a second conductivity-type and an insulating injection blocking layer (304) provided on the surface of the isolation well (305).

Description

集成耗尽型结型场效应晶体管的器件Device with integrated depletion junction field effect transistor 技术领域Technical field
本发明涉及半导体制造技术，特别是涉及一种集成耗尽型结型场效应晶体管的器件。The present invention relates to semiconductor fabrication techniques, and more particularly to a device for integrating depletion junction field effect transistors.
背景技术Background technique
在高压工艺平台上集成高压结型场效应晶体管(Junction Field-Effect Transistor，JFET)为如今智能功率集成电路领域的一种先进开发与构想，它可以大大提升纵向功率器件的开态性能，以及显著的减小芯片面积，符合当今智能功率器件制造的主流趋势。Integrating a high-voltage junction-effect transistor (JFET) on a high-voltage process platform is an advanced development and concept in the field of smart power ICs, which can greatly improve the on-state performance of vertical power devices, as well as significant The reduction of chip area is in line with the mainstream trend of today's smart power device manufacturing.
传统结构的高压集成JFET有较简单的工艺可以实现，但其与功率器件的隔离成为了一个难点。在工作原理上，要求JFET结束工作处于关断状态下时，功率器件处于开启的正常工作状态，此时电流通过功率器件的纵向沟道流向漏极，隔离结构就是要阻止电流流向JFET，即防止漏电。隔离的要求是在集成了JFET器件后，不影响功率器件的工作性能和状态，即功率器件正向工作同时无漏电，反向耗尽时击穿点固定，击穿电压稳定不变。传统集成JFET的隔离方法是在JFET和功率器件的交界处通过N-外延层拉开足够的距离。随着距离加长，电流途径越长而更少地流向JFET区，从而达到了屏蔽漏电的效果。这种方法的问题是隔离区域占据了大量的面积而加大了整个集成芯片的面积，造成了浪费，同时兼容度不高，会带来可靠性等问题。The traditional high-voltage integrated JFET has a simpler process, but its isolation from power devices has become a difficult point. In the working principle, when the JFET is required to be in the off state, the power device is in the normal working state. At this time, the current flows to the drain through the longitudinal channel of the power device, and the isolation structure is to prevent the current from flowing to the JFET, that is, to prevent Leakage. The requirement of isolation is that after the JFET device is integrated, the working performance and state of the power device are not affected, that is, the power device is working in the forward direction without leakage, and the breakdown point is fixed and the breakdown voltage is stable when the reverse is depleted. The traditional integrated JFET isolation method is to pull a sufficient distance through the N-epitaxial layer at the junction of the JFET and the power device. As the distance is lengthened, the longer the current path, the less the flow to the JFET region, thereby achieving the effect of shielding leakage. The problem with this method is that the isolation area occupies a large area and increases the area of the integrated chip, resulting in waste, and the compatibility is not high, which brings reliability and other problems.
发明内容Summary of the invention
根据本申请的各种实施例，提供一种集成耗尽型结型场效应晶体管的器件。 In accordance with various embodiments of the present application, a device for integrating a depletion junction field effect transistor is provided.
一种集成耗尽型结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：漏极，为第一导电类型；第一导电类型区，设于所述漏极朝向所述器件正面的面上，所述JFET区和功率器件区共享所述漏极和第一导电类型区；及隔离结构，包括第二导电类型的隔离阱和设于所述隔离阱表面的绝缘注入阻挡层，所述第一导电类型和所述第二导电类型相反。A device for integrating a depletion junction field effect transistor, the device being divided into a JFET region and a power device region, the device comprising: a drain, being a first conductivity type; and a first conductivity type region, disposed at the a drain facing the front side of the device, the JFET region and the power device region sharing the drain and the first conductivity type region; and an isolation structure including an isolation well of a second conductivity type and being disposed in the isolation The insulation of the well surface is implanted into the barrier layer, the first conductivity type and the second conductivity type being opposite.
上述集成耗尽型结型场效应晶体管的器件，在JFET区和功率器件区的交界处采用一个较深的第二导电类型的隔离阱进行隔离，在推阱时使其有着足够的结深，这样漏电路径大大加长，起到了良好的隔离效果，该隔离阱的横向距离可以做到很短，大大节约了整个集成器件的面积。该隔离阱可以与结终端扩展技术相兼容，即可利用功率器件的终端区的第二导电类型阱作为隔离阱，在传统的功率器件的工艺基础上完成，无需增加额外的光刻版，不提高工艺生产的成本，有利于提高产品的市场竞争力。在隔离阱的表面设置绝缘注入阻挡层，可以防止电压过高开启场管，同时屏蔽了离子注入，在保证了良好的隔离的同时还提高了功率器件的可靠性。The device for integrating the depletion-type junction field effect transistor is isolated at the junction of the JFET region and the power device region by a deeper isolation type of the second conductivity type, and has a sufficient junction depth when pushing the well. In this way, the leakage path is greatly lengthened, and the isolation effect is good. The lateral distance of the isolation well can be made short, which greatly saves the area of the integrated device. The isolation well can be compatible with junction termination extension technology, that is, the second conductivity type well of the termination region of the power device can be used as an isolation well, which is completed on the basis of the conventional power device process without adding an additional lithographic plate. Increasing the cost of process production is conducive to improving the market competitiveness of products. An insulating injection barrier layer is disposed on the surface of the isolation well to prevent the voltage from being too high to turn on the field tube, and shielding the ion implantation, thereby ensuring good isolation and improving the reliability of the power device.
附图说明DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only the present invention. For some embodiments, those skilled in the art can obtain drawings of other embodiments according to the drawings without any creative work.
图1是一实施例中采用平面栅结构的集成耗尽型结型场效应晶体管的器件的剖面结构示意图；1 is a cross-sectional structural view of a device using an integrated depletion junction field effect transistor having a planar gate structure in an embodiment;
图2是一实施例中采用沟槽栅结构的集成耗尽型结型场效应晶体管的器件的剖面结构示意图；2 is a cross-sectional structural view showing a device of an integrated depletion junction field effect transistor using a trench gate structure in an embodiment;
图3是一种传统的集成JFET的VDMOS与上述集成耗尽型结型场效应晶体管的器件的击穿电压对比图。 3 is a comparison of breakdown voltages of a conventional JFET-integrated VDMOS and the above-described integrated depletion junction field effect transistor device.
具体实施方式detailed description
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。In order to facilitate the understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the invention are given in the drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and comprehensive.
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. The terminology used in the description of the present invention is for the purpose of describing particular embodiments and is not intended to limit the invention. The term "and/or" used herein includes any and all combinations of one or more of the associated listed items.
需要说明的是，当元件被称为“固定于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or the element can be present. When an element is considered to be "connected" to another element, it can be directly connected to the other element or. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like, as used herein, are used for purposes of illustration only.
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。The vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
图1是一实施例中采用平面栅结构的集成耗尽型结型场效应晶体管的器件的剖面结构示意图，在本实施例中，定义N型为第一导电类型，P型为第二导电类型，结型场效应晶体管(Junction Field-Effect Transistor，JFET)集成在垂直双扩散金属氧化物半导体场效应晶体管(Vertical Double-diffused MOSFET，VDMOS)上。如图1中所示，将器件按结构分为JFET区和VDMOS区，JFET区和VDMOS区共享设于器件背面(即图1中朝下的面)的N型的漏极310，和设于漏极310正面(即图1中朝上的面)的N型区309。在 本实施例中，漏极310为N+漏极，N型区309为N-外延层(在其他实施例中也可以直接使用N型衬底)，作为VDMOS的漂移区。在本实施例中，JFET区和VDMOS区的交界处形成有隔离结构，该隔离结构包括P型的隔离阱305和设于隔离阱305表面的绝缘注入阻挡层304。1 is a cross-sectional structural view of a device using an integrated depletion junction field effect transistor having a planar gate structure in an embodiment. In this embodiment, an N type is defined as a first conductivity type, and a P type is a second conductivity type. The Junction Field-Effect Transistor (JFET) is integrated on a vertical double-diffused MOSFET (VDMOS). As shown in FIG. 1, the device is divided into a JFET region and a VDMOS region by structure, and the JFET region and the VDMOS region share an N-type drain 310 provided on the back surface of the device (ie, the face facing downward in FIG. 1), and are disposed on The N-type region 309 of the front side of the drain 310 (i.e., the upward facing surface in Fig. 1). In In this embodiment, the drain 310 is an N+ drain, and the N-type region 309 is an N- epitaxial layer (in other embodiments, an N-type substrate can also be used directly) as a drift region of the VDMOS. In the present embodiment, an isolation structure is formed at the junction of the JFET region and the VDMOS region, and the isolation structure includes a P-type isolation well 305 and an insulating injection blocking layer 304 disposed on the surface of the isolation well 305.
上述集成耗尽型结型场效应晶体管的器件，在JFET区和功率器件区的交界处采用一个较深的第二导电类型的隔离阱305进行隔离，在推阱时使其达到足够的结深，这样漏电路径大大加长，起到了良好的隔离效果。该隔离阱305的横向距离可以做到很短，大大节约了整个集成器件的面积。该隔离阱305可以与结终端扩展技术相兼容，即可利用功率器件的终端区的第二导电类型阱作为隔离阱305，在传统的功率器件的工艺基础上完成，无需增加额外的光刻版，不提高工艺生产的成本，有利于提高产品的市场竞争力。在隔离阱305的表面设置绝缘注入阻挡层304，可以防止电压过高开启场管，同时屏蔽了离子注入，在保证了良好的隔离的同时还提高了功率器件的可靠性。The device with integrated depletion junction field effect transistor is isolated at the junction of the JFET region and the power device region by a deeper isolation well 305 of the second conductivity type, which achieves sufficient junction depth when pushing the well. Therefore, the leakage path is greatly lengthened and has a good isolation effect. The lateral distance of the isolation well 305 can be made short, which greatly saves the area of the entire integrated device. The isolation well 305 can be compatible with junction termination extension technology, that is, the second conductivity type well of the termination region of the power device can be used as the isolation well 305, which is completed on the basis of the conventional power device process without adding an additional lithography plate. , not to increase the cost of process production, is conducive to improving the market competitiveness of products. An insulating injection blocking layer 304 is disposed on the surface of the isolation well 305 to prevent the voltage from being too high to turn on the field tube while shielding the ion implantation, thereby ensuring good isolation and improving the reliability of the power device.
在其中一个实施例中，绝缘注入阻挡层304的材质为二氧化硅。具体可以采用场氧层作为绝缘注入阻挡层304。In one embodiment, the insulating implant barrier layer 304 is made of silicon dioxide. Specifically, a field oxide layer can be used as the insulating injection blocking layer 304.
在图1所示实施例中，JFET区包括阱区307、JFET栅极欧姆接触308以及沟道区306；VDMOS区包括阱区307、VDMOS源极302以及欧姆接触区303。其中阱区307为P阱，P+的JFET栅极欧姆接触308设于P阱内，JFET的栅极设于JFET栅极欧姆接触308上。N+的沟道区306设于JFET区的两相邻阱区307之间。N+的VDMOS源极302和P+的欧姆接触区303设于VDMOS区的阱区307内。平面型的栅极301的两端各延伸至一VDMOS源极302的表面。In the embodiment shown in FIG. 1, the JFET region includes a well region 307, a JFET gate ohmic contact 308, and a channel region 306; the VDMOS region includes a well region 307, a VDMOS source 302, and an ohmic contact region 303. The well region 307 is a P well, the P+ JFET gate ohmic contact 308 is disposed in the P well, and the JFET gate is disposed on the JFET gate ohmic contact 308. The channel region 306 of N+ is disposed between two adjacent well regions 307 of the JFET region. N+ VDMOS source 302 and P+ ohmic contact region 303 are provided in well region 307 of the VDMOS region. Both ends of the planar gate 301 extend to the surface of a VDMOS source 302.
在图1所示实施例中，隔离阱305的阱深大于阱区307的阱深、离子浓度小于阱区307的离子浓度。In the embodiment shown in FIG. 1, the well depth of the isolation well 305 is greater than the well depth of the well region 307, and the ion concentration is less than the ion concentration of the well region 307.
进一步地，隔离阱305的注入浓度为1.5E13cm-2～2.2E13cm-2，阱深为8.5微米～13.5微米。Further, the isolation well 305 has an implantation concentration of 1.5E13 cm -2 to 2.2 E13 cm -2 and a well depth of 8.5 μm to 13.5 μm.
图3是一种传统的集成JFET的VDMOS与上述集成耗尽型结型场效应 晶体管的器件的击穿电压对比图，其中曲线A表示传统结构，曲线B表示上述集成耗尽型结型场效应晶体管的器件，横坐标为漏极电压Vd，纵坐标为漏极电流Id。传统的击穿电压设计值为600V的VDMOS在集成了JFET后，击穿电压下降至450V左右，对其应用造成了较大影响，而上述集成耗尽型结型场效应晶体管的器件，击穿点稳定，击穿电压可以保持在600V。Figure 3 is a conventional integrated JFET VDMOS with the above integrated depletion junction field effect A breakdown voltage comparison diagram of a device of a transistor, wherein curve A represents a conventional structure, and curve B represents the device of the above integrated depletion junction field effect transistor, the abscissa is the drain voltage Vd, and the ordinate is the drain current Id. The traditional breakdown voltage design value of 600V VDMOS after the integration of JFET, the breakdown voltage drops to about 450V, which has a great impact on its application, and the above-mentioned integrated depletion junction field effect transistor device, breakdown The point is stable and the breakdown voltage can be kept at 600V.
图2是一实施例中采用沟槽栅结构的集成耗尽型结型场效应晶体管的器件的剖面结构示意图。在该实施例中，夹设于两相邻VDMOS源极间的栅极401向下贯穿阱区伸至第一导电类型区。2 is a cross-sectional structural view of a device of an integrated depletion junction field effect transistor employing a trench gate structure in an embodiment. In this embodiment, the gate 401 interposed between the sources of two adjacent VDMOS extends down through the well region to the first conductivity type region.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。 The above-described embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (10)

  1. 一种集成耗尽型结型场效应晶体管的器件，所述器件被划分为JFET区和功率器件区，所述器件包括：A device for integrating a depletion junction field effect transistor, the device being divided into a JFET region and a power device region, the device comprising:
    第一导电类型漏极；a first conductivity type drain;
    第一导电类型区，设于所述第一导电类型漏极的正面，所述JFET区和功率器件区共享所述第一导电类型漏极和第一导电类型区；及a first conductivity type region disposed on a front surface of the first conductivity type drain, the JFET region and the power device region sharing the first conductivity type drain and the first conductivity type region;
    隔离结构，包括第二导电类型的隔离阱和设于所述隔离阱表面的绝缘注入阻挡层，所述第一导电类型和所述第二导电类型相反。The isolation structure includes an isolation well of a second conductivity type and an insulation injection barrier layer disposed on a surface of the isolation well, the first conductivity type and the second conductivity type being opposite.
  2. 根据权利要求1所述的器件，其特征在于，所述绝缘注入阻挡层的材质为二氧化硅。The device according to claim 1, wherein the insulating injection blocking layer is made of silicon dioxide.
  3. 根据权利要求1所述的器件，其特征在于，所述JFET区和功率器件区均包括第二导电类型的阱区，所述隔离阱的阱深大于所述阱区的阱深且隔离阱的离子浓度小于所述阱区的离子浓度。The device of claim 1 wherein said JFET region and power device region each comprise a well region of a second conductivity type, said well having a well depth greater than a well depth of said well region and isolating a well The ion concentration is less than the ion concentration of the well region.
  4. 根据权利要求3所述的器件，其特征在于，所述隔离阱的阱深为8.5微米～13.5微米。The device of claim 3 wherein said isolation well has a well depth of between 8.5 microns and 13.5 microns.
  5. 根据权利要求3所述的器件，其特征在于，所述器件是垂直双扩散金属氧化物半导体场效应晶体管。The device of claim 3 wherein said device is a vertical double diffused metal oxide semiconductor field effect transistor.
  6. 根据权利要求5所述的器件，其特征在于，所述功率器件区还包括：The device of claim 5 wherein said power device region further comprises:
    栅极；Gate
    第一导电类型VDMOS源极，设于功率器件区的阱区内；a first conductivity type VDMOS source disposed in the well region of the power device region;
    第二导电类型欧姆接触区，设于功率器件区的阱区内。The second conductivity type ohmic contact region is disposed in the well region of the power device region.
  7. 根据权利要求6所述的器件，其特征在于，所述栅极为平面栅，所述功率器件区包括至少两个所述第一导电类型VDMOS源极，所述栅极的两端各延伸至一第一导电类型VDMOS源极的表面。The device according to claim 6, wherein said gate is a planar gate, said power device region comprises at least two of said first conductivity type VDMOS sources, and said two ends of said gate each extend to a The surface of the first conductivity type VDMOS source.
  8. 根据权利要求6所述的器件，其特征在于，所述栅极为沟槽栅，所述功率器件区包括至少两个所述第一导电类型VDMOS源极，夹设于两相邻第 一导电类型VDMOS源极间的所述栅极向下贯穿所述阱区伸至所述第一导电类型区。The device of claim 6 wherein said gate is a trench gate, said power device region comprising at least two of said first conductivity type VDMOS sources, sandwiched between two adjacent The gate between the source of a conductivity type VDMOS extends down through the well region to the first conductivity type region.
  9. 根据权利要求3所述的器件，其特征在于，所述JFET区包括至少两个所述阱区，还包括设于两相邻所述阱区之间的第一导电类型的沟道区。The device according to claim 3, wherein said JFET region comprises at least two of said well regions, and further comprising a channel region of a first conductivity type disposed between two adjacent said well regions.
  10. 根据权利要求1所述的器件，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型，所述第一导电类型区为N型外延层。 The device according to claim 1, wherein said first conductivity type is N-type, said second conductivity type is P-type, and said first conductivity type region is an N-type epitaxial layer.
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