CN111326578B - Gate drive integrated circuit - Google Patents

Gate drive integrated circuit Download PDF

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Publication number
CN111326578B
CN111326578B CN201811525663.XA CN201811525663A CN111326578B CN 111326578 B CN111326578 B CN 111326578B CN 201811525663 A CN201811525663 A CN 201811525663A CN 111326578 B CN111326578 B CN 111326578B
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integrated circuit
drain
drain region
gate drive
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CN111326578A (en
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杨维成
姚旭红
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Ningbo Semiconductor International Corp
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Ningbo Semiconductor International Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate

Abstract

The invention provides a gate driving integrated circuit. In the gate driving integrated circuit, the transition region is arranged between the second drain region and the first drain region, so that the transition region can be used for dispersing high voltage in a longer distance, and the high voltage is prevented from being applied to the low voltage region, and the voltage resistance of the gate driving integrated circuit is favorably improved.

Description

Gate drive integrated circuit
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gate drive integrated circuit.
Background
The high-voltage gate driving integrated circuit is a product of combining a power electronic device technology and a microelectronic technology and is a key element of mechanical and electrical integration. The high-voltage gate driving integrated circuit has a wide application range, such as electronic ballast, motor driving, dimming, and various power modules.
The high-voltage gate driving integrated circuit generally includes a high-voltage side driving control module, a low-voltage side driving control module, and a level shifting module. The low-voltage side drive control module works under the conventional voltage and serves as a control signal part; the high-voltage side driving control module mainly comprises a high-voltage control signal part; and the level shifting module is used for transmitting the low-voltage side control signal to the high-voltage side drive control module. Therefore, when these functions are implemented, it is generally desirable that the gate driver integrated circuit has a high withstand voltage performance.
Disclosure of Invention
The invention aims to provide a gate drive integrated circuit, which is used for improving the voltage withstanding performance of the conventional gate drive integrated circuit.
To solve the above technical problem, the present invention provides a gate driving integrated circuit, including:
a substrate having an epitaxial layer of a first doping type formed therein;
the field effect transistor comprises a source region of a second doping type, a transition region of the second doping type, a second drain region of the second doping type and a first drain region of the second doping type, which are formed in the epitaxial layer, wherein the transition region is arranged between the second drain region and the first drain region, two ends of the transition region are respectively connected to the second drain region and the first drain region, ion doping concentrations of the second drain region, the transition region and the first drain region are sequentially increased, and the source region is positioned on one side, far away from the transition region, of the second drain region.
Optionally, the gate driving integrated circuit further includes: a first deep buried region of a second doping type, the first drain region being formed in the first deep buried region.
Optionally, an end of the transition region close to the first drain region is connected to the first deep buried region.
Optionally, the gate driving integrated circuit further includes: a first buffer region of a second doping type, the first buffer region being formed in the first deep buried region, the first drain region being formed in the first buffer region, and an ion doping concentration of the first buffer region being between an ion doping concentration of the first drain region and an ion doping concentration of the first deep buried region.
Optionally, an end of the transition region close to the first drain region extends to the first buffer region to connect with the first buffer region, and an ion doping concentration of the first buffer region is between an ion doping concentration of the first drain region and an ion doping concentration of the transition region.
Optionally, the gate driving integrated circuit further includes:
a first connection region of a second doping type and a second connection region of a second doping type, the first connection region being arranged on a side of the source region close to the transition region, the second connection region being arranged on a side of the source region far from the transition region;
and the second deep buried region of the second doping type is positioned below the source region and is arranged at an interval with the source region, and two end parts of the second deep buried region along the direction from the source region to the transition region are also respectively connected with the first connecting region and the second connecting region.
Optionally, an end of the transition region near the second drain region is connected to the first connection region, and the first connection region is further connected to the second drain region.
Optionally, an inversion buried region of the first doping type is formed in the second deep buried region, and the inversion buried region extends from an upper boundary of the second deep buried region close to the source region to an inside of the second deep buried region.
Optionally, the inversion buried region further extends laterally from a middle region of the second deep buried region to the first connection region and the second connection region.
Optionally, the gate driving integrated circuit further includes: a first contact region of a first doping type located between the second connection region and the source region.
Optionally, the gate driving integrated circuit further includes: a second contact region of the first doping type located on a side of the second connection region remote from the source region.
Optionally, the gate driving integrated circuit further includes: a first field plate structure formed on a surface of the substrate and on a side of the second connection region remote from the source region.
Optionally, the second field plate structure includes a field dielectric layer and a field conductive layer, the field dielectric layer is formed on the substrate, and the field conductive layer is formed on the field dielectric layer.
Optionally, the substrate includes a base layer of the first doping type and an epitaxial layer of the first doping type formed on the base layer, the base layer and the epitaxial layer together form the doping layer, and the first deep buried region extends from the epitaxial layer into the base layer.
Optionally, the withstand voltage of the first drain region is 200V to 700V, and the withstand voltage of the second drain region is 5V to 30V.
Optionally, the gate driving integrated circuit is a level shift circuit.
Optionally, the first doping type is P-type, and the second doping type is N-type.
In the gate drive integrated circuit provided by the invention, the source region, the second drain region and the first drain region are all formed in the doped layer, and a transition region is also arranged between the first drain region and the second drain region. By providing the transition region, the distance between the high-voltage region corresponding to the first drain region and the low-voltage region corresponding to the second drain region can be increased, so that when the first drain region is connected to a high voltage, on the one hand, the high voltage can be dispersed over a longer distance along with the transition region; on the other hand, a PN junction formed by an interface between the transition region and the doped layer is in contact with the doped layer, and can realize depletion layer expansion under reverse voltage for bearing high voltage so as to improve the voltage resistance of the device.
Drawings
Fig. 1 is a schematic structural diagram of a gate driving integrated circuit according to a first embodiment of the invention;
fig. 2 is a schematic distribution diagram of PN junctions of the gate driver ic according to the first embodiment of the invention.
Wherein the reference numbers are as follows:
100-a substrate;
110P-a base layer; a 120P-epitaxial layer;
200D-a first drain region;
210N-a first deep buried region; 220N-first buffer;
200S-source region; 200B — a first contact zone;
200G-a gate structure;
210P-first field plate structure; 220P — second field plate structure;
a 300N-transition region;
400N-second drain region;
500N-a second deep buried region;
610N-first connection region; 620N-a second connecting region;
621N-second buffer.
700P-second contact area;
800P-inversion buried region;
900 GND-ground port; 900S-source signal port;
900G-gate signal port; 900D-drain signal port.
Detailed Description
The gate driving integrated circuit according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a schematic structural diagram of a gate driver integrated circuit according to a first embodiment of the present invention, and as shown in fig. 1, the gate driver integrated circuit includes a substrate 100 and a field effect transistor.
A doped layer PW of a first doping type is formed in the substrate 100. And the field effect transistor includes a source region 200S of the second doping type, a transition region 300N of the second doping type, a second drain region 400N of the second doping type, and a first drain region 200D of the second doping type formed in the doping layer. The transition region 300N is spaced between the second drain region 400N and the first drain region 200D, two end portions of the transition region 300N are respectively connected to the second drain region 400N and the first drain region 200D, ion doping concentrations of the second drain region 400N, the transition region 300N and the first drain region 200D are sequentially increased, and the source region 200S is located on one side of the second drain region 400N, which is far away from the transition region 300N.
With continued reference to fig. 1, the field effect transistor further comprises: a gate structure 200G, wherein the gate structure 200G is formed on the surface of the substrate 100 and is located between the source region 200S and the second drain region 400N. The gate structure 200G is used to control the current flowing from the source region 200S to the first drain region 200D.
Wherein the end of the second drain region 400N near the gate structure extends to below the gate structure 200G. When a gate signal is applied to the gate structure 200G to turn on the field effect transistor, a channel region is formed under the gate structure 200G and corresponding to the inversion of the doped layer PW between the source region 200S and the second drain region 400N, and a current flow path between the source region 200S and the first drain region 200D is, for example: the channel region, the second drain region 400N, and the transition region 300N are sequentially formed from the source region 200S to the first drain region 200D.
And when a high voltage is applied to the first drain region 200D, the distance between the first drain region 200D and the second drain region 400N is increased due to the transition region 300N disposed between the first drain region 200D and the second drain region 400N, so that the high voltage can be dispersed to a longer distance, the voltage near the second drain region 400N is weakened, the high voltage is prevented from being applied to the low voltage region corresponding to the second drain region, and thus the problem that the low voltage region is broken down can be prevented. In addition, since the ion doping concentration of the transition region 300N is lower than that of the first drain region 200D, the transition region 300N has a relatively large resistance, and thus can bear a relatively high voltage and realize the function of resistance voltage division.
It should be further noted that the ion doping concentration of the second drain region 400N is lower than that of the transition region 300N, that is, the second drain region 400N is a lightly doped region, so that the hot carrier effect of the field effect transistor can be further alleviated.
Specifically, the first drain region 200D is connected to the drain signal port 900D, and the source region 200S is connected to the source signal port 900S. And the withstand voltage of the first drain region 200D is higher than that of the second drain region 400N, for example, the withstand voltage of the first drain region 200D is 200V to 700V, and the withstand voltage of the second drain region 400N is 5V to 30V. It can be considered that a side of the transition region 300N adjacent to the first drain region 200D is defined as a high voltage region, and a side of the transition region 300N adjacent to the second drain region 400N is defined as a low voltage region, i.e., the transition region 300N is a transition region connecting the high voltage region and the low voltage region.
That is, by providing the transition region 300N, the distance between the high voltage region and the low voltage region is increased, so that the high voltage can be dispersed over a long distance, so that the voltage near the low voltage region is weakened, the high voltage is prevented from being applied to the low voltage region, and thus the problem that the low voltage region is broken down can be prevented.
Preferably, the transition region 300N has a larger length relative to the first drain region 200D, so that a larger distance can be formed between the high voltage region and the low voltage region. The length of the transition region 300N in the direction from the first drain region 200D to the second drain region 400N is, for example, 30 μm to 80 μm.
Fig. 2 is a schematic diagram illustrating distribution of PN junctions of the gate driver ic according to an embodiment of the invention. As shown in fig. 2, a first PN junction PN1 is formed at the interface between the transition region 300N of the second doping type and the doped layer PW of the first doping type. When a high voltage is applied to the first drain region 200D, the transition region 300N has a relatively high voltage with respect to the doped layer PW, which is equivalent to applying a reverse voltage to the first PN junction PN1 to expand the depletion layer of the first PN junction PN1, so that the first PN junction PN can be used to withstand a relatively high voltage. That is, the transition region 300N serves to disperse a high voltage over a long distance on the one hand, and also to realize a depletion layer expansion to further withstand the high voltage in the case of applying the high voltage on the other hand.
It can be considered that in the present embodiment, the low voltage region has a MOS region therein, the source region 200S, the gate structure 200G and the second drain region 400N are all formed in the MOS region, and the current between the source region 200S and the first drain region 200D passes through the second drain region 400N and further passes through the transition region 300N, so that the transition region 300N also serves as a MOS region connected to the line of the high voltage region.
With continued reference to fig. 1, in this embodiment, the substrate 100 includes a base layer 110P of the first doping type and an epitaxial layer 120P of the first doping type formed on the base layer 110P, and the base layer 110P and the epitaxial layer 120P together form the doping layer PW. The source region 200S, the transition region 300N, the second drain region 400N, and the first drain region 200D are all formed in the epitaxial layer 120P.
The ion doping concentration of the epitaxial layer 120P is higher than that of the substrate layer 110P, so that the part of the epitaxial layer 120P for forming the channel region of the field effect transistor is not inverted under a low voltage to cause the problem of false conduction of the field effect transistor, and the conduction performance of the field effect transistor is ensured. For example, the resistivity of the base layer 110P may be made, for example, between 50 ohm-100 ohm-cm; and, the epitaxial layer 120P may be a boron doped epitaxial layer, for example, having a thickness of 5 μm to 8 μm and a resistivity of, for example, 20 ohm-70 ohm.
It should be appreciated that the first doping type and the second doping type are opposite doping types, e.g., the first doping type is N-type, then the second doping type is P-type; or, the first doping type is P-type, and the second doping type is N-type.
In this embodiment, the first doping type is P-type and the second doping type is N-type. In this embodiment, the doped layer PW is P-type, and an N-type field effect transistor is formed in the P-type doped layer. Specifically, the second drain region 400N of the second doping type is an N-type doping region, such as a phosphorus doping region.
With continued reference to fig. 1, the gate driver ic further comprises: a first deep buried region 210N of the second doping type is formed in the doping layer PW, and the first drain region 200D is formed in the first deep buried region 210N. That is, the first deep buried region 210N extends to a position below the first drain region 200D and is electrically connected to the first drain region 200D, so as to improve the voltage endurance of the high voltage region, thereby realizing the high voltage endurance of the field effect transistor. In the present embodiment, the first deep buried region 210N of the second doping type is an N-type doped region, such as a phosphorus doped region. At this time, the end of the transition region 300N close to the first drain region 200D may be connected to the first deep buried region 210N, so that the end of the transition region 300N close to the first drain region 200D is connected to the first drain region 200D.
As described with reference to fig. 2, the second PN junction PN2 is formed by the interface between the first deep buried region 210N of the second doping type and the doped layer PW of the first doping type. At this time, since the first deep buried region 210N is extended to a deeper position of the substrate relative to the first drain region 200D, which is equivalent to the second PN junction PN2 being extended to a deeper position of the substrate, the junction depth of the PN junction in the high voltage region is increased, so that the PN junction in the high voltage region can bear a larger breakdown voltage.
Specifically, as the junction depth corresponding to the first drain region position increases, the interface of the PN junction corresponding to the first drain region position extends further into the substrate. In other words, when the first deep buried region is not provided, the junction depth corresponding to the first drain region is, for example, a bottom boundary of a PN junction formed by the first drain region 200P and the doping layer PW; when the first deep buried region 210N is provided, the junction depth corresponding to the first drain region is the bottom boundary of the PN junction formed by the first deep buried region 210N and the doped layer PW. That is, the first deep buried region 210N is provided so that the junction depth with the doped layer PW at the first drain position is further reduced from the bottom position of the first drain 200D to the bottom position of the first deep buried region 210N.
It should be noted that, since the interface of the PN junction corresponding to the first drain region extends to a deeper position of the substrate, the surface area of the PN junction can be effectively increased, and the depletion layer with a larger area can be expanded, so that the voltage withstanding performance of the first drain region can be improved. Therefore, under the protection of the first deep buried region 210N, it is beneficial to protect the first drain region 200D and prevent the first drain region 200D from being broken down.
In this embodiment, the first drain region 200D, the source region 200S and the transition region 300N are all formed in the epitaxial layer 120P, the first deep buried region 210N is partially formed in the epitaxial layer 120P to be electrically connected to the first drain region 200D, and the bottom of the first deep buried region 210N further extends into the substrate layer 110P. As described above, since the base layer 110P is of the first doping type, the first deep buried region 210N may be allowed to extend and extend further into the base layer 110P, so that the first deep buried region 210N and the doped layer PW in the base layer 110P can also form a PN junction.
When a high voltage is applied to the first drain region 200D, the first deep buried region 210N can be further utilized to bear the high voltage, so as to avoid the voltage concentration in the first drain region 200D, and the depletion layer expansion can be realized by the second PN junction PN2 formed by the first deep buried region 210N and the doped layer PW under a reverse bias. As described above, the first deep buried layer 210N is extended into a deeper position of the substrate 100, not only the junction depth of the PN junction of the high voltage region can be increased, but also the area of the depletion layer formed can be increased, so that the withstand voltage performance of the high voltage region can be greatly improved.
Wherein the ion doping concentration of the first deep buried region 210N is lower than that of the first drain region 200D.
Optionally, the gate driving integrated circuit further includes: a first buffer region 220N of a second doping type, wherein the first buffer region 220N is formed in the first deep buried region 210N, the first drain region 200D is formed in the first buffer region 220N, and an ion doping concentration of the first buffer region 220N is between an ion doping concentration of the first drain region 200D and an ion doping concentration of the first deep buried region 210N. That is, the first buffer region 220N is located between the first drain region 200D and the first deep buried region 210N, and the ion doping concentrations of the first drain region 200D, the first buffer region 220N and the first deep buried region 210N are sequentially decreased, so that a large difference in ion doping concentration generated when the first drain region 200D directly reaches the first deep buried region 210N is avoided.
It should be appreciated that, in this embodiment, by providing the first buffer region 220N, the first buffer region 220N partially overlaps the first drain region 200D, and the first buffer region 220N also partially overlaps the first deep buried region 210N, so that the first deep buried region 210N and the first drain region 200D are indirectly electrically connected through the first buffer region 220N.
In this embodiment, an end portion of the transition region 300N near the first drain region 200D may further extend to the first buffer region 220N to be connected to the first buffer region 220N. As described above, the first drain region 200D is formed in the first buffer region 220N, and the end of the transition region 300N near the first drain region 200D is indirectly connected to the first drain region 200D through the first buffer region 220N.
In addition, the first buffer region 220N is spaced between the first drain region 200D and the transition region 300N, and the ion doping concentration of the first buffer region 220N may be further between that of the first drain region 200D and that of the transition region 300N. Similarly, the ion doping concentrations of the first drain region 200D, the first buffer region 220N and the transition region 300N are sequentially decreased in a gradient manner, so as to avoid the problem of too large difference in ion doping concentrations when the first drain region 200D is directly connected to the transition region 300N.
With continued reference to fig. 1, the gate driver integrated circuit further includes a second field plate structure 220P, wherein the second field plate structure 220P is formed on the surface of the substrate 100 and is located at an end of the transition region 300N near the gate structure 300G. The second field plate structure 220P can be used to invert the substrate region beneath it to form an inversion layer.
Specifically, when a high voltage is applied to the first drain region 200S, the transition region 300N is correspondingly set to have a higher voltage, that is, the high voltage is distributed over the transition region 300N, and the voltage of the portion of the transition region 300N close to the first drain region 200D is higher, and the voltage of the portion of the transition region 300N close to the second drain region 400N is relatively lower. At this time, the second field plate structure 220P is used to invert the portion of the transition region 300N near the second drain region 400N (i.e., the portion of the transition region 300N under the second field plate structure 220P), so that the inversion region can be used to further isolate the voltage, thereby preventing the higher voltage from being further applied in the low voltage region.
In this embodiment, the second field plate structure 220P includes a field dielectric layer and a field conductive layer, the field dielectric layer is formed on the substrate, and the field conductive layer is formed on the field dielectric layer. Further, the second field plate structure 220P is, for example, a ring-shaped structure, and surrounds the second drain region 400N and a portion of the transition region 300N. Further, the second field plate structure 220P is an annular structure, and a center of the second field plate structure 220P coincides with the second drain region 400N.
Further, the second field plate structure 220P and the gate structure 200G can be connected to the same signal port (e.g., both connected to gate signal port 900G). When a gate signal port 900G inputs a start signal of the field effect transistor, the gate structure 200G controls the inversion of the first doping type doping layer PW therebelow to form a conductive channel; when a high voltage is applied to the first drain region 200D, an inversion-on signal is input through the gate signal port 900G, so that the second field plate structure 220P controls the inversion of the second doping type transition region 300N thereunder, thereby playing a role of isolating the high voltage.
Referring to fig. 1 with emphasis, the gate driving integrated circuit further includes: and a second deep buried region 500N of a second doping type formed in the doping layer PW, wherein the second deep buried region 500N is disposed below the source region 200S and spaced apart from the source region 200S. The end of the second deep buried region 500N close to the second drain region 400N further extends to the lower side of the second drain region 400N, and one end of the second deep buried region 500N far from the second drain region 400N extends to one side of the source region 200S far from the gate structure 200G in the direction far from the second drain region 400N.
It is considered that the second deep buried region 500N is located under the source region 200S and the gate structure 200G, and a lateral length dimension of the second deep buried region 500N is equal to or greater than a lateral length dimension of the source region 200S to the second drain region 400N, so that the source region 200S and the doped layer PW under the second deep buried region can be separated from each other by the second deep buried region 500N at a position spaced apart from the source region 200S by a predetermined distance.
In this embodiment, the second deep buried region 500N is partially formed in the epitaxial layer 120P and further extends into the substrate layer 110P, so that the second deep buried region 500N is buried in a deeper position and is spaced apart from the source region 200S. The second deep buried region 500N may be formed by, for example, arsenic doping, and the second deep buried region 500N may have a larger ion doping concentration (for example, the ion doping concentration of the second deep buried region 500N is greater than that of the transition region 300N), so that a PN junction isolation structure with better isolation performance may be formed between the second deep buried region 500N and the doping layer PW based on the larger ion doping concentration.
And, the gate drive integrated circuit further comprises: a first connection region 610N of a second doping type and a second connection region 620N of a second doping type are formed in the doped layer PW, the first connection region 610N is disposed at a side of the source region 200S close to the transition region, and the second connection region 620N is disposed at a side of the source region 200S far from the transition region. In this embodiment, the first connection region 610N is disposed on a side of the gate structure 200G away from the source region 200S, and the second connection region 620N is disposed on a side of the source region 200S away from the gate structure 200G. The first connection region 610N and the second connection region 620N are both extended from the surface of the substrate 100 to the inside of the substrate 100, so that the bottom of the first connection region 610N is connected to the end of the second deep buried region 500N close to the second drain region, and the bottom of the second connection region 620N is connected to the end of the second deep buried region 500N far from the second drain region. That is, both ends of the second deep buried region 500N in the source region to transition region direction connect the first connection region 610N and the second connection region 620N, respectively. Thus, a MOS region is surrounded by the first connection region 610N, the second deep buried region 500N and the second connection region 620N.
It should be noted that, by combining the second deep buried region 500N, the first connection region 610N and the second connection region 620N, the MOS region and the high voltage region can be separated from each other, so that when a high voltage is applied to the first drain region 200D, it is possible to further ensure that the high voltage is not applied to the MOS region of the low voltage region based on the separation of the first connection region 610N, the second deep buried region 500N and the second connection region 620N, so as to prevent the MOS region from being broken down.
In this embodiment, the side boundary of the first connection region 610N close to the transition region wraps the side boundary of the second drain region 400N close to the transition region, so that the second drain region 400N is wrapped in the MOS region, wherein the first connection region 610N and the second connection region 620N are used for sealing the side edges of the MOS region, and the second deep buried region 500N is used for sealing the bottom edge of the MOS region.
Further, the first connection region 610N may be extended to the lower side of the second drain region 400N to cover a portion of the bottom boundary of the second drain region 400N. And the side boundary of the first connection region 610N far from the transition region does not cover the side boundary of the second drain region 400N far from the transition region, so that the boundary of the second drain region 400N close to the channel region is exposed in the MOS region, and is used for ensuring the conduction performance of the field effect transistor.
With continued reference to fig. 1, in this embodiment, the end of the transition region 300N near the second drain region is further connected to the first connection region 610N, and the first connection region 610N is further connected to the second drain region 400N, that is, the end of the transition region 300N near the second drain region 400N is connected to the second drain region 400N through the first connection region 610N. It should be appreciated that the second drain region 400N, the transition region 300N, the first connection region 610N, and the second deep buried region 500N are connected to each other at this time. As described above, the transition region 300N is connected to the first drain region 200D, so that the second deep buried region 500N, the first connection region 610N and the second connection region 620N are electrically connected to the first drain region 200D.
Referring to fig. 2, an interface between the first connection region 610N and the doped layer PW may form a third PN junction PN3, an interface between the second deep buried region 500N and the doped layer PW may form a fourth PN junction PN4, and an interface between the second connection region 620N and the doped layer PW may form a fifth PN junction PN 5.
When a high voltage is applied to the first drain region 200D, the high voltage is further shared among the first connection region 610N, the second deep buried region 500N, and the second connection region 620N, so that the first connection region 610N, the second deep buried region 500N, and the second connection region 620N have a higher voltage, and at this time, the third PN junction PN3, the fourth PN junction PN4, and the fifth PN junction PN5 are all depleted to form a depletion layer; certainly, at this time, the first PN junction PN1 and the second PN junction PN2 are also depleted, and the depletion layer corresponding to the first PN junction PN1, the depletion layer corresponding to the second PN junction PN2, the depletion layer corresponding to the third PN junction PN3, the depletion layer corresponding to the fourth PN junction PN4, and the depletion layer corresponding to the fifth PN junction PN5 can punch through each other, so that not only the area of the depletion layer in the doping layer PW is increased, but also the depletion layers based on the mutual punch-through are surrounded on the outer periphery of the MOS region, so that the high-voltage region and the MOS region can be completely pinched off, a function of isolating the high voltage is achieved, and the MOS region can be effectively prevented from being broken down.
In addition, in this embodiment, the ion doping concentration of the first connection region 610N may be further higher than the ion doping concentration of the second drain region 400N and lower than the ion doping concentration of the transition region 300N, so that the ion doping concentrations among the second drain region 400N, the first connection region 610N and the transition region 300N are distributed in a gradient manner.
With continued reference to fig. 1, the gate driver ic further comprises: a first field plate structure 210P formed on the surface of the substrate 100 on a side of the second connection region 620N remote from the source region 200S and may enable the first field plate structure 210P to be connected to, for example, a ground port 900 GND. By providing the first field plate structure 210P, it is possible to control the electric field attenuation in the substrate region therebelow, and in particular, to modulate the electric field at the corner positions of the second connection region 620N and the doped layer PW, so as to alleviate the phenomenon that the electric field is easily concentrated at the corner positions.
With continued reference to fig. 1, the gate driver ic further comprises: a second buffer region 621N of a second doping type formed in the doped layer PW, wherein the second buffer region 621N extends longitudinally from the surface of the substrate toward the inside of the substrate, and a portion of the second buffer region 621N is formed in the second connection region 620N and further extends laterally into the doped layer PW in a direction away from the source region 200S, that is, the second buffer region 621N extends to a corner connection point of the doped layer PW and the second connection region 620N. In this embodiment, the second buffer region 621N laterally extends to below the first field plate structure 210P in a direction away from the source region 200S.
The ion doping concentration of the second buffer region 621N is lower than that of the second connection region 620N, so that the ion concentration difference between the second connection region 620N and the doping layer PW can be effectively alleviated based on the second buffer region 621N with a lower ion concentration, and the problem of electric field concentration at the corner is further improved.
Further, the gate driver integrated circuit further includes: a first contact region 200B of a first doping type formed in the doped layer PW, the first contact region 200B being located between the second connection region 620N and the source region 200S. That is, the first contact region 200B is surrounded in the MOS region by the first connection region 610N, the second deep buried region 500N, and the second connection region 620N, so that the voltage of the MOS region surrounded by the first connection region 610N, the second deep buried region 500N, and the second connection region 620N is controlled by the first contact region 200B.
Further, the first contact region 200B and the source region 200S are connected to the same signal port (e.g., both connected to a source signal port 900S). In this way, the doped layer PW in the source region 200S and the MOS region can be maintained at the same voltage value, so that when the field effect transistor is turned on, the leakage current from the source region 300S to the doped layer PW can be avoided.
Referring to fig. 1 again, the gate driver ic further includes: a second contact region 700P of the first doping type formed in the doped layer PW, the second contact region 700P being located at a side of the second connection region 620N away from the source region 200S, such that the first contact region 200B and the second contact region 700P are separated from each other by the second connection region 620N. The second contact region 700P may be used to control the substrate voltage excluding the MOS region in the first doping type doped layer PW, and the second contact region 700P may be further connected to a signal port with a low voltage, for example, the second contact region 700P is connected to the ground port 900 GND. In this embodiment, the second contact region 700P and the first field plate structure 210P may be connected to the same ground port 900 GND.
As shown in fig. 2, when a high voltage is applied to the first drain region 200D, at this time, the transition region 300N, the first deep buried region 210N, the first connection region 610N, the second deep buried region 500N and the second connection region 620N have a high voltage correspondingly, and a low voltage is applied to the second contact region 700P, at this time, the doped layer PW with the first doping type outside the MOS region has a low voltage correspondingly, so that the first PN junction PN1, the second PN junction PN2, the third PN junction PN3, the fourth PN junction PN4 and the fifth PN junction PN5 are all depleted to withstand the high voltage.
It can be seen that, by providing the first connection region 610N, the second deep-buried region 500N and the second connection region 620N to separate the doped layer in the MOS region from the doped layer outside the MOS region, the first contact region 200B and the second contact region 700P can be used to control the voltages of the doped layers outside the MOS region and the MOS region, respectively, so as to avoid the voltages of the doped layers outside the MOS region and the MOS region from interfering with each other.
In an alternative embodiment, an inversion buried region 800P of the first doping type is formed in the second deep buried region 500N, and the inversion buried region 800P extends from an upper boundary of the second deep buried region 500N near the source region 200S to an inside of the second deep buried region 500N.
At this time, the inversion buried region 800P and the doped layer PW of the MOS region are connected to each other, and the inversion buried region 800P does not extend out of the MOS region, which corresponds to an increase in the area of the doped layer in the MOS region. Further, the inversion buried region 800P may be provided right below the source region 200S, so that the distance from the source region 200S of the second doping type to the second deep buried region 500N of the second doping type may be lengthened, and the problem that the doped layer PW between the source region 200S and the second deep buried region 500N is easily broken down due to the fact that the distance from the source region 200S to the second deep buried region 500N is too small is avoided.
Alternatively, the inversion buried region 800P may be laterally extended from the middle region of the second deep buried region 500N to the first connection region 610N and the second connection region 620N. That is, the second deep buried region 500N may be formed with the inversion buried region 800P toward the entire upper boundary of the MOS region to increase the doped layer area in the MOS region.
In summary, in the gate driving integrated circuit provided by the present invention, since the transition region is disposed between the second drain region and the first drain region, the transition region can be used to withstand a high voltage, and the high voltage can be dispersed over a long distance, thereby preventing the high voltage from being applied to the low voltage region. Furthermore, a first deep buried region can be arranged below the first drain region, so that the junction depth of the PN junction in the high-voltage region can be increased, the first deep buried region can be further utilized to bear high voltage, and the depletion layer of the PN junction corresponding to the first deep buried region and the depletion layer of the PN junction corresponding to the transition region can be mutually penetrated, so that the high-voltage resistance of the gate drive integrated circuit can be greatly improved.
Further, in the gate driving integrated circuit provided by the invention, a second deep buried region, a first connection region and a second connection region may be further provided to surround the MOS region, and the substrate regions corresponding to the source region and the gate structure are all surrounded in the MOS region. Therefore, the MOS region and the region outside the MOS region are separated from each other, and when a high voltage is applied to the first drain region, depletion layers of PN junctions corresponding to the first connection region, the second connection region and the second deep buried region can penetrate through each other and surround the MOS region to resist the high voltage. Specifically, the gate driving integrated circuit provided by the invention can bear a voltage of 200V-700V, for example.
The gate driving integrated circuit is, for example, a level shift circuit, and the level shift circuit is used for transmitting a low-voltage control signal of the control circuit to the high-voltage driving circuit. Therefore, the level shift circuit generally needs to be connected to the high voltage driving circuit, and the level shift circuit in this embodiment has high voltage endurance, so that the level shift circuit can be prevented from being broken down.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (18)

1. A gate drive integrated circuit, comprising:
a substrate having a first doping type doping layer formed therein;
the field effect transistor comprises a source region of a second doping type, a transition region of the second doping type, a first drain region of the second doping type and a second drain region of the second doping type, which are formed in the doping layer, wherein the transition region is arranged between the second drain region and the first drain region, two ends of the transition region are respectively connected to the second drain region and the first drain region, ion doping concentrations of the second drain region, the transition region and the first drain region are sequentially increased, and the source region is positioned on one side, away from the transition region, of the second drain region;
a first connection region of a second doping type and a second connection region of a second doping type, the first connection region being arranged on a side of the source region close to the transition region, the second connection region being arranged on a side of the source region far from the transition region; and the number of the first and second groups,
and the second deep buried region of the second doping type is positioned below the source region and is arranged at an interval with the source region, and two end parts of the second deep buried region along the direction from the source region to the transition region are also respectively connected with the first connecting region and the second connecting region.
2. The gate drive integrated circuit of claim 1, further comprising: a first deep buried region of a second doping type, the first drain region being formed in the first deep buried region.
3. The gate drive integrated circuit of claim 2, wherein an end of the transition region proximate to the first drain region is connected to the first deep buried region.
4. The gate drive integrated circuit of claim 2, further comprising:
a first buffer region of a second doping type, the first buffer region being formed in the first deep buried region, the first drain region being formed in the first buffer region, and an ion doping concentration of the first buffer region being between an ion doping concentration of the first drain region and an ion doping concentration of the first deep buried region.
5. The gate drive integrated circuit of claim 4, wherein an end of the transition region near the first drain region extends to the first buffer region to connect with the first buffer region, and an ion doping concentration of the first buffer region is between an ion doping concentration of the first drain region and an ion doping concentration of the transition region.
6. The gate drive integrated circuit of claim 1, wherein an end of the transition region proximate to the second drain region is connected to the first connection region, and the first connection region is further connected to the second drain region.
7. The gate drive integrated circuit of claim 1, wherein an inversion buried region of the first doping type is formed in the second deep buried region, the inversion buried region extending from an upper boundary of the second deep buried region near the source region to an interior of the second deep buried region.
8. The gate drive integrated circuit of claim 7, wherein the inversion buried region further extends laterally from a middle region of the second deep buried region to the first connection region and the second connection region.
9. The gate drive integrated circuit of claim 1, further comprising:
a first contact region of a first doping type located between the second connection region and the source region.
10. The gate drive integrated circuit of claim 1, further comprising:
a second contact region of the first doping type located on a side of the second connection region remote from the source region.
11. The gate drive integrated circuit of claim 1, further comprising:
a first field plate structure formed on a surface of the substrate and on a side of the second connection region remote from the source region.
12. The gate drive integrated circuit of claim 1, wherein the field effect transistor further comprises:
and the gate structure is formed on the surface of the substrate and is positioned between the source region and the second drain region.
13. The gate drive integrated circuit of claim 1, further comprising:
and the second field plate structure is formed on the surface of the substrate and is positioned on the end part of the transition region close to the second drain region.
14. The gate drive integrated circuit of claim 13, wherein the second field plate structure comprises a field dielectric layer formed on the substrate and a field conductive layer formed on the field dielectric layer.
15. The gate drive integrated circuit of claim 1, wherein the substrate comprises a base layer of the first doping type and an epitaxial layer of the first doping type formed on the base layer, the base layer and the epitaxial layer together constituting the doped layer, and the second deep buried region extends from the epitaxial layer into the base layer.
16. The gate driving integrated circuit according to claim 1, wherein the first drain region has a withstand voltage of 200V to 700V, and the second drain region has a withstand voltage of 5V to 30V.
17. The gate drive integrated circuit of claim 1, wherein the gate drive integrated circuit is a level shifting circuit.
18. The gate drive integrated circuit of any of claims 1 to 17, wherein the first doping type is P-type and the second doping type is N-type.
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