CN103606562B - Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer - Google Patents
Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer Download PDFInfo
- Publication number
- CN103606562B CN103606562B CN201310395509.6A CN201310395509A CN103606562B CN 103606562 B CN103606562 B CN 103606562B CN 201310395509 A CN201310395509 A CN 201310395509A CN 103606562 B CN103606562 B CN 103606562B
- Authority
- CN
- China
- Prior art keywords
- silicon
- layer
- buried layer
- type
- length
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010703 silicon Substances 0.000 title claims abstract description 179
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 179
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 177
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 34
- 239000001301 oxygen Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- 239000002210 silicon-based material Substances 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 45
- 230000005684 electric field Effects 0.000 abstract description 24
- 230000000694 effects Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VCUFZILGIRCDQQ-KRWDZBQOSA-N N-[[(5S)-2-oxo-3-(2-oxo-3H-1,3-benzoxazol-6-yl)-1,3-oxazolidin-5-yl]methyl]-2-[[3-(trifluoromethoxy)phenyl]methylamino]pyrimidine-5-carboxamide Chemical compound O=C1O[C@H](CN1C1=CC2=C(NC(O2)=O)C=C1)CNC(=O)C=1C=NC(=NC=1)NCC1=CC(=CC=C1)OC(F)(F)F VCUFZILGIRCDQQ-KRWDZBQOSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000003100 immobilizing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
Abstract
The invention discloses silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer, described transistor arrangement contains a substrate layer the most successively；A part of oxide layer, wherein left-half is silicon window, and right half part is oxygen buried layer；One silicon film and a device top layer.On the partial insulative layer with N-type silicon buried layer disclosed by the invention, silicon ldmos transistor can introduce higher electric field intensity in oxygen buried layer, thus improves the breakdown voltage of device；The more electronics provided by N-type silicon buried layer, strengthens the current driving ability of transistor, it is possible to reduce the conducting resistance of device.
Description
Technical field
Present invention design belongs to quasiconductor high-voltage power integrated circuit devices field, is specifically related to one and has N
Silicon (Partial on the partial insulative layer of type silicon buried layer (Buried N-type Layer, BNL)
Silicon-on-Insulator, PSOI) lateral double diffusion metal oxide semiconductor (Lateral
Double-diffused Metal-Oxide-Semiconductor, LDMOS), english abbreviation BNL
PSOI-LDMOS。
Background technology
Power integrated circuit development is broadly divided into both direction, and one is high voltage integrated circuit, and another is intelligence
Can power integrated circuit.No matter but that power integrated circuit, it continues a most crucial problem of development still
It is how to improve further the performance of High voltage power device, namely two problem (1) device power control
Capacity: breakdown voltage and operating current；(2) device parameter performance index: conducting resistance, operating frequency with
And switching speed etc..Therefore, multiple high-voltage LDMOS new construction is suggested, such as ladder step oxygen buried layer LDMOS,
Super junction LDMOS, carborundum LDMOS etc..And silicon PSOI structure on partial insulative layer, not only can improve device
The heat dispersion of part, and device electric breakdown strength can be greatly improved, in addition its compatibility with existing technique
Well.So, silicon LDMOS(PSOI LDMOS on partial insulative layer) arise at the historic moment, and receive much concern.Cause
And be necessary to study, further improved structure on the basis of existing PSOI LDMOS, so that
The performances such as the breakdown voltage of device, operating current, conducting resistance are more superior.
Summary of the invention
It is an object of the invention to develop for the continuation of power integrated circuit provide one to have high-breakdown-voltage, low
Conducting resistance, the ldmos transistor of high driving ability.
The technical solution used in the present invention is as follows:
Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer, it is characterised in that described crystalline substance
Body tubular construction contains the most successively:
One substrate layer；
A part of oxide layer, wherein left-half is silicon window, right half part oxygen buried layer；
One silicon film, silicon film top left side is the cingens source region of silicon body, and right side is drain region, and remainder is then
For drift region, raceway groove is provided by the silicon body between source region and drift region, drift region is covered in silicon dioxide it
On, there is the one layer of doping content N-type silicon buried layer more than drift region；
One device top layer, in device top layer, being positioned at above raceway groove is gate oxide, and drift region is extension oxide layer,
Extension oxidated layer thickness is more than gate oxide, and gate oxide is all covered by gate electrode, and extension oxide layer is close
A part for raceway groove is just covered by field plate, forms ladder step gate electrode.
The doping type of described substrate layer is p-type, and doping content is 4 × 1014cm-3Silicon materials, doping content
Needing to readjust also dependent on device performance, occurrence requires according to design and technique is drafted.
The doping type of described silicon window is consistent with substrate layer with concentration, described oxygen buried layer use thickness less than or
Equal to the silicon dioxide of 4 μm, preferably 3 μm.
The all regions of described silicon film are all silicon materials, silicon film thickness typically below 20 μm (containing 20 μm),
Be preferably 20 μm, it is also possible to bigger, but the thicker meeting of silicon fiml causes device to be prepared, heat radiation etc. some bad ask
Topic.
Described raceway groove a length of 1-5 μm.
Described source region and drain region length 5 μm, doping type is N-type, and general employing is highly doped, 1018cm-3Amount
On Ji, preferably doping content is 2 × 1019cm-3, the concrete numerical value of doping content is arranged, and length
Concrete numerical value, is drafted according to design by designer.Described silicon body doping type is p-type, and the doping of silicon body is dense
Degree generally 1017cm-3Magnitude, doping content is preferably 1 × 1017cm-3, concrete numerical value is arranged, by designer
Draft according to design.
Described drift region length is preferably 90 μm, and doping type is N-type, and doping content is 4 × 1014cm-3。
The gate oxide silicon dioxide of thick 20nm, extension oxide layer uses the silicon dioxide of thick 50nm, field
A length of 40 μm of plate, it is long too short all can affect device performance (breakdown voltage etc.).
The doping type of described silicon window is consistent with substrate layer with concentration.
The all regions of described silicon film are all silicon materials.
In described transistor arrangement, substrate layer, silicon window, silicon film are silicon materials.
Following arbitrary parameter of described transistor is the most adjustable,
(1), source region, drain region, raceway groove, drift region length is adjustable；
(2), source region, drain region, raceway groove, drift region, silicon buried layer, silicon window and the dopant material of substrate layer,
Doping content is adjustable；
(3), gate oxide, extension oxide layer and the material of oxygen buried layer, thickness is adjustable；
(4), the gate electrode field plate length above drift region is adjustable；
(5), at the timing of total device length one, its silicon window and the adjustable length of oxygen buried layer.
Silicon LDMOS(BNL on the partial insulative layer with N-type silicon buried layer proposed by the invention
PSOI-LDMOS), at length, material, the doping type of source-drain area, channel region, drift region and substrate with mix
Miscellaneous concentration is the most identical, and top silicon surface thickness is identical, and the thickness of oxygen buried layer or part oxygen buried layer is identical, all of
Under conditions of insulation oxide material parameter is all consistent, with silicon on traditional insulating barrier
LDMOS (Conventional Silicon-on-Insulator LDMOS, CSOI LDMOS), traditional portion
Silicon LDMOS on point insulating barrier (Conventional Partial Silicon-on-Insulator LDMOS,
CPSOI LDMOS) and there is (the Buried N-type Layer of silicon LDMOS on the insulating barrier of N-type silicon buried layer
Silicon-on-Insulator LDMOS, BNL SOI-LDMOS) compare.Due to the fact that and draw simultaneously
Entering silicon PSOI and two kinds of structures of N-type silicon buried layer on partial insulative layer makes high-voltage LDMOS device silicon film accommodate
The ability of carrier is higher so that electric current increase, cause device conducting resistance (On-resistance,
Ron) reduce；On the other hand, N-type silicon buried layer can introduce more electric field in the oxygen buried layer below drain region,
Thus improve the voltage endurance capability of device, simultaneously because the silicon window that PSOI introduces so that substrate layer can also divide
Load portion voltage, can improve the voltage endurance capability of device further, thus its breakdown voltage of proposed device
(Breakdown Voltage, BV) is the highest.Therefore, the present invention is the further performance of high pressure SOI-LDMOS
Optimize, and high voltage integrated circuit design provides a new selection.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of BNL-PSOI LDMOS of the present invention；
Fig. 2 is a length of 50 microns of the silicon window of BNL-PSOI, a length of 70 microns of the silicon window of CPSOI, fixing
Other parameters of ldmos transistor, device drain terminal is indulged by the partial insulative layer silicon-on with N-type silicon buried layer
To the impact of Electric Field Distribution；
A length of 50 microns of the silicon window of Fig. 3: BNL-PSOI, a length of 70 microns of the silicon window of CPSOI, fixing
Other parameters of ldmos transistor, device drain terminal is indulged by the partial insulative layer silicon-on with N-type silicon buried layer
To the impact of voltage's distribiuting；
A length of 50 microns of the silicon window of Fig. 4: BNL-PSOI, a length of 70 microns of the silicon window of CPSOI, fixing
Other parameters of ldmos transistor, have the partial insulative layer silicon-on of N-type silicon buried layer to device upper surface
The impact of Electric Field Distribution；
A length of 50 microns of the silicon window of Fig. 5: BNL-PSOI, a length of 70 microns of the silicon window of CPSOI, fixing
Other parameters of ldmos transistor, have the partial insulative layer silicon-on of N-type silicon buried layer to device lower surface
The impact of Electric Field Distribution；
Fig. 6: other parameters of fixing BNL-PSOI LDMOS, change silicon length of window LWTo device electric breakdown strength
BV, oxygen buried layer undertake voltage VIAnd substrate undertakes voltage VsubImpact；
Fig. 7；Other parameters of fixing BNL-PSOI LDMOS, change concentration N of N-type silicon buried layerBNLAnd thickness
tBNLImpact on device electric breakdown strength；
Fig. 8: other parameters of fixing BNL-PSOI LDMOS, change concentration N of N-type silicon buried layerBNLTo puncturing
The impact of the drain terminal longitudinal electric field distribution under state；
Fig. 9: other parameters of fixing BNL-PSOI LDMOS, change the thickness t of N-type silicon buried layerBNLTo puncturing
The impact of the drain terminal longitudinal electric field distribution under state；
Figure 10: other parameters of fixing BNL-PSOI LDMOS, in concentration N of different N-type silicon buried layersBNLAnd thickness
Degree tBNLUnder conditional combination, along with the increase of silicon length of window, breakdown voltage (Breakdown Voltage, BV)
With conducting resistance (On-resistance, Ron) relation；
Figure 11: other parameters of fixing LDMOS, the silicon window variable-length of two kinds of PSOI structures, compare four kinds
The breakdown voltage of device architecture and the relation of conducting resistance.
Detailed description of the invention
Below in conjunction with being embodied as example, the present invention is further elaborated.
As it is shown in figure 1, the present invention has silicon LDMOS(BNL on the partial insulative layer of N-type silicon buried layer
PSOI-LDMOS) there are four layers the most successively:
(1), substrate layer 10, doping type is p-type, and doping content is 4 × 1014cm-3Silicon materials, mix
Miscellaneous concentration needs to readjust also dependent on device performance, and occurrence requires according to design and technique is drafted.
(2), portion of oxide layer 20, wherein left-half is silicon window 21, its doping type and concentration and lining
The end, is consistent, right half part oxygen buried layer 22, the silicon dioxide using thickness to be 3 μm；
(3), silicon film 30, all regions of described silicon film are all silicon materials, and thickness is 20 μm, silicon film
30 top left side are the cingens source region of silicon body 32 31, and right side is drain region 34, and remainder is then drift region
33, raceway groove is provided by the silicon body 32 between source region 31 and drift region 33, a length of 5 μm of raceway groove, drift region 33
It is covered on silicon dioxide, has the one layer of doping content N-type silicon buried layer 35 more than drift region 33, source region
31 and long 5 μm in drain region 34, doping type is N-type, and doping content is 2 × 1019cm-3；Silicon body 32 adulterates class
Type is p-type, and doping content is 1 × 1017cm-3；A length of 90 μm in drift region 33, doping type is N-type,
Doping content is 4 × 1014cm-3；
(4), device top layer 40, in device top layer 40, being positioned at above raceway groove is thin gate oxide 41, adopts
Being the silicon dioxide of 20nm with thickness, being positioned at above drift region 33 is thick extension oxide layer 42, uses thickness
The silicon dioxide of 50nm, gate oxide 41 is all covered by gate electrode 43, and extension oxide layer 42 is near raceway groove
A part just covered by field plate 44, a length of 40 μm of field plate 44, thus form ladder step gate electrode.
The partial insulative layer of N-type silicon buried layer is provided with on silicon LDMOS electrode 45,46.
The present invention has silicon LDMOS(BNL PSOI-LDMOS on the partial insulative layer of N-type silicon buried layer), its property
Can be to obtain based on three-dimensional Sentaurus TCAD software simulation study, and analog simulation research serves as a contrast
The end and source are all ground connection.
Embodiment 1:
A length of 50 μm of silicon window of BNL-PSOI, a length of 70 μm of silicon window of CPSOI, N-type silicon buried layer adulterates
Concentration is 9.2 × 1015cm-3Thickness is 0.5 μm, other parameters of fixing ldmos transistor, has N-type
The impact that device drain terminal longitudinal electric field is distributed by the partial insulative layer silicon-on of silicon buried layer.
As in figure 2 it is shown, have BNL-PSOI structure and the BNL-SOI structure of N-type silicon buried layer, can bury
Oxygen layer introduces high electric field, such that it is able to improve device electric breakdown strength.Additionally, the electric field that BNL-PSOI introduces
Lower by about 2 × 10 than BNL-SOI4V/cm or 2.6%, this is because: hole on interface in order to keep electrical
Seriality can redistribute.In BNL-SOI, hole is in the bottom (namely silicon/oxygen buried layer interface) of silicon fiml
Accumulation distribution can be formed, but in BNL-PSOI structure, these holes can be driven into lining by silicon window
The end, so the hole number at the silicon of BNL-SOI/oxygen buried layer interface is some more below drain terminal.But due to
Hole is minority carrier, and comparing with alms giver's ionized impurity of n type buried layer is the difference on the order of magnitude, institute
More a little bit smaller than BNL-SOI with BNL-PSOI, and can't be mutually far short of what is expected.
Embodiment 2:
A length of 50 μm of silicon window of BNL-PSOI, a length of 70 μm of silicon window of CPSOI, N-type silicon buried layer adulterates
Concentration is 9.2 × 1015cm-3Thickness is 0.5 μm, other parameters of fixing ldmos transistor, has N-type
The impact that device drain terminal longitudinal voliage is distributed by the partial insulative layer silicon-on of silicon buried layer.
As it is shown on figure 3, owing to the substrate of PSOI structure can share a part of breakdown voltage, and soi structure
Substrate is almost without undertaking voltage.Although for BNL-PSOI and BNL-SOI, the voltage V that oxygen buried layer undertakesI
It is respectively 225V and 230V, but the substrate of BNL-PSOI undertakes voltage VsubThe BNL-SOI for 120V
VsubBeing almost equal to zero, the most generally, BNL-PSOI can obtain much higher breakdown voltage than BNL-SOI.
Additionally, the V of CPSOI and CSOIIOnly have 156V and 168V respectively, compare with them, BNL-PSOI's
VIIt is respectively increased 44.2% and 33.9%.Therefore, in the LDMOS of these four structure, BNL-PSOI obtains
The highest breakdown voltage.
Embodiment 3:
A length of 50 μm of silicon window of BNL-PSOI, a length of 70 μm of silicon window of CPSOI, N-type silicon buried layer adulterates
Concentration is 9.2 × 1015cm-3Thickness is 0.5 μm, other parameters of fixing ldmos transistor, has N-type
The impact on device upper surface Electric Field Distribution of the partial insulative layer silicon-on of silicon buried layer.
As shown in Figure 4, due to silicon and the difference of dioxide dielectric constant, in silicon window and the boundary of oxygen buried layer
Place's (the most respectively at a length of 50 μm of silicon window and 70 μm), CPSOI and BNL-PSOI upper surface is respectively
Having one " protruding ", this " protruding " plays the electric field intensity dragging down source and drain end, thus improves device
Breakdown voltage.This means that PSOI structure can be strengthened reducing surface field (REduced SURface than SOI further
Field, RESURF) effect.
Embodiment 4:
A length of 50 μm of silicon window of BNL-PSOI, a length of 70 μm of silicon window of CPSOI, N-type silicon buried layer adulterates
Concentration is 9.2 × 1015cm-3Thickness is 0.5 μm, other parameters of fixing ldmos transistor, has N-type
The impact on device lower surface Electric Field Distribution of the partial insulative layer silicon-on of silicon buried layer.
As it is shown in figure 5, for two kinds of PSOI structure devices, when gradually rising to from the lower surface of top silicon surface
The when of upper surface, the spike in Fig. 5 can become the projection in Fig. 4.And these spikes of BNL-PSOI or
Sharp peaks or projections corresponding in convexity CPSOI wants height, then drag down source and drain end electric field in explanation BNL-PSOI
Effect is higher, this also means that the RESURF effect of BNL-PSOI is better than CPSOI.So BNL-PSOI
RESURF effect be best in four kinds of device architectures.
Embodiment 5:
N-type silicon buried layer doping content is 9.2 × 1015cm-3Thickness is 0.5 μm, fixing BNL-PSOI LDMOS
Other parameters, change silicon length of window LWDevice electric breakdown strength BV, oxygen buried layer are undertaken voltage VIAnd lining
The end, undertakes voltage VsubImpact (owing to total device length is constant, so oxygen buried layer length and the length of silicon buried layer
Corresponding change can occur therewith).
As shown in Figure 6, in BNL-PSOI device, the length of silicon window is to breakdown voltage BV of device and each
The voltage's distribiuting in region has significant effect, here it is apparent that, breakdown voltage first increases and reduces afterwards, with LW=
50 μm are turning point.At LWBefore=50 μm, oxygen buried layer voltage VISlowly reduce and underlayer voltage Vsub
Quickly increasing, now along with the increase depletion layer of silicon window length, to thrust substrate layer the deepest, and breakdown voltage increases；
But at LWAfter=50 μm, along with the increase of silicon window length, oxygen buried layer voltage VIReduction start to accelerate
(precipitous) and underlayer voltage VsubIncrease but start slack-off (flattening), this shows substrate carrier now
Start to stop depletion layer to extend to substrate area further, thus the breakdown voltage of BNL-PSOI begins to decline.
Embodiment 6:
A length of 50 μm of silicon window, other parameters of fixing BNL-PSOI LDMOS, change mixing of N-type silicon buried layer
Miscellaneous concentration NBNLWith thickness tBNLImpact on device electric breakdown strength.
As it is shown in fig. 7, work as NBNLTime fixing, along with tBNLIncreasing, breakdown voltage is all first to increase to reduce afterwards；And
Work as tBNLTime fixing, along with NBNLIncreasing, breakdown voltage is all first to increase to reduce afterwards.Thickness along with n type buried layer
Degree tBNLIncrease, " the opening bore " of breakdown voltage curve can be more and more less, breakdown voltage maximum simultaneously
It is kept approximately constant, about 660 volts.So for this example, in order to obtain optimized device
Can, the thickness t of n type buried layerBNL2 μm should be less than, can be so the manufacturing and the working line of device
For providing space, more limit, to ensure high efficiency and the reliability of device.
Embodiment 7:
A length of 50 μm of silicon window, the thickness t of N-type silicon buried layerBNLIt is 0.5 μm, fixing BNL-PSOI LDMOS
Other parameters, change N-type silicon buried layer doping content NBNLDrain terminal longitudinal electric field under breakdown conditions is distributed
Impact.
As shown in Figure 8, as N-type silicon buried layer thickness tBNLWhen immobilizing, along with doping content NBNLIncrease,
The electric field of silicon/oxygen buried layer interface also can increase.So, along with doping content NBNLIncrease, puncturing of device
Voltage is also first in increase trend, when increasing to a certain degree when, can reach prematurely due to ionization integration
To unit constant, so that device breakdown occurs to early, cause punch through voltage and reduce.Because if from top
Layer silicon fiml is seen toward its basal surface (silicon/oxygen buried layer interface), and the electric field of silicon/oxygen buried layer near interface is to rise rapidly
High, can be found in Fig. 8 illustration, but, when doping content exceedes certain value time so that N-type silicon buried layer
In electric field have a too high increase, thus ionize integration and will more easily reach unit constant, then just reduce
The breakdown voltage of device.Now, there is the silicon/oxygen buried layer interface below drain terminal in device breakdown.
Embodiment 8:
A length of 50 μm of silicon window, the thickness N of N-type silicon buried layerBNLIt is 9.2 × 1015cm-3, fixing BNL-PSOI
Other parameters of LDMOS, change the thickness t of N-type silicon buried layerBNLDrain terminal longitudinal electric field under breakdown conditions is divided
The impact of cloth.
As it is shown in figure 9, thicker N-type silicon buried layer is bigger to the change of longitudinal electric field, and can be at silicon buried layer
Introduce higher longitudinal electric field.All ionized donor ions in this explanation n type buried layer are all to silicon/oxygen buried layer circle
High electric field on face has contribution.So with Fig. 8 breakdown voltage-silicon buried layer doping content " relation is similar, along with
Silicon buried layer thickness tBNLIncrease, breakdown voltage can first increase, but, as silicon buried layer thickness tBNLExceed certain
During value, the electric field of silicon/oxygen buried layer interface is the highest, causes device to puncture in advance, thus breakdown voltage reduces.
Now, there is the silicon below drain terminal/oxygen buried layer interface equally in device breakdown.
Embodiment 9:
Other parameters of fixing BNL-PSOI LDMOS, in concentration N of different N-type silicon buried layersBNLWith thickness tBNL
Under conditional combination, along with the increase of silicon length of window, breakdown voltage (Breakdown Voltage, BV) with lead
The relation of energising resistance (On-resistance, Ron).
As shown in Figure 10, example 9 is chosen so that device can reach maximum breakdown voltage according to Fig. 7.Permissible
See, along with the increase of silicon window length, conducting resistance (ROn, sp) can increase together with breakdown voltage (BV).Former
One of cause is that the electronics provided due to shorter N-type silicon buried layer (bigger silicon window length) is less, thus leads
Cause work leakage current less, namely mean that electric conduction resistive is big；Another one reason is due to the increasing of silicon window
Add and depleted region can be caused to become big and cause electric current to reduce, be similarly to " the electric conduction in traditional PS OI structure
Resistance-silicon window length " relation.Conducting resistance curve in figure is overall past along with the increase of N-type silicon buried layer thickness
Lower right is moved, it is meant that the BNL-PSOI that silicon buried layer thickness is the biggest has more preferable device performance, the biggest
Breakdown voltage and less conducting resistance.In the drawings it is seen that, silicon buried layer thickness is 0.5 μm and 1.0 μm
Two curves intersect and be coupled, illustrate that two curves are respectively arranged with quality in different working regions,
Such as: breakdown voltage is in the region of 600～650V, and thickness is that to be better than thickness be 0.5 μm for the curve of 1.0 μm
Curve；In the drawings the region at two ends be then thickness be that the curve of 0.5 μm is wanted more preferably.Wide in range in view of having
Optimum device performance scope as design reference, the scope of silicon buried layer thickness is selected from 0.5 μm to 1.0 μm
Between.
Embodiment 10:
N-type silicon buried layer doping content N of BNL-PSOI and BNL-SOIBNLIt is respectively 1.1 × 1016cm-3With
9.2×1015cm-3, silicon buried layer thickness tBNLIt is 0.5 μm, other parameters of fixing LDMOS, two kinds of PSOI
The silicon window variable-length of structure, compares the breakdown voltage of four kinds of device architectures and the relation of conducting resistance.
As shown in figure 11, it is understood that the performance seeing BNL-PSOI be best in all device architectures.With
CSOI with CPSOI compares, and BNL-PSOI is not only only capable of reaching much higher 660V breakdown voltage, and
Its conducting resistance also reduces 13.6%～15.5%.And compared with BNL-SOI, although BNL-PSOI
Conducting resistance corresponding to 660V breakdown voltage is than big the 7.8% of BNL-SOI, but the puncturing of its 660V
Voltage about high by 20.4% than BNL-SOI, thus final BNL-PSOI can obtain more preferable device quality because of
Number (Figure-of-merit ,=BV2/Ron)
From example 1-10, silicon LDMOS on the partial insulative layer with N-type silicon buried layer proposed by the invention
(BNL-PSOI LDMOS) can introduce higher electric field intensity in oxygen buried layer, thus improves hitting of device
Wear voltage；The more electronics provided by N-type silicon buried layer, strengthens the current driving ability of transistor, and
The conducting resistance of device can be reduced；Due to the material impact of silicon buried layer, need to consider to select silicon buried layer comprehensively
Parameter is to obtain more excellent device performance.
In sum, although the detailed description of the invention of the present invention is to the present invention have been described in detail, but ability
Territory those skilled in the art are it is to be understood that above-described embodiment is only to retouch the preferred embodiments of the present invention
State, rather than limiting the scope of the invention, persons skilled in the art are in the skill that disclosed herein
In the range of art, the change that can readily occur in, all within protection scope of the present invention.
Claims (4)
1. silicon ldmos transistor on a partial insulative layer with N-type silicon buried layer, it is characterised in that described
Transistor arrangement contains the most successively:
One substrate layer, the doping type of described substrate layer is p-type, and doping content is 4 × 1014cm-3Silicon materials；
A part of oxide layer, wherein left-half is silicon window, and right half part is oxygen buried layer, described silicon window
Doping type consistent with substrate layer with concentration, a length of 50 μm of described silicon window, state oxygen buried layer use thickness little
In or equal to the silicon dioxide of 4 μm；
One silicon film, silicon film top left side is the cingens source region of silicon body, and right side is drain region, remainder
Being then drift region, raceway groove is provided by the silicon body between source region and drift region, is covered in silicon dioxide in drift region
On, there is the one layer of doping content N-type silicon buried layer more than drift region, the thickness of described silicon buried layer is less than 2 μm,
Described silicon film thickness is less than or equal to 20 μm, described raceway groove a length of 1-5 μm, described source region and drain region length 5
μm, doping type is N-type, and doping content is 2 × 1019cm-3, described silicon body doping type is p-type, doping
Concentration is 1 × 1017cm-3,Described drift region length is 90 μm, and doping type is N-type, and doping content is
4×1014cm-3；
One device top layer, in device top layer, being positioned at above raceway groove is gate oxide, and drift region is arranged above extension
Oxide layer, extension oxidated layer thickness is more than gate oxide, and gate oxide is all covered by gate electrode, extends oxygen
Changing layer and just covered by field plate near a part for raceway groove, form ladder step gate electrode, described gate oxide is thickness
For the silicon dioxide of 20nm, extension oxide layer uses the silicon dioxide of thick 50nm, a length of 40 μm of field plate.
There is silicon ldmos transistor on the partial insulative layer of N-type silicon buried layer, its feature the most as claimed in claim 1
It is: all regions of described silicon film are all silicon materials.
There is silicon ldmos transistor on the partial insulative layer of N-type silicon buried layer, its feature the most as claimed in claim 1
Being: in described transistor arrangement, substrate layer, silicon window, silicon film are silicon materials.
There is silicon ldmos transistor on the partial insulative layer of N-type silicon buried layer, its feature the most as claimed in claim 1
It is: following arbitrary parameter of described transistor is the most adjustable,
(1), source region, drain region, raceway groove, drift region length is adjustable；
(2), source region, drain region, raceway groove, drift region, silicon buried layer, silicon window and the dopant material of substrate layer, doping
Concentration is adjustable；
(3), gate oxide, extension oxide layer and the material of oxygen buried layer, thickness is adjustable；
(4), the gate electrode field plate length above drift region is adjustable；
(5), at the timing of total device length one, its silicon window and the adjustable length of oxygen buried layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310395509.6A CN103606562B (en) | 2013-09-03 | 2013-09-03 | Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310395509.6A CN103606562B (en) | 2013-09-03 | 2013-09-03 | Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103606562A CN103606562A (en) | 2014-02-26 |
| CN103606562B true CN103606562B (en) | 2017-01-04 |
Family
ID=50124777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310395509.6A Active CN103606562B (en) | 2013-09-03 | 2013-09-03 | Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103606562B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206666B (en) * | 2014-05-28 | 2018-09-25 | 北大方正集团有限公司 | Semiconductor devices |
| CN104201203B (en) * | 2014-08-13 | 2016-03-30 | 四川广义微电子股份有限公司 | High withstand voltage LDMOS device and manufacture method thereof |
| CN104966734A (en) * | 2015-05-06 | 2015-10-07 | 深圳市海泰康微电子有限公司 | Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor used for high frequency circuit design and preparation method thereof |
| CN106298475B (en) * | 2015-06-03 | 2020-07-14 | 北大方正集团有限公司 | Method for reducing expansion on semiconductor substrate |
| CN112713193B (en) * | 2020-12-30 | 2023-05-02 | 杭州电子科技大学温州研究院有限公司 | Trench LDMOS transistor with convex type extended buried oxide region |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
-
2013
- 2013-09-03 CN CN201310395509.6A patent/CN103606562B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101477999A (en) * | 2009-01-19 | 2009-07-08 | 电子科技大学 | SOI voltage resistant structure having interface charge island for power device |
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103606562A (en) | 2014-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9842925B2 (en) | Insulated gate semiconductor device having a shield electrode structure and method | |
| US7928505B2 (en) | Semiconductor device with vertical trench and lightly doped region | |
| CN102610643B (en) | Trench MOSFET device | |
| TWI374474B (en) | High voltage lateral fet structure with improved on resistance performance | |
| US8778764B2 (en) | Method of making an insulated gate semiconductor device having a shield electrode structure and structure therefor | |
| CN104201206B (en) | A kind of laterally SOI power LDMOS device | |
| CN103268890B (en) | A kind of power LDMOS device with junction type field plate | |
| CN103606562B (en) | Silicon ldmos transistor on a kind of partial insulative layer with N-type silicon buried layer | |
| JP5280056B2 (en) | MOS field effect transistor | |
| WO2012055225A1 (en) | High voltage ldmos device | |
| JP2011512677A (en) | Semiconductor device structure and related processes | |
| CN103474466B (en) | A kind of high tension apparatus and manufacture method thereof | |
| JP7442699B2 (en) | semiconductor equipment | |
| CN103280457B (en) | A kind of horizontal high voltage power device of Ultra-low Specific conducting resistance and manufacture method | |
| KR102068842B1 (en) | Semiconductor power device | |
| Su et al. | State-of-the-art device in high voltage power ICs with lowest on-state resistance | |
| WO2014000340A1 (en) | Trench-gate semiconductor power device | |
| CN111725071B (en) | Silicon-based junction accumulation layer and buffer layer lateral double-diffusion field effect transistor and manufacturing method thereof | |
| CN103311272B (en) | There is the (Silicon-on-insulator) MOSFET lateral of dielectric isolation groove | |
| JP2008124421A (en) | Semiconductor device and method for fabricating it | |
| CN105789270A (en) | VDMOS device with variable dielectric side | |
| CN105097936A (en) | Silicon-on-insulator lateral double-diffused metal-oxide-semiconductor (LDMOS) power device | |
| JP5148852B2 (en) | Semiconductor device | |
| CN104966734A (en) | Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor used for high frequency circuit design and preparation method thereof | |
| CN107546274B (en) | LDMOS device with step-shaped groove |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201208 Address after: No. 321, No. 88, qinlang Road, Hengqin New District, Zhuhai City, Guangdong Province Patentee after: Zhuhai Youte Lean Development Co., Ltd Address before: 518057, Guangdong Nanshan District hi tech Industrial Park, Shenzhen Southern Hong Kong University Research Base Patentee before: PEKING University SHENZHEN GRADUATE SCHOOL |
|
| TR01 | Transfer of patent right |