JP5353093B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a lateral insulation gate transistor element achieving downsizing while suppressing ON resistance increase, and to provide a manufacturing method therefor. <P>SOLUTION: The semiconductor device includes an LDMOS element formed on a semiconductor layer and a first contact plug serving as a contact plug formed to pass through an insulation film formed on a main surface of the semiconductor layer from the main surface and connected to source and base contact regions. The base contact region is formed at a position lower than the position of the source region relative to the main surface almost perpendicularly to the main surface of the semiconductor layer and where it at least partially overlaps the source region along the main surface of the semiconductor layer. The first contact plug is extended up to the base contact region passing through the insulation film and the source region. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

The present invention relates to a method for manufacturing a semiconductor device including a lateral insulated gate transistor element.

  Conventionally, for example, as disclosed in Patent Document 1, a semiconductor device including a horizontal insulated gate transistor element is known.

The semiconductor device disclosed in Patent Document 1 has a lateral DMOS element (hereinafter referred to as an LDMOS element) as a lateral insulated gate transistor element. Specifically, a p conductivity type base layer is formed on a surface layer of an n conductivity type active layer (semiconductor layer), and an n + source layer and a p + diffusion layer are formed side by side on the surface layer in the base layer. A source electrode is provided on the n + source layer and the p + diffusion layer. That is, the n + source layer and the p + diffusion layer are connected to a common contact plug (source electrode).
JP 2001-320047 A

  By the way, lateral insulated gate transistor elements (LDMOS elements) used as power ICs combined with ICs (Integrated Circuits) including memory cells and logic circuits, and control ICs including CMOS, etc. High integration is required. That is, further downsizing of the physique of the LDMOS element formed in the semiconductor layer, specifically, downsizing in a direction substantially perpendicular to the thickness direction of the semiconductor layer is required.

  As a means for reducing the size, a plug technology using tungsten (W) or the like is known, whereby the diameter of the contact plug can be reduced to, for example, 0.5 μm or less. However, in a configuration in which an n + source layer and a p + diffusion layer are connected to a common contact plug as in the configuration disclosed in Patent Document 1, if the contact plug has a small diameter, due to manufacturing variations, for example, the contact plug and the n + source There is a possibility that the contact area with the layer is small and the on-resistance (contact resistance) is high, or that the contact plug is not connected to one of the n + source layer and the p + diffusion layer.

  On the other hand, it is conceivable to adopt a structure in which the n + source layer and the p + diffusion layer are connected to contact plugs having different fine diameters. However, when separate contact plugs are formed for the n + source layer and the p + diffusion layer, it is necessary to consider misalignment in the exposure process when the contact hole is formed by etching the insulating film on the semiconductor layer. In view of such manufacturing variations, there is a margin in the formation region of the n + source layer and the p + diffusion layer. That is, it is difficult to reduce the size of the LDMOS element.

In view of the above problems, it comprises a lateral insulated gate field effect transistor, and an object thereof is to provide a method of manufacturing a semiconductor device capable of miniaturizing the physique while suppressing an increase in on-resistance.

The semiconductor device which is the object of the manufacturing method according to the present invention includes a first conductivity type semiconductor layer having a main surface and a second opposite to the first conductivity type formed on a surface layer on the main surface side of the semiconductor layer. A conductive type base region; a first conductive type first high concentration region formed in a surface layer in the base region; and a second conductive type formed in the base region and having a higher impurity concentration than the base region. A first contact type second high concentration region, a first high concentration region, and a second high concentration region formed on the surface layer on the main surface side of the semiconductor layer apart from the base region; A lateral insulating gate transistor element having a gate electrode formed on the base region via a gate insulating film, and a contact penetrating from the same surface through the insulating film formed on the main surface of the semiconductor layer. As a plug, the first high concentration region and the base And it includes a first contact plug connected to the contact region. The base contact region is lower than the first high-concentration region in the direction substantially perpendicular to the main surface of the semiconductor layer (hereinafter referred to as the vertical direction) and is along the main surface of the semiconductor layer. In the direction (hereinafter referred to as the left-right direction), the first contact plug is formed at a position at least partially overlapping with the first high-concentration region, and the first contact plug penetrates the insulating film and the first high-concentration region. It is characterized by extending to the area.

According to the semiconductor device , the first high concentration region is formed in the surface layer on the main surface side in the base region, and is below the first high concentration region and in the left-right direction. A base contact region is formed at a position at least partially overlapping. The first contact plug extends to the base contact region while penetrating the insulating film and the first high-concentration region, and serves as a common plug for the first high-concentration region and the base contact region. Therefore, even if the diameter of the first contact plug (the diameter on the surface of the insulating film opposite to the main surface of the semiconductor layer , in other words, the diameter on the upper surface of the insulating film, hereinafter referred to as the upper end diameter ) is reduced. A contact area with the first high-concentration region can be ensured, thereby suppressing an increase in on-resistance (contact resistance) of the lateral insulated gate transistor element. In addition, the contact area with the base contact region can be ensured, the potential of the base region can be set to a predetermined potential, and the operation of the lateral insulated gate transistor element can be stabilized.

  The base contact region is formed at a position below the first high concentration region and at least partially overlapping the first high concentration region in the left-right direction. That is, the first high concentration region and the base contact region are arranged in parallel in the vertical direction. Therefore, in the left-right direction, the physique in the left-right direction can be reduced as compared with the conventional configuration in which the first high-concentration region and the base contact region are arranged side by side. Furthermore, in the vertical direction, the first high concentration region and the base contact region are arranged in parallel, so that the contact plug is shared. Therefore, the physique in the left-right direction can be made smaller than when separate contact plugs are formed.

The semiconductor device, as a contact plug, a second contact plug connected to the second heavily doped region, and includes a third contact plug connected to the gate electrode, all the contact plugs, the upper end It is good also as a structure by which the diameter was made substantially equal.

  In the contact plug in which the conductive member is embedded in the contact hole, the variation in the depth of the contact hole formed by etching increases as the upper end diameter decreases. Therefore, when forming multiple types of contact plugs with different upper end diameters in the same process, even if the formation of contact holes with larger upper end diameters is completed, contact holes with smaller upper end diameters can only reach a predetermined depth. It may happen that it is not formed. On the other hand, if the upper end diameters of all the contact plugs are substantially equal, the influence of variation during etching becomes the same in each contact hole, so that the electrical connection state between each contact plug and the corresponding connection location in the element is It becomes easy to secure. Moreover, since each contact plug can be formed in the same process, the manufacturing process can be simplified.

In this case , as the insulating film, an insulating film having a slower etching rate than the insulating film in the first contact plug formation region is arranged in the contact plug formation region shallower than the first contact plug. Is preferred.

  According to this, even if the upper end diameters of all the contact plugs are substantially equal, the depth of each contact plug can be adjusted by the configuration of the insulating film, so that, for example, only the first contact plug extends to the semiconductor layer side. It can be set as the extended structure.

In the semiconductor device , the first contact plug has a diameter on the surface on the main surface side of the semiconductor layer in the insulating film (in other words, the diameter on the lower surface of the insulating film and the lower end diameter corresponding to the upper end diameter) You may employ | adopt the thing of the level | step difference shape made larger than the diameter in the main surface of an area | region. According to this, since the contact area between the first high concentration region and the contact plug is increased, the on-resistance (contact resistance) can be further reduced while keeping the upper end diameter the same.

The semiconductor device may employ a first contact plug in which the lower end diameter and the diameter of the portion in the base region are larger than the upper end diameter.

  According to these, when the contact hole corresponding to the first contact plug is formed after forming the first high-concentration region, and the base contact region is formed via the contact hole by ion implantation, Ions can be suppressed from being implanted into the first high concentration region. That is, an increase in on-resistance (contact resistance) can be suppressed.

In this case , an impurity may be added to the insulating film in the formation region of the first contact plug, and the impurity concentration may be higher at a portion closer to the main surface side of the semiconductor layer . In the same insulating film, the higher the added impurity concentration, the faster the etching rate. Therefore, as described above , the impurity concentration in the insulating film suppresses ions from being implanted into the first high concentration region in the contact hole, thereby suppressing an increase in on-resistance (contact resistance). it can. For example, BPSG or PSG can be used as such an insulating film.

The semiconductor device preferably employs a lateral DMOS element (hereinafter referred to as an LDMOS element) in which the first high-concentration region is a source region and the second high-concentration region is a drain region as the lateral insulated gate transistor element. . The LDMOS element is suitable as a power IC used for controlling a vehicle control ECU (Electric Control Unit) and various consumer devices because it has good process consistency with other elements such as CMOS.

In this case , a CMOS transistor element configured in a semiconductor layer may be provided, and a contact plug for a CMOS transistor element connected to the CMOS transistor element may be provided as a contact plug.

A contact plug connected to the CMOS transistors (especially fine CMOS transistor) is its upper end diameter is small, according to this, it is also possible integration with LDMOS device with such a CMOS transistor. And a manufacturing process can be simplified.

In addition to the CMOS transistor element, for example , a bipolar transistor element configured in a semiconductor layer may be provided, and a contact plug for a bipolar transistor element connected to the bipolar transistor element as a contact plug may be provided.

  According to this, the shape of the first contact plug can be a stepped shape in which the diameter on the main surface side of the insulating film is larger than the diameter on the main surface of the base region. Therefore, the on-resistance (contact resistance) can be further reduced by increasing the contact area between the first high concentration region and the contact plug while keeping the same upper end diameter. Note that for the isotropic etching, a material having a large rate difference between the insulating film and the semiconductor layer, such as hydrofluoric acid, can be used.

Next, a manufacturing method according to the present invention for the semiconductor device will be described.
The method of manufacturing a semiconductor device according to 請 Motomeko 1, with respect to the first conductivity type semiconductor layer having a main surface, a device forming step of forming an element including at least lateral insulated gate field effect transistor, a main surface of the semiconductor layer A plug forming step of forming a plurality of contact plugs penetrating the insulating film formed above from the same surface and connected to the element. Then, as an element forming step, impurities are introduced from the main surface side by ion implantation into the semiconductor layer in which the base region of the second conductivity type opposite to the first conductivity type is formed on the surface layer on the main surface side. Forming a first high concentration region of the first conductivity type on the surface layer in the base region; and after forming the first high concentration region, an insulating film is formed on the semiconductor layer, and etching is performed on the insulating film . The diameter (upper end diameter) on the surface opposite to the main surface of the semiconductor layer is substantially equal, and penetrates the first high concentration region from the insulating film to the main surface rather than the first high concentration region in the base region. On the other hand, a step of forming a plurality of contact holes including a first contact hole reaching a lower region, and after forming the contact hole, an impurity is introduced into the semiconductor layer through the contact hole by an ion implantation method. Base area In the direction substantially perpendicular to the main surface of the semiconductor layer, the first high concentration region is lower than the first high concentration region, and in the direction along the main surface of the semiconductor layer, at least the first high concentration region and Including a step of forming a base contact region of a second conductivity type having a higher impurity concentration than the base region at a position where a part thereof overlaps, and in the plug formation step, a conductive member is embedded in the contact hole to form a first high concentration In the step of forming a plurality of contact plugs including a first contact plug in contact with the region and the base contact region and forming the contact hole, the insulating film is formed in the contact hole formation region shallower than the first contact hole. An insulating film having a slower etching rate than an insulating film in a contact hole forming region is selectively formed. .

Operation and effect of the semiconductor device obtained by the manufacturing method of the present invention, Ru der as described in paragraphs [0008] - [0014].

In this case, as described in claim 2 , in the step of forming the contact hole, an insulating film having a higher concentration of the impurity added to a region closer to the main surface of the semiconductor layer is formed in the formation region of the first contact plug. It is good to form.

In the same insulating film, the higher the added impurity concentration, the faster the etching rate. Therefore, according to the present invention, the shape of the contact hole in the insulating film can be made larger in diameter as it is closer to the main surface of the semiconductor layer . As a result, when the base contact region is formed, ions can be suppressed from being implanted into the first high-concentration region in the contact hole, and an increase in on-resistance (contact resistance) can be suppressed. . For example, BPSG or PSG can be used as such an insulating film.

According to a third aspect of the present invention, in the step of forming the contact hole, after the anisotropic etching, the insulating film and the semiconductor layer are isotropically etched by using the same mask as the anisotropic etching, and the first etching is performed. In the step of forming the base contact region and forming the base contact region, the base contact region may be formed in the semiconductor layer through the first contact hole by the ion implantation method using the same mask as in the etching.

  According to this, the diameter of the first contact plug can be made larger than the opening diameter of the mask at least above the wall surface portion of the first high concentration region. As a result, when the base contact region is formed, ions can be suppressed from being implanted into the first high-concentration region in the contact hole, and an increase in on-resistance (contact resistance) can be suppressed. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a cross-sectional view showing a schematic configuration of part of an LDMOS element formation region in the semiconductor device according to the first embodiment of the present invention.

  A semiconductor device 100 shown in FIG. 1 has a lateral DMOS element (Lateral Double Diffusion MOS-FET, hereinafter referred to as an LDMOS element) as a lateral insulated gate transistor element as an element formed on a semiconductor substrate 10.

The semiconductor substrate 10 corresponds to a semiconductor layer of the first conductivity type described in the claims. In the present embodiment, for example, an N conductivity type (N impurity concentration of about 1 × 10 ¹⁶ cm ^{−3 is used.} ) Bulk single crystal silicon substrate. In the following, the thickness direction of the semiconductor substrate 10 is the up-down direction, and the direction substantially perpendicular to the thickness direction (the direction along the main surface 10a of the semiconductor substrate 10) is the left-right direction. As the semiconductor layer, a part of the semiconductor substrate in the vertical direction can be adopted.

In the semiconductor substrate 10, a P conductivity type (P) base region 11 having an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ is formed in a part of the surface layer on the main surface 10a side. An N conductivity type (N +) source region 12 is formed on the surface layer in the base region 11. The source region 12 corresponds to the first high concentration region described in the claims, and the impurity concentration may be a concentration that can ensure ohmic characteristics with the first contact plug 31 described later. . In this embodiment, it is about 1 × 10 ²⁰ cm ⁻³ .

Further, in the base region 11, a p conductivity type (p +) of the main surface 10 a is located below the source region 12 in the vertical direction and at least partially overlaps the source region 12 in the horizontal direction. A base contact region 13 is formed. The base contact region 13 is a connection region with the first contact plug 31 in the base region 11, and the impurity concentration may be any concentration that can ensure ohmic characteristics with the first contact plug 31. In the present embodiment, almost the entire base contact region 13 overlaps the source region 12 in the left-right direction, and the impurity concentration is about 1 × 10 ²⁰ cm ⁻³ . Thus, the source region 12 and the base contact region 13 are arranged side by side in the vertical direction in the base region 11.

On the surface layer of the semiconductor substrate 10 on the main surface 10a side, an N conductivity type (N +) drain region 14 having an impurity concentration of about 1 × 10 ²⁰ cm ⁻³ is formed apart from the base region 11. The drain region 14 corresponds to a second high concentration region described in the claims. A portion of the base region 11 sandwiched between the source region 12 and the drain region 14 is a channel formation region of the LDMOS element. That is, in this embodiment, an N-channel type LDMOS element is formed as the LDMOS element. In addition, a drift region of N conductivity type (N) having a concentration higher than that of the semiconductor substrate 10 is formed in the surface layer on the main surface 10a side of the semiconductor substrate 10, and a drain region 14 is formed in the surface layer in the drift region. It is good also as a structure.

  In addition, a LOCOS oxide film 15 is formed on the main surface 10 a of the semiconductor substrate 10 between the base region 11 and the drain region 14, and the semiconductor substrate located between the LOCOS oxide film 15 and the source region 12. A gate electrode 17 is formed above the base region 11 and a gate insulating film 16.

Then, insulation is performed so as to cover the gate electrode 17 disposed on the main surface 10a of the semiconductor substrate 10 with the gate insulating film 16 interposed therebetween at a portion excluding the formation region of the contact plug 30 on the main surface 10a of the semiconductor substrate 10. A film 20 is formed. In the present embodiment, as shown in FIG. 1, the first insulating film 21 is formed on the source region 14 so as to be adjacent to the second contact plug 32 and surround the periphery thereof. Further, the second insulating film 22 is formed on the gate electrode 17 so as to be adjacent to the third contact plug 33 and surround the periphery thereof. A third insulating film 23 is formed on the main surface 10 a of the semiconductor substrate 10 so as to cover the first insulating film 21 and the second insulating film 22. As these insulating films 21 to 23, when the contact plug 30 is formed, the first insulating film 21 and the second insulating film 22 are appropriately selected from a combination of materials having a slower etching rate than the third insulating film 23. can do. That is, in the formation region of the contact plug 30 (32, 33) shallower than the first contact plug 31, the insulating films 22, 23 having a slower etching rate than the insulating film 21 in the formation region of the first contact plug 31 are disposed. ing. In this embodiment, since the anisotropic dry etching by fluorocarbon type such as CF ₄ (tetrafluorocarbon) is used for forming the contact plug 30, the silicon nitride film is used as the first insulating film 21 and the TEOS is used as the second insulating film 22. A BPSG film (or PSG film) is employed as the film and the third insulating film 23. Note that the first insulating film 21 and the second insulating film 22 may have the same structure as long as the gate electrode 17 is not abutted during etching. The third insulating film 23 may have a multilayer structure instead of a single layer.

  The insulating film 20 is formed with a plurality of contact plugs 30 that penetrate from the upper surface 20 a and are connected to elements formed on the semiconductor substrate 10. As the contact plug 30, three contact plugs 31 to 33 are connected to the LDMOS element. The first contact plug 31 corresponds to the first contact plug described in the claims, and the lower end extends to the base contact region 13 while penetrating the insulating film 20 (third insulating film 23) and the source region 12. It is installed. That is, it is connected to the source region 12 and the base contact region 13. The second contact plug 32 corresponds to the second contact plug recited in the claims, penetrates through the insulating film 20 (the third insulating film 23 and the first insulating film 21), and the lower end is the drain region. 14. The third contact plug 33 corresponds to the third contact plug recited in the claims, penetrates through the insulating film 20 (the third insulating film 23 and the second insulating film 22), and the lower end is the gate electrode. 17 is connected. In these contact plugs 31 to 33, as shown in FIG. 1, the depth in the vertical direction is deepest in the first contact plug 31 and shallowest in the third contact plug 33.

  In the present embodiment, the first contact plug 31 passes through the approximate center position of the source region 12 and is in contact with the approximate center position of the base contact region 13 in the left-right direction. Further, tungsten (W) plugs are adopted as all the contact plugs 30 including the contact plugs 31 to 33. That is, the diameter (hereinafter referred to as the upper end diameter) on the upper surface 20a of the insulating film 20 in the contact plug 30 is a fine diameter (for example, 0.5 μm or less). The upper end diameters of all the contact plugs 30 are substantially equal to each other. That is, the upper end diameters of the contact plugs 31 to 33 are substantially equal to each other. Reference numerals 41 to 43 shown in FIG. 1 indicate wirings arranged on the upper surface 20a of the insulating film 20 and connected to the upper ends of the contact plugs 31 to 33.

  The semiconductor device 100 configured as described above can be formed by, for example, a manufacturing method described below. FIG. 2 is a cross-sectional view for explaining a forming process up to an insulating film in the manufacturing process of the semiconductor device shown in FIG. FIG. 3 is a cross-sectional view showing a contact plug forming step in the manufacturing process of the semiconductor device shown in FIG.

  First, an element including an LDMOS element is formed on an N conductivity type (N) semiconductor substrate 10 having a main surface 10a by a known semiconductor process such as photolithography or ion implantation. In the present embodiment, as shown in FIG. 2, the LOCOS oxide film 15 is formed by a well-known LOCOS formation technique, and the gate insulating film 16 is formed on the main surface 10a of the semiconductor substrate 10 by, for example, thermal oxidation. Then, polycrystalline silicon is deposited on the LOCOS oxide film 15 and the gate insulating film 16, and after introducing impurities such as phosphorus, the gate electrode 17 is formed by patterning. Thereafter, as shown in FIG. 2, the gate electrode 17 is used as a mask by ion implantation to form a P conductivity type (P) base region 11 and an N conductivity type (N +) on the surface layer of the main surface 10a of the semiconductor substrate 10. Source region 12 and N conductivity type (N +) drain region 13 are formed. Further, by ion implantation (high acceleration implantation), a P contact type (P +) base contact region has a concentration peak below the source region 12 and at least partially overlaps the source region 12 in the left-right direction. 13 is formed. Note that the source region 12 can also be formed after the base contact region 13 is formed by ion implantation. Further, after the base region 11, the source region 12, the base contact region 13, and the drain region 14 are formed, the LOCOS oxide film 15, the gate insulating film 16, and the gate electrode 17 can be formed.

Next, the insulating film 20 is formed on the main surface 10a of the semiconductor substrate 10 using a CVD method or the like. In the present embodiment, the first insulating film 21 is selectively formed on the source region 14 as shown in FIG. 2 so as to cover the connection region with the second contact plug 32 in the source region 14. Further, the second insulating film 22 is selectively formed on the gate electrode 17 as shown in FIG. 2 so as to cover the connection portion of the gate electrode 17 with the third contact plug 33. And after forming these, the 3rd insulating film 23 is formed so that the main surface 10a whole region of the semiconductor substrate 10 may be covered. In the present embodiment, since the anisotropic dry etching based on a fluorocarbon such as CF ₄ (tetrafluorocarbon) is used for forming the contact plug 30, a silicon nitride film and a second insulating film 22 are used as the first insulating film 21. A TEOS film and a BPSG film (or PSG film) are formed as the third insulating film 23. Then, the insulating film 20 shown in FIG. 2 is formed by planarizing the surface of the third insulating film 23 by CMP or the like.

  Next, a plurality of contact plugs 30 penetrating the insulating film 20 from the upper surface 20a and connected to the element are formed. In this step, first, a mask (not shown) is formed on the upper surface 20a of the insulating film 20 by photolithography, and etching is performed through this mask. In the present embodiment, the diameters of the openings of the masks corresponding to the respective contact plugs 30 are made substantially equal, and all contact plugs 30 can be handled in the same process by anisotropic dry etching (specifically reactive ion etching). A contact hole is formed. That is, as shown in FIG. 3, the first contact hole 34 corresponding to the first contact plug 31, the second contact hole 35 corresponding to the second contact plug 32, and the third contact hole corresponding to the third contact plug 33. 35 is formed in the same process.

  Here, as described above, the first insulating film 21 is disposed on the source region 14, and the second insulating film 22 is disposed on the gate electrode 17. Therefore, the depth of the first contact hole 34 formed by etching only the region of the third insulating film 23 having a high etching rate as the insulating film 20 is defined as the first etching rate slower than that of the third insulating film 23 as the insulating film 20. The region including the insulating film 21 and the second insulating film 22 can be made deeper than the depths of the second contact hole 35 and the third contact hole 36 formed by etching. Thereby, when the second contact hole 35 reaches the source region 14 and the third contact hole 36 reaches the gate electrode 17, the first contact hole 34 penetrates the source region 12 together with the insulating film 20, and the base contact It can be in a state of reaching the region 13. In the present embodiment, each contact hole including the contact holes 34 to 36 has a forward tapered shape having a diameter that decreases toward the bottom side, but the shape is not limited to the above example. A vertical shape with a substantially constant diameter in the depth direction may be used, or a reverse taper shape with a larger diameter on the bottom side.

  After etching, tungsten (W) is grown in each contact hole including the contact holes 34 to 36, and CMP or etchback is performed as necessary to form a contact plug 30 in which W is embedded in each contact hole. To do. Thereafter, wirings 41 to 43, a protective film (not shown), and the like are formed by a known semiconductor process. Through the above steps, the semiconductor device 100 illustrated in FIG. 1 can be formed.

  Next, effects of the semiconductor device 100 and the manufacturing method thereof according to the present embodiment will be described. First, in the present embodiment, the source region 12 is formed in the surface layer on the main surface 10a side in the base region 11, and the base region is positioned below the source region 12 and at least partially overlaps the source region 12 in the left-right direction. A contact region 13 is formed. The first contact plug 31 extends to the base contact region 13 while penetrating the insulating film 20 and the source region 12, and serves as a common plug for the source region 12 and the base contact region 13. Therefore, even if manufacturing variation occurs, a contact area between the first contact plug 31 having a fine upper end diameter and the source region 12 is secured, thereby suppressing an increase in on-resistance (contact resistance) of the LDMOS element. Can do. In addition, since the contact area between the first contact plug 31 and the base contact region 13 can be secured, the potential of the base region is set to a predetermined potential (the same potential as the source region 12) to stabilize the operation of the LDMOS element. You can also. In particular, in the present embodiment, the first contact plug 31 penetrates substantially the center position of the source region 12 and contacts the substantially center position of the base contact region 13 in the left-right direction. The contact area between the plug 31 and the source region 12 and the base contact region 13 can be ensured.

  The base contact region 13 is formed at a position below the source region 12 and at least partially overlapping with the source region 12 in the left-right direction. That is, the source region 12 and the base contact region 13 are juxtaposed in the vertical direction. Therefore, in the left-right direction, the size in the left-right direction can be reduced as compared with the conventional configuration in which the source region 12 and the base contact region 13 are arranged in parallel. Furthermore, in the vertical direction, the source region 12 and the base contact region 13 are arranged in parallel, and the two regions 12 and 13 are connected to the first contact plug 31. That is, the contact plug is shared. Therefore, the physique in the left-right direction can be made smaller than when separate contact plugs are formed.

  From the above, since the LDMOS element shown in this embodiment can be miniaturized, that is, highly integrated, it can be combined with an IC (Integrated Circuit) in which memory cells and logic circuits are configured, and a control IC including a CMOS. It is suitable as a power IC.

  In addition, as the upper end diameter of the contact plug 30 is reduced, active species such as radicals are less likely to enter the hole, and the depth variation of the contact hole formed by etching increases. Therefore, when a plurality of types of contact plugs 30 having different upper end diameters are formed, even if the formation of some of the contact holes is completed, the contact holes having a smaller upper end diameter are formed only up to a predetermined depth. Something can happen. On the other hand, in this embodiment, since the upper end diameters of all the contact plugs 30 are made substantially equal, the influence of variations during etching is the same in each contact hole. Therefore, it becomes easy to ensure the electrical connection state between each contact plug 30 and the corresponding connection location in the element. In addition, the manufacturing process can be simplified.

  In the present embodiment, the configuration of the insulating film 20 is different depending on the depth of the contact plug 30 to be formed. Specifically, in the formation region of the contact plug 30 (32, 33) shallower than the first contact plug 31, the insulating films 22, 23 having a slower etching rate than the insulating film 21 in the formation region of the first contact plug 31. Is arranged. Therefore, as described above, it is possible to provide a difference in the depth of the contact plug 30 while making the upper end diameters of all the contact plugs 30 substantially equal to each other. Thereby, the electrical connection state of each contact plug 30 and the corresponding connection location in the element can be ensured.

  From the above, it is possible to provide a difference in the depth of the contact plugs 30 while making the upper end diameters of all the contact plugs 30 substantially equal to each other, so that CMOS elements and bipolar elements are integrated on the semiconductor substrate 10 together with the LDMOS elements. Also in the semiconductor device 100 that has been manufactured, the contact plugs 30 can be formed in the same process. Therefore, the manufacturing process can be simplified. In particular, the LDMOS element is suitable for integration with other elements such as CMOS from the viewpoint of process consistency.

  In the present embodiment, an example is shown in which the shape of the contact hole formed by anisotropic dry etching (reactive ion etching), that is, the shape of the contact plug 30 is a forward tapered shape having a smaller diameter toward the bottom side. . However, since the constituent materials are different between the insulating film 20 (first insulating film 23) and the semiconductor substrate 10, if the etching rate of the semiconductor substrate 10 is slower than that of the insulating film 20, as shown in FIG. The shape of the first contact plug 31 can be a step shape in which the diameter of the lower surface 20 b of the insulating film 20 is larger than the diameter of the main surface 10 a of the base region 12. For example, the higher the impurity concentration in the BPSG film (PSG film) constituting the third insulating film 23, the higher the etching rate, so that the difference in etching rate with the semiconductor substrate 10 increases, and the first contact plug 31 is The stepped shape can include a stepped portion 31a. As described above, when the step-shaped first contact plug 31 is employed, the contact area between the source region 12 and the first contact plug 31 can be increased while maintaining the same upper end diameter, so that the on-resistance (contact resistance) is increased. It can be further reduced. FIG. 4 is an enlarged cross-sectional view around the first contact plug showing a modification of the first contact plug. Note that when the first contact plug 31 has a stepped shape, the other contact plugs 30 also have a shape whose diameter has been expanded, similar to the portion of the insulating film 20 in the first contact plug 31.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. 5A and 5B are cross-sectional views showing a contact plug forming process in the manufacturing process of the semiconductor device according to the second embodiment, where FIG. 5A shows an anisotropic etching process and FIG. 5B shows an isotropic etching process. Show. FIG. 5 corresponds to FIG.

  Since the semiconductor device and the manufacturing method thereof according to the second embodiment are in common with the semiconductor device and the manufacturing method thereof according to the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be emphasized. I will explain it. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In the first embodiment, an example in which the first contact plug 31 (first contact hole 34) has a stepped shape as shown in FIG. 4 by anisotropic dry etching (reactive ion etching) only has been shown. . In contrast, in the present embodiment, anisotropic etching is first performed as shown in FIG. 5A when each contact hole is formed. As a result, a temporary contact hole 34a having a forward tapered shape having a diameter that reaches the base contact region 13 and has a smaller diameter toward the bottom side is formed. In addition, the code | symbol 50 shown to Fig.5 (a) is a mask which consists of photoresists, for example. Next, as shown in FIG. 5B, the insulating film 20 is selectively etched by performing isotropic etching with hydrofluoric acid or the like using the same mask 50. As a result, the portion of the insulating film 20 is expanded in the left-right direction. As shown in FIG. 5B, the shape of the first contact hole 34 is the same as the diameter of the lower surface 20 b of the insulating film 20. It can be set as the level | step difference shape made larger than the diameter in the surface 10a. When the first contact plug 31 has a stepped shape, the other contact plug 30 has a shape in which the upper end diameter is larger than the opening diameter of the mask 50, similarly to the portion of the insulating film 20 in the first contact plug 31. Become.

  Thus, also by the manufacturing method shown in this embodiment, the shape of the first contact plug 31 can be a stepped shape having the stepped portion 31a as shown in FIG. Therefore, the contact area between the source region 12 and the first contact plug 31 can be increased while maintaining the same upper end diameter, and the on-resistance (contact resistance) can be further reduced.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a cross-sectional view showing a contact hole forming step in the manufacturing steps of the semiconductor device according to the third embodiment. FIG. 7 is a cross-sectional view showing a base contact region forming step in the manufacturing process. 6 and 7 correspond to FIG.

  Since the semiconductor device manufacturing method according to the third embodiment is in common with the semiconductor device shown in the first embodiment and the manufacturing method thereof, the detailed description of the common parts is omitted below, and different parts are emphasized. Explained. In addition, the same code | symbol shall be provided to the element same as the element shown to said each embodiment.

  In the first embodiment, an example in which each contact hole including the first contact hole 34 is formed after the base contact region 13 is formed has been described. On the other hand, in the present embodiment, first, the P conductivity type (P) base region 11, the N conductivity type (N +) source region 12, and the N conductivity type (N +) are formed on the surface layer of the main surface 10 a of the semiconductor substrate 10. The drain regions 13 (not shown in FIG. 6) are respectively formed. Then, as shown in FIG. 6, before forming the base contact region 13, each contact hole (only the first contact hole 34 is shown in FIG. 6) is formed by, for example, anisotropic dry etching through the mask 50. To do. At this time, as shown in FIG. 6, the first contact hole 34 penetrates the source region 12, and the bottom of the first contact hole 34 is in the base region 11 and below the source region 12 (the base region 13 is later formed). It will be in the state extended to the site | part formed.

  Then, as shown in FIG. 7, a peak of concentration exists below the source region 12 by the ion implantation method using the same mask 50 and through the formed first contact hole 34. A P contact type (P +) base contact region 13 is formed so as to at least partially overlap the region 12. Thereafter, contact plugs 30 are formed by burying W in each contact hole, and wirings 41 to 43, a protective film (not shown) and the like are formed by a known semiconductor process.

  Although not shown, also in this embodiment, the configuration of the insulating film 20 is different depending on the depth of the contact plug 30 to be formed. Specifically, in the formation region of the contact plug 30 (32, 33) shallower than the first contact plug 31, the insulating films 22, 23 having a slower etching rate than the insulating film 21 in the formation region of the first contact plug 31. Is arranged. Even with such a manufacturing method, the semiconductor device 100 shown in FIG. 1 can be formed.

  In the present embodiment, ions are implanted through the first contact hole 34 to form the base contact region 13, so that the ion implantation need not be performed at high acceleration (high acceleration implantation may not be performed). Therefore, the formation time of the base contact region 13 can be shortened as compared with the manufacturing method shown in the first embodiment. In addition, since the base contact region 13 is formed after the first contact hole 34 is formed, the mask 50 can be shared, and the manufacturing process can be simplified.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view showing a base contact region forming step in the manufacturing steps of the semiconductor device according to the fourth embodiment. FIG. 8 corresponds to FIG.

  Since the semiconductor device and the manufacturing method thereof according to the fourth embodiment are often in common with the semiconductor device and the manufacturing method thereof shown in the above embodiment, the detailed description of the common parts will be omitted below, and different parts will be emphasized. Explained. In addition, the same code | symbol shall be provided to the element same as the element shown to said each embodiment.

  In the third embodiment, the first contact hole 34 penetrating the source region 12 is formed, and then the base contact region 13 is formed by the ion implantation method through the first contact hole 34. However, as shown in FIG. 7, the shape of the first contact hole 34 was a forward tapered shape having a diameter reduced toward the bottom side. Thus, in the case of a forward tapered shape or a vertical shape having a substantially constant diameter in the depth direction, a portion (wall surface portion) of the source region 12 in the first contact hole 34 during ion implantation to form the base contact region 13. It is also conceivable that ions are implanted into this, and this increases the on-resistance (contact resistance).

  Therefore, in the present embodiment, the insulating film 20 (third insulating film 23) in the region where the first contact plug 31 (first contact hole 34) is formed is an insulating material having a higher concentration of impurities added to the portion closer to the back surface 20b. It is a film. As such an insulating film, for example, BPSG or PSG can be employed. Therefore, when such an insulating film 20 is subjected to anisotropic dry etching, the higher the impurity concentration, the faster the etching rate. Therefore, as shown in FIG. The diameter of the semiconductor substrate 10 (inside the base region 11) is larger than the upper end diameter (the diameter of the upper surface 20a). When the first contact plug 31 has the above shape, the other contact plugs 30 have a reverse taper shape as in the portion of the insulating film 20 in the first contact plug 31.

  Therefore, if ion implantation is performed to form the base contact region 13 through the first contact hole 34 having such a shape, the upper wall surface of the first contact hole 34 becomes a wall as shown in FIG. Therefore, ions can be suppressed from being implanted into the portion (wall surface portion) of the source region 12 in the first contact hole 34. As a result, an increase in on-resistance (contact resistance) can be suppressed.

  In addition to the configuration shown in FIG. 8, ions can be suppressed from being implanted into the portion (wall surface portion) of the source region 12 in the first contact hole 34. For example, when each contact hole is formed, anisotropic etching is first performed using a mask 50 made of, for example, a photoresist as shown in FIG. 9A. Thus, a temporary contact hole 34b having a forward tapered shape with a smaller diameter is formed on the bottom side while reaching the portion where the base region 13 is formed later while penetrating the source region 12. Next, as shown in FIG. 9B, isotropic etching is performed using the same mask 50 to expand the diameter of the temporary contact hole 34b in the entire depth direction, and the first contact hole 34 having a forward tapered shape. And At this time, as shown in FIG. 9B, isotropic etching is performed until the diameter of the wall surface portion of the source region 12 in the first contact hole 34 becomes larger than the opening diameter of the mask 50. When the first contact plug 31 has the above-described shape, the other contact plugs 30 have an upper end diameter of each contact plug 30 larger than the opening diameter of the mask 50 as in the portion of the insulating film 20 in the first contact plug 31. The shape becomes wider. Then, as shown in FIG. 10, the base contact region 13 is formed through the first contact hole 34 by the ion implantation method using the same mask 50. At this time, since the mask 50 becomes a wall, it is possible to prevent ions from being implanted into a portion (wall surface portion) of the source region 12 in the first contact hole 34. As a result, an increase in on-resistance (contact resistance) can be suppressed. FIG. 9 is a cross-sectional view showing a manufacturing process of a modified example, where (a) shows an anisotropic etching process and (b) shows an isotropic etching process. FIG. 10 is a cross-sectional view showing the manufacturing process of the modification, and shows the base contact region forming process. 9 and 10 correspond to FIG.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In the present embodiment, an example of an LDMOS element is shown as the lateral insulated gate transistor element. However, a lateral IGBT element can also be employed.

  In the present embodiment, only an N-channel type LDMOS element is shown as an element configured on the semiconductor substrate 10. However, a configuration having only a P-channel type LDMOS element or a configuration having both an N-channel type and a P-channel type may be adopted. In the case of having a plurality of LDMOS elements as elements, the above-described configuration (the base contact region 13 below the source region 12) may be applied to at least one LDMOS element, but the above configuration is applied to more LDMOS elements. By doing so, the physique of the left-right direction can be reduced in size effectively.

  Further, in the case where a plurality of LDMOS elements are provided and both the N-channel type and the P-channel type are included, the above-described configuration may be employed only for either the N-channel type or the P-channel type. In general, the N-channel type can reduce the on-resistance as compared with the P-channel type, but has a low breakdown resistance. The P-channel type has a higher breakdown resistance than the N-channel type, but has a high on-resistance. Therefore, for example, when the above-described configuration is adopted only for the N channel type, it is possible to suppress an increase in the number of masks while improving the N channel type breakdown tolerance. For example, when the above configuration is adopted only for the P-channel type, it is possible to suppress an increase in the number of masks while reducing the on-resistance of the P-channel type.

  When the manufacturing method shown in the third embodiment or the fourth embodiment is applied, the impurity for forming the base contact region 13 is ion-implanted through each contact hole. Therefore, the impurity concentration in a region other than the base contact region 13 may be set in advance so that a predetermined impurity concentration can be secured in a state where the impurity is introduced. However, the above configuration (the base contact region 13 below the source region 12) is applied to both the N-channel type LDMOS device (horizontal insulated gate transistor device) and the P-channel type LDMOS device (lateral insulated gate transistor device). In the manufacturing method shown in the third embodiment or the fourth embodiment, it is difficult to set the concentration of each base contact region 13. Therefore, in this case, the manufacturing method shown in the first embodiment may be applied.

  In the present embodiment, the configuration of the insulating film 20 is different depending on the depth of the contact plug 30 to be formed, so that the upper end diameters of the contact plugs 30 are substantially equal to each other. An example in which contact plugs 30 of different sizes are formed has been shown. However, as shown in FIG. 11, even if the upper end diameters of the contact plugs 30 are different from each other, the structure of the insulating film 20 in the formation region of the contact plugs 30 is made of the same insulating film 24. Contact plugs 30 having different depths can also be formed. However, each contact plug 30 has a fine diameter as described above, and it is difficult to provide a large difference in depth only by the difference in the upper end diameter. Therefore, preferably, as shown in the present embodiment, the configuration of the insulating film 20 may be made different depending on the depth of the contact plug 30 to be formed. FIG. 11 is a cross-sectional view showing another modification.

1 is a cross-sectional view showing a schematic configuration of a part of an LDMOS element formation region in a semiconductor device according to a first embodiment. It is sectional drawing for demonstrating the formation process to an insulating film among the manufacturing processes of the semiconductor device shown in FIG. FIG. 7 is a cross-sectional view showing a contact plug forming step in the manufacturing process of the semiconductor device shown in FIG. 1. It is an expanded sectional view around the 1st contact plug which shows the modification of the 1st contact plug. It is sectional drawing which shows the formation process of a contact plug among the manufacturing processes of the semiconductor device which concerns on 2nd Embodiment, (a) has shown the anisotropic etching process, (b) has shown the isotropic etching process. It is sectional drawing which shows a contact hole formation process among the manufacturing processes of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows a base contact area | region formation process among manufacturing processes. It is sectional drawing which shows a base contact area | region formation process among the manufacturing processes of the semiconductor device which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing process of a modification, (a) shows the anisotropic etching process, (b) has shown the isotropic etching process. It is sectional drawing which shows the manufacturing process of a modification, and has shown the base contact area | region formation process. It is sectional drawing which shows the other modification example.

Explanation of symbols

10 ... Semiconductor substrate (semiconductor layer)
11 ... Base region 12 ... Source region (first high concentration region)
13 ... base contact region 20 ... insulating film 20a ... upper surface 21 ... first insulating film 22 ... second insulating film 23 ... third insulating film 30 ... contact plug 31 ..First contact plug (first contact plug)

Claims (3)

An element forming step of forming an element including at least a lateral insulated gate transistor element with respect to the first conductivity type semiconductor layer having a main surface, and an insulating film formed on the main surface of the semiconductor layer penetrating from the same surface; A method of manufacturing a semiconductor device comprising a plug forming step of forming a plurality of contact plugs connected to the element,
As the element forming step, impurities are introduced from the main surface side by ion implantation into the semiconductor layer in which the base region of the second conductivity type opposite to the first conductivity type is formed on the surface layer on the main surface side. A step of forming a first conductivity type first high concentration region on a surface layer in the base region; and after the formation of the first high concentration region, the insulating film is formed on the semiconductor layer and etched. The diameter of the insulating film on the surface opposite to the main surface of the semiconductor layer is substantially equal, and the first high-concentration region in the base region from the insulating film penetrates the first high-concentration region. A step of forming a plurality of contact holes including a first contact hole that reaches a region below the main surface, and after the formation of the contact hole, an ion implantation method is used to advance the contact hole through the contact hole. Impurities are introduced into the semiconductor layer, and are in the base region and in a direction substantially perpendicular to the main surface of the semiconductor layer, below the first high concentration region and below the main surface, and the semiconductor layer Forming a second conductivity type base contact region having an impurity concentration higher than that of the base region at a position at least partially overlapping with the first high concentration region in a direction along the main surface of
In the plug forming step, a plurality of contact plugs including a first contact plug in contact with the first high concentration region and the base contact region are formed by embedding a conductive member in the contact hole,
In the step of forming the contact hole, as the insulating film, an insulating film having a slower etching rate than the insulating film in the first contact hole forming region is formed in the contact hole forming region shallower than the first contact hole. Is selectively formed . A method for manufacturing a semiconductor device. The step of forming the contact hole is characterized in that an insulating film having a higher concentration of impurities added to a region closer to the main surface of the semiconductor layer is formed in the formation region of the first contact plug. 2. A method for manufacturing a semiconductor device according to 1. In the step of forming the contact hole, after the anisotropic etching, the insulating film and the semiconductor layer are isotropically etched using the same mask as the anisotropic etching to form the first contact hole And
In the step of forming the base contact region, using the mask by ion implantation, according to claim 1, characterized in that to form the base contact region in the semiconductor layer through the first contact hole A method for manufacturing a semiconductor device.

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