CN102130060B - Method for producing high-voltage grid drive chip for directly driving power device - Google Patents
Method for producing high-voltage grid drive chip for directly driving power device Download PDFInfo
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Abstract
The invention discloses a method for producing a high-voltage grid drive chip for directly driving a power device. By adopting a high-voltage junction isolating process, a high-voltage side drive control module is isolated from a low-voltage side drive control module; on the basis of the PN junction isolation in the conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) transistor process, a surface electric field reducing region is formed on the surface of a PN junction; a capacitive voltage divider is formed by using two layers of polysilicon; the distribution of an electric field on the surface of the PN junction is effectively changed; the high-voltage isolation of a high-voltage transverse DMOS (Double-Diffused Metal Oxide Semiconductor) transistor is formed; and a high-voltage N type DMOS transistor is obtained by forming a P type lightly-doped region. Compared with the conventional transverse DMOS transistor, the voltage resistant requirement of over 700V can be met by additionally arranging a P type surface electric field reducing region structure and a dual-layer polysilicon capacitor structure; and meanwhile, the production method has concise work procedures and lower cost; and a high-voltage grid drive circuit device for directly driving the power device can be formed by only needing 13 structure levels.
Description
Technical field
The present invention relates to a kind of preparation technology of semiconductor chip, especially relate to a kind of preparation method who drives chip for the high-voltage grid of direct driving power device.
Background technology
High-voltage grid drives chip and also claims power integrated circuit (PIC, POWER INTERGARTED CIRCUIT), and it is the product that the power electronic device technology combines with microelectric technique, is the key element of electromechanical integration.High-voltage grid drives being of wide application of chip, as is applied to electric ballast, motor driving, light modulation, various power modules etc.
The peripheral circuits such as power device and drive circuit thereof, protective circuit, interface circuit are integrated on one or several chip, have just made power model.Along with the application of power model is more and more extensive, power model needs development by simple Trigger Function to multi-functional application gradually, as adopt multi-core encapsulation module (MCM) that power integrated circuit and power semiconductor or passive component are encapsulated in the same packaging body, form power model; Also just like adopting simple Ji Dao isolation, high-voltage grid is driven chip and power device package in same packaging body, form power model, reach the purpose that reduces the power model volume, improves functional reliability.What early stage drive circuit adopted is the discrete device scheme, because the discrete device scheme needs a plurality of elements, integrated level is low, reliability is not high yet, gradually the scheme that is integrated drive circuit substitutes, but early stage integrated drive electronics scheme is because its preparation technology can't realize high pressure, therefore, early stage integrated drive electronics can not directly drive high voltage power device, need to increase a transformer during application and could realize identical function.
Development along with power semiconductor technology and stand CMOS technical compatibility, adopt the high pressure isolation technology, high-pressure side drive control module, low-pressure side drive control module and level shift module be integrated in the same chip form high-voltage grid and drive chip and become possibility, so the high-voltage grid of the final technical development direct driving power device that still, function higher take integrated level is more powerful drives chip as main.Drive in the chip at high-voltage grid, the low-pressure side drive control module is worked under conventional voltage, as the control signal part; The high-pressure side drive control module mainly comprises the high voltage control signal part, control high-pressure side signal; The level shift module considers that then the low-pressure side control signal transmits to the controlled area, high-pressure side, thereby when realizing these functions, following two the aspect problems of main consideration: be the isolating problem of high-pressure side drive control module and low-pressure side drive control module on the one hand, from the technology angle, high voltage isolation techniques is mainly divided three kinds of PN junction isolation, medium isolation and self-isolations, self-isolation technique is the simplest, but leakage current is large; Medium isolation cost is higher, complex procedures, difficult the realization; The advantage of PN junction isolation technology is that operation is simple, cost is low, therefore in stand CMOS, mostly adopt the PN junction isolation technology, but the basic principle according to the PN junction puncture, its withstand voltage breakdown point is generally in planar junction, and occurs in the surface of knot, and PN junction is punctured in advance, cause the demand that does not reach design, thereby cause in stand CMOS, can't realizing the high pressure more than tens volts; Be exactly on the other hand the high tension apparatus (being the lateral DMOS pipe) of realizing the high-pressure side drive control module be on the basis of conventional cmos device technology, by increasing RESURF zone (RESURF, be called for short and fall the place) and P type lightly doped region (be called for short the P type and gently mix the district), the N-type lateral dmos device structure formed.
Summary of the invention
Technical problem to be solved by this invention provides the preparation method that a kind of high-voltage grid that can produce the direct driving power device of 700 volts of high pressure drives chip.
The present invention solves the problems of the technologies described above the technical scheme that adopts: a kind of preparation method who drives chip for the high-voltage grid of direct driving power device is characterized in that may further comprise the steps:
1. selection: select the crystal orientation be (100), resistivity be the P type silicon chip of 40～60 Ω cm as original material, the N-type silicon chip of selection phosphorus doping is as epitaxial material; Make substrate layer by original material, make double-deck epitaxial loayer by epitaxial material, epitaxial loayer comprises bottom epitaxial loayer and top layer epitaxial loayer, and substrate layer, bottom epitaxial loayer and top layer epitaxial loayer be successively growth from the bottom to top;
2. prepare P type area of isolation, detailed process is:
2.-1, be the silicon dioxide of 900～1100nm in top layer epitaxial loayer growth a layer thickness, then apply one deck lithographic mask layer at silicon dioxide; 2.-2, utilize mask aligner to open area of isolation for isolated high-voltage side drive control module and low-pressure side drive control module in lithographic mask layer, then use corrosive liquid to remove the silicon dioxide of area of isolation; 2.-3 be that the silicon dioxide of 60～80nm is as implant blocking layer in area of isolation growth a layer thickness; 2.-4 be 9.0E15/cm to area of isolation isolation implantation dosage,
2And energy is the boron ion of 50Kev; 2.-5, using corrosive liquid to remove thickness is the silicon dioxide of 500～600nm; 2.-6, in oxidation furnace, advance area of isolation, advancing temperature is 1200 ℃, the propelling time is 100～120 minutes, then carries out wet-oxygen oxidation, is the silicon dioxide of 250nm in area of isolation growth a layer thickness, forms P type area of isolation;
3. prepare P well area and P type and reduce electric field region, detailed process is:
3.-1, in the surface of top layer epitaxial loayer coating one deck lithographic mask layer, then utilize mask aligner to open the P well area and the P type reduces electric field region in lithographic mask layer, re-use corrosive liquid and remove the silicon dioxide that P well area and P type reduce electric field region; 3.-2, reducing a layer thickness of growing respectively on the electric field region in P well area and P type is the silicon dioxide of 80～90nm; 3.-3 be 6.6E12/cm to P well area isolation implantation dosage,
2And energy is the boron ion of 80Kev; 3.-4, again in the surface of top layer epitaxial loayer coating one deck lithographic mask layer, then utilize mask aligner to open the P type and reduce lithographic mask layer on the electric field region, reducing the electric field region implantation dosage to the P type again is 3.4E12/cm
2And energy is the boron ion of 80Kev; 3.-5, utilize removing of photoresist by plasma equipment to remove the lip-deep lithographic mask layer of top layer epitaxial loayer; 3.-6, in oxidation furnace, advance P well area and P type to reduce electric field region, advancing temperature is 1200 ℃, the propelling time is 600～720 minutes, then carries out wet-oxygen oxidation, is the silicon dioxide of 1000～1200nm at P well area and P type reduction electric field region growth a layer thickness respectively;
4. prepare the P type heavily doped region of high pressure lateral DMOS pipe, detailed process is:
4.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner to open P type heavily doped region in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P type heavily doped region; 4.-2 be the silicon dioxide of 60～80nm in P type heavily doped region growth a layer thickness; 4.-3 be 3.0E14/cm to P type heavily doped region implantation dosage,
2And energy is the boron ion of 80Kev; 4.-4, inject the lip-deep lithographic mask layer that finishes rear removal top layer epitaxial loayer; 4.-5, in oxidation furnace, advance P type heavily doped region;
5. prepare polycrystalline resistor and polycrystalline electric capacity, detailed process is:
5.-1, to utilize mode deposit a layer thickness on the surface of top layer epitaxial loayer of cryochemistry vapour deposition be the polysilicon of 600～800nm, as the ground floor polysilicon; 5.-2, implantation dosage is 3.2E14/cm in the ground floor polysilicon
2And energy is that the boron ion of 80Kev carries out polysilicon doping; 5.-3, utilize lithographic mask layer to form the bottom crown of polycrystalline resistor and polycrystalline electric capacity; 5.-4, in oxidation furnace, carry out polysilicon oxidation, growth a layer thickness is the silicon dioxide of 600～700nm, as the capacitor dielectric layer;
6. prepare active area and the polysilicon gate of high pressure lateral DMOS pipe and conventional cmos pipe, detailed process is:
6.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner to open the active area of active device in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed active area; 6.-2, at active area growth one deck grid oxygen; 6.-3, on grid oxygen deposit one deck polysilicon, as second layer polysilicon, form top crown and the polygate electrodes of polycrystalline electric capacity;
7. prepare the P type lightly doped region of high pressure lateral DMOS pipe, detailed process is:
7.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner to open P type lightly doped region at photoresist mask layer, re-use the silicon dioxide that corrosive liquid is removed P type lightly doped region; 7.-2 be the silicon dioxide of 60～80nm in P type lightly doped region growth a layer thickness; 7.-3 be 7.0E13/cm to P type lightly doped region implantation dosage,
2And energy is the boron ion of 80Kev; 7.-4 utilize plasma degumming machine to remove the lip-deep lithographic mask layer of top layer epitaxial loayer after, injection finishes; 7.-5, isolation advances P type lightly doped region in oxidation furnace;
8. prepare source electrode and the drain electrode of conventional cmos pipe, detailed process is:
8.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner on lithographic mask layer, to open respectively N-type source/drain region and the P type source/drain region of CMOS pipe, re-use the silicon dioxide that corrosive liquid is removed N-type source/drain region and P type source/drain region; 8.-2 be 5.0E15/cm to N-type source/drain region implantation dosage,
2And energy is the arsenic ion of 60Kev; 8.-3, the drain region implantation dosage to N-type source/drain region is 6.0E12/cm
2And energy is the phosphorus impurities of 120Kev, forms N-type drain region lightly doped region; 8.-4, the drain region implantation dosage to P type source/drain region is 7.0E14/cm
2And energy is the boron ion of 50Kev.
The thickness of described bottom epitaxial loayer is 2.0～4.5 μ m, and the resistivity of described bottom epitaxial loayer is 0.5～1.2 Ω cm, and the thickness of described top layer epitaxial loayer is 5.0～10.0 μ m, and the resistivity of described top layer epitaxial loayer is 2.5～3.15 Ω cm.
Described step is 900 ℃ in the growth temperature of area of isolation growth silicon dioxide in 2.-3, and growth time is 20～30 minutes; Described step 2.-6 in the temperature of wet-oxygen oxidation be 1050 ℃, the time of wet-oxygen oxidation is 18～25 minutes.
The growth temperature that described step reduces the silicon dioxide of growing respectively on the electric field region in P well area and P type in 3.-2 is 900 ℃, and growth time is 30 minutes; Described step 3.-6 in the temperature of wet-oxygen oxidation be 1050 ℃, the time of wet-oxygen oxidation is 18～25 minutes.
Described step is 900 ℃ in the growth temperature of P type heavily doped region growth silicon dioxide in 4.-2, and growth time is 20 minutes; Described step 4.-5 in isolation to advance the propelling temperature of P type heavily doped region be 1050 ℃, the propelling time is 50～60 minutes.
The thickness of the grid oxygen that described step is grown at active area in 6.-2 is 78～82nm, and growth temperature is 920 ℃; Described step 6.-3 on grid oxygen the thickness of the polysilicon of deposit be 500～600nm.
Described step is 900 ℃ in the growth temperature of P type lightly doped region growth silicon dioxide in 7.-2, and growth time is 20 minutes; Described step 7.-5 in isolation to advance the propelling temperature of P type lightly doped region be 1175 ℃, the propelling time is 45 minutes.
The described step 7. square resistance of the middle P type lightly doped region that forms is 450～630 Ω/.
Compared with prior art, the invention has the advantages that by adopting high voltage junction isolation technology (HVJI) that high-pressure side drive control module and low-pressure side drive control module are kept apart, and on the conventional cmos plumber plants the basis of PN junction isolation, by forming RESURF (RESURF on the PN junction surface, be called for short and fall the place) zone, utilize two-layer polysilicon (being ground floor polysilicon and second layer polysilicon) to form capacitor voltage divider, effectively changed the PN junction surface electric field distribution, formed the high pressure isolation of high pressure lateral DMOS pipe, again by forming P type lightly doped region (be called for short the P type and gently mix the district), prepare high-voltage N type transverse DMOS pipe, compare with conventional lateral DMOS pipe, reduce electric field region structure and double level polysilicon capacitance structure by increasing the P type, can reach the above requirement of withstand voltage of 700V; This preparation method operation is succinct simultaneously, cost is lower, only needs 13 block structure levels just can form the high-voltage grid drive circuit device of direct driving power device; And adopted the N/N-double epi process during technological design, and satisfying under the withstand voltage requirement of 700V, reduce the extension gross thickness, increase the impurity energy degree of lower floor's extension, reduced the horizontal proliferation of high voltage junction.
Description of drawings
Fig. 1 is the high voltage junction isolation structure generalized section that high-voltage grid drives chip (PIC);
Fig. 2 is the structural profile schematic diagram of high pressure lateral DMOS pipe;
Fig. 3 is the position view of substrate layer and epitaxial loayer;
Fig. 4 is the process schematic diagram of preparation P type area of isolation;
Fig. 5 reduces the process schematic diagram in electric field (RESURF) zone for preparation P well area and P type;
Fig. 6 is the process schematic diagram of the P type heavily doped region of preparation high pressure lateral DMOS pipe;
Fig. 7 is the process schematic diagram of preparation polycrystalline resistor;
Fig. 8 is the process schematic diagram of preparation polycrystalline electric capacity
Fig. 9 is preparation high pressure lateral DMOS pipe and the active area of conventional cmos pipe and the process schematic diagram of polysilicon gate;
Figure 10 is the process schematic diagram of the P type lightly doped region of preparation high pressure lateral DMOS pipe;
Figure 11 is the process schematic diagram of preparation conventional cmos pipe source electrode and drain electrode.
Embodiment
Embodiment is described in further detail the present invention below in conjunction with accompanying drawing.
Embodiment one:
A kind of preparation method who drives chip for the high-voltage grid of direct driving power device that the present invention proposes, it is that high-pressure process and conventional CMOS process compatible are in the same place, on the basis of using conventional PN junction isolation, form the P type by dopant implant boron ion at the N-type epitaxial loayer and reduce electric field (RESURF) zone, use two-layer polysilicon (being ground floor polysilicon and second layer polysilicon) to form a series of capacitor voltage dividers on the surface of PN junction simultaneously, as shown in Figure 1, when circuit connects, make the bottom crown ground connection of the capacitor voltage divider of outermost end, the top crown of the most inboard capacitor voltage divider connects high potential, so effectively changed the PN junction surface field, change the power line direction on PN junction surface, help to reduce the electric field on isolation PN junction surface.Simultaneously when design, consider the edge effect that PN junction punctures, can be designed to ring-like during the high pressure isolation design or with the racetrack structure of circular corner, minimum radius size is not less than 100 μ m.
The preparation method that high-voltage grid of the present invention drives chip mainly may further comprise the steps:
1. selection: selecting the crystal orientation is that (100), resistivity are that the P type silicon chip of 40 Ω cm is as original material, select the N-type silicon chip of phosphorus doping as epitaxial material, make substrate layer 1 by original material, the double-deck N-type epitaxial loayer 2 that direct growth is made by epitaxial material on substrate layer, as shown in Figure 3, epitaxial loayer 2 comprises bottom epitaxial loayer 2a and top layer epitaxial loayer 2b, and substrate layer 1, bottom epitaxial loayer 2a and top layer epitaxial loayer 2b be successively growth from the bottom to top.
At this, the thickness of bottom epitaxial loayer 2a is 2.0～4.5 μ m, and the resistivity of bottom epitaxial loayer 2a is 0.5～1.2 Ω cm, and the thickness of top layer epitaxial loayer 2b is 5.0～10.0 μ m, and the resistivity of top layer epitaxial loayer 2b is 2.5～3.15 Ω cm; In actual design process, can be 3.0 μ m with the Thickness Design of bottom epitaxial loayer 2a, the resistivity of bottom epitaxial loayer 2a is designed to 0.86 Ω cm, and the Thickness Design of top layer epitaxial loayer 2b is 8.0 μ m, and the resistivity of top layer epitaxial loayer 2b is designed to 3.0 Ω cm.The present invention adopts the double-deck epitaxial structure of variable concentrations, be that bottom epitaxial loayer 2a adopts low resistivity, can satisfy like this requirement of withstand voltage of high pressure lateral DMOS pipe, top layer epitaxial loayer 2b adopts higher resistivity, then can satisfy preferably the requirement of conventional cmos pipe, effectively reduce the gain of parasitic NPN transistor.
2. adopt high voltage junction isolation technology (HVJI) preparation P type area of isolation, as shown in Figure 4, its detailed process is as follows:
2.-1, be the silicon dioxide of 900nm in top layer epitaxial loayer 2b growth a layer thickness, apply one deck lithographic mask layer at silicon dioxide; 2.-2, utilize mask aligner to open area of isolation for isolated high-voltage side drive control module and low-pressure side drive control module in lithographic mask layer, then use corrosive liquid to remove the silicon dioxide of area of isolation; 2.-3, use oxidation furnace in area of isolation growth a layer thickness as the silicon dioxide of 60nm as implant blocking layer, growth temperature is 900 ℃, growth time is 20 minutes; 2.-4 be 9.0E15/cm to area of isolation isolation implantation dosage,
2(namely 9.0 * 10
15/ cm
2) and energy be the boron ion B of 50Kev
11+; 2.-5, use corrosive liquid to remove thickness and be the silicon dioxide of 500nm; 2.-6, in oxidation furnace, advance area of isolation, advancing temperature is 1200 ℃, the propelling time is 100 minutes, then carries out 18 minutes wet-oxygen oxidation under 1050 ℃ of temperature, is the silicon dioxide of 250nm in area of isolation growth a layer thickness.By above step, just formed P type area of isolation 3.
At this, after P type area of isolation 3 formed, epitaxial loayer 2(comprised top layer epitaxial loayer 2b and bottom epitaxial loayer 2a) be divided into high-pressure side part and low-pressure side part.
3. prepare P well area and P type and reduce electric field region, as shown in Figure 5, its detailed process is as follows:
3.-1, in the surface of top layer epitaxial loayer 2b coating one deck lithographic mask layer, then utilize mask aligner to open P well area 11 and P type reduction electric field region 4 in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P well area 11 and P type reduction electric field region 4; 3.-2, to reduce a layer thickness of growing respectively on the electric field region 4 in P well area 11 and P type be the silicon dioxide of 80nm, growth temperature is 900 ℃, growth time is 30 minutes; 3.-3 be 6.6E12/cm to P well area 11 isolation implantation dosages,
2And energy is the boron ion of 80Kev; 3.-4, again in the surface of top layer epitaxial loayer 2b coating one deck lithographic mask layer, then utilize mask aligner to open the P type and reduce lithographic mask layer on the electric field region 4, reducing electric field region 4 implantation dosages to the P type again is 3.4E12/cm
2And energy is the boron ion of 80Kev; 3.-5, utilize removing of photoresist by plasma equipment to remove the lip-deep lithographic mask layer of top layer epitaxial loayer 2b; 3.-6, in oxidation furnace, advance P well area 11 and P type to reduce electric field region 4, advancing temperature is 1200 ℃, the propelling time is 600 minutes, then carry out 18 minutes wet-oxygen oxidation under 1050 ℃ of temperature, reducing electric field region 4 growth a layer thickness in P well area 11 and P type respectively is the silicon dioxide of 1000nm.
4. prepare the P type heavily doped region of high pressure lateral MOS pipe, as shown in Figure 6, its preparation process is similar to the preparation process of P well area, and its detailed process is as follows:
4.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open P type heavily doped region 9 in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P type heavily doped region 9; 4.-2, be the silicon dioxide of 60nm in P type heavily doped region 9 growth a layer thickness, growth temperature is 900 ℃, growth time is 20 minutes; 4.-3 be 3.0E14/cm to P type heavily doped region 9 implantation dosages,
2And energy is the boron ion of 80Kev; 4.-4, inject the lip-deep lithographic mask layer that finishes rear removal top layer epitaxial loayer 2b; 4.-5, in oxidation furnace, advance P type heavily doped region 9, advancing temperature is 1050 ℃, the propelling time is 50 minutes.
5. prepare polycrystalline resistor and polycrystalline electric capacity, the preparation process of polycrystalline resistor as shown in Figure 7, the preparation process of polycrystalline electric capacity as shown in Figure 8, detailed process is as follows:
5.-1, utilize mode deposit a layer thickness on the surface of top layer epitaxial loayer 2b of cryochemistry vapour deposition to be the polysilicon of 600nm, as ground floor polysilicon 6; 5.-2 be 3.2E14/cm to ground floor polysilicon 6 interior implantation dosages,
2And energy is that the boron ion of 80Kev carries out polysilicon doping; 5.-3, utilize lithographic mask layer to form the bottom crown of polycrystalline resistor and polycrystalline electric capacity; 5.-4, in oxidation furnace, carry out polysilicon oxidation, growth a layer thickness is the silicon dioxide of 600nm, as capacitor dielectric layer 14.
6. the active area and the polysilicon gate that prepare high pressure lateral DMOS pipe and conventional cmos pipe, as shown in Figure 9, its detailed process is as follows:
6.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open the active area of active device in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed active area; 6.-2, be the grid oxygen of 78nm in active area growth a layer thickness, growth temperature is 920 ℃; 6.-3, deposit a layer thickness is the polysilicon of 500nm on grid oxygen, as second layer polysilicon 5, forms top crown and the polygate electrodes of polycrystalline electric capacity.
7. prepare the P type lightly doped region of high pressure lateral DMOS pipe, as shown in figure 10, its detailed process is as follows:
7.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open P type lightly doped region 10 at photoresist mask layer, re-use the silicon dioxide that corrosive liquid is removed P type lightly doped region 10; 7.-2, be the silicon dioxide of 60nm in P type lightly doped region 10 growth a layer thickness, growth temperature is 900 ℃, growth time is 20 minutes; 7.-3 be 7.0E13/cm to P type lightly doped region implantation dosage,
2And energy is the boron ion of 80Kev; 7.-4 utilize plasma degumming machine to remove the lip-deep lithographic mask layer of top layer epitaxial loayer 2b after, injection finishes; 7.-5, isolation advances P type lightly doped region 10 in oxidation furnace, advancing temperature is 1175 ℃, and the propelling time is 45 minutes, and the square resistance of the P type lightly doped region 10 of formation is about 450～630 Ω/.
8. the source electrode and the drain electrode that prepare the conventional cmos pipe, as shown in figure 11, its detailed process is as follows:
8.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner on lithographic mask layer, to open respectively CMOS pipe N-type source/drain region 15 and P type source/drain region, re-use the silicon dioxide that corrosive liquid is removed N-type source/drain region and P type source/drain region; 8.-2 be 5.0E15/cm to N-type source/drain region 15 implantation dosages,
2And energy is the arsenic ion of 60Kev; 8.-3, in order to form N-type drain region light-dope structure, do not use mask plate, be 6.0E12/cm to the drain region implantation dosage of N-type source/drain region 15
2And energy is the phosphorus impurities of 120Kev, forms N-type drain region lightly doped region 16; 8.-4, the drain region implantation dosage to P type source/drain region is 7.0E14/cm
2And energy is the boron ion of 50Kev.
In this specific embodiment, the 6:1 hydrofluoric acid corrosive liquid (BOE with buffer that corrosive liquid can adopt semiconductor technology often to use, Buffered oxide etch), this volume ratio with water and hydrofluoric acid in the 6:1 hydrofluoric acid corrosive liquid of buffer is 6:1, simultaneously in order to stablize corrosion rate, reduce the generation of polymer, add ammoniacal liquor as buffer.
After the above-mentioned processing step, high-voltage grid drives chip manufacturing proces and substantially finishes, and by forming contact hole, metal deposit, forming metal interconnecting wires, forms at last chip surface passivation protection layer again, finishes the whole preparation technology that high-voltage grid drives chip.
The inventive method is on the stand CMOS basis, by injecting N-type boron impurities ion B
11+, form the P type and reduce electric field region, between source, drain region, form and the same secondary terminal of high pressure isolation.By increasing implanted dopant boron ion B
11+Form P type lightly doped region, P type lightly doped region and N-type heavy-doped source/drain region forms the raceway groove of lateral DMOS pipe, only increase thus the P type and reduce electric field level and two levels of P type light dope level, just can form the lateral dmos device structure with the RESURF structure, compare with general BCD technique, this preparation method technological process is shorter, the processes cycle is short, mask aligner only needs 13 levels just can finish, the manufacturing process of employing and stand CMOS compatibility, technical maturity is produced and is easy to reach volume production.
In order to improve the threshold value of parasitic CMOS pipe, reduce the anti-latch up effect of CMOS pipe, this preparation method has adopted the N/N-double epi process, satisfying under the withstand voltage requirement of 700V, reduce the extension gross thickness, increased the impurity concentration of bottom epitaxial loayer, shortened activity time.
High-voltage grid that the inventive method prepares drives the devices such as CMOS pipe that chip comprises 700V high pressure lateral DMOS pipe, 25V, NPN transistor, resistance, electric capacity, and its core devices is high pressure lateral DMOS pipe, and its cross-sectional view as shown in Figure 2.High pressure lateral DMOS pipe comprises that the P type reduces the zones such as electric field region, P type lightly doped region, P type heavily doped region, N-type heavily doped region.N-type heavily doped region and P type lightly doped region form the raceway groove of high pressure lateral DMOS pipe jointly.When device is operated under the normal voltage condition, the P type reduces the electric field region right-hand member and forms anti-partially PN junction, increase along with voltage, the depletion region that increases so that surface voltage in this rapid decline, RESURF according to RESURF is theoretical, the effect of field plate makes puncture voltage not occur in the surface of device, and also forms anti-partially PN junction at P type substrate layer and N-type epitaxial loayer place simultaneously, and the puncture of secondary terminal mainly occurs in the PN junction place of substrate/extension in the body.
In the present invention, high pressure lateral DMOS pipe is equivalent to a series of electric capacity and a reverse PN is formed in parallel.The high pressure size is definite by capacitor dielectric thickness and electric capacity quantity, and for example, according to test, medium is between electric capacity
During the left and right sides, the withstand voltage of its electric capacity is about 200V, for the purpose of reliable, is designed with redundancy, so the high-voltage LDMOS pipe of 700V is the series connection of 6 electric capacity, the high-voltage LDMOS pipe of 1200V is the series connection of 12 electric capacity.The same in its structure and connection and the high pressure isolation structure, ground floor gate polysilicon ring is connected to source, and the 4th layer of polysilicon grating ring connects drain terminal, and high-voltage N type transverse DMOS structure is a round or racetrack structure.
Embodiment two:
The present embodiment and embodiment one are basic identical, and the preparation process of the present embodiment is specific as follows:
1. selection: selecting the crystal orientation is that (100), resistivity are that the P type silicon chip of 60 Ω cm is as original material, select the N-type silicon chip of phosphorus doping as epitaxial material, make substrate layer 1 by original material, the double-deck N-type epitaxial loayer 2 that direct growth is made by epitaxial material on substrate layer, as shown in Figure 3, epitaxial loayer 2 comprises bottom epitaxial loayer 2a and top layer epitaxial loayer 2b, and substrate layer 1, bottom epitaxial loayer 2a and top layer epitaxial loayer 2b be successively growth from the bottom to top.
2. adopt high voltage junction isolation technology (HVJI) preparation P type area of isolation, as shown in Figure 4, its detailed process is as follows:
2.-1, be the silicon dioxide of 1100nm in top layer epitaxial loayer 2b growth a layer thickness, apply one deck lithographic mask layer at silicon dioxide; 2.-2, utilize mask aligner to open area of isolation for isolated high-voltage side drive control module and low-pressure side drive control module in lithographic mask layer, then use corrosive liquid to remove the silicon dioxide of area of isolation; 2.-3, use oxidation furnace in area of isolation growth a layer thickness as the silicon dioxide of 80nm as implant blocking layer, growth temperature is 900 ℃, growth time is 30 minutes; 2.-4 be 9.0E15/cm to area of isolation isolation implantation dosage,
2(namely 9.0 * 10
15/ cm
2) and energy be the boron ion B of 50Kev
11+; 2.-5, use corrosive liquid to remove thickness and be the silicon dioxide of 600nm; 2.-6, in oxidation furnace, advance area of isolation, advancing temperature is 1200 ℃, the propelling time is 120 minutes, then carries out 25 minutes wet-oxygen oxidation under 1050 ℃ of temperature, is the silicon dioxide of 250nm in area of isolation growth a layer thickness.By above step, just formed P type area of isolation 3.
3. prepare P well area and P type and reduce electric field region, as shown in Figure 5, its detailed process is as follows:
3.-1, in the surface of top layer epitaxial loayer 2b coating one deck lithographic mask layer, then utilize mask aligner to open P well area 11 and P type reduction electric field region 4 in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P well area 11 and P type reduction electric field region 4; 3.-2, to reduce a layer thickness of growing respectively on the electric field region 4 in P well area 11 and P type be the silicon dioxide of 90nm, growth temperature is 900 ℃, growth time is 30 minutes; 3.-3 be 6.6E12/cm to P well area 11 isolation implantation dosages,
2And energy is the boron ion of 80Kev; 3.-4, again in the surface of top layer epitaxial loayer 2b coating one deck lithographic mask layer, then utilize mask aligner to open the P type and reduce lithographic mask layer on the electric field region 4, reducing electric field region 4 implantation dosages to the P type again is 3.4E12/cm
2And energy is the boron ion of 80Kev; 3.-5, utilize removing of photoresist by plasma equipment to remove the lip-deep lithographic mask layer of top layer epitaxial loayer 2b; 3.-6, in oxidation furnace, advance P well area 11 and P type to reduce electric field region 4, advancing temperature is 1200 ℃, the propelling time is 720 minutes, then carry out 25 minutes wet-oxygen oxidation under 1050 ℃ of temperature, reducing electric field region 4 growth a layer thickness in P well area 11 and P type respectively is the silicon dioxide of 1200nm.
4. prepare the P type heavily doped region of high pressure lateral MOS pipe, as shown in Figure 6, its preparation process is similar to the preparation process of P well area, and its detailed process is as follows:
4.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open P type heavily doped region 9 in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P type heavily doped region 9; 4.-2, be the silicon dioxide of 80nm in P type heavily doped region 9 growth a layer thickness, growth temperature is 900 ℃, growth time is 20 minutes; 4.-3 be 3.0E14/cm to P type heavily doped region 9 implantation dosages,
2And energy is the boron ion of 80Kev; 4.-4, inject the lip-deep lithographic mask layer that finishes rear removal top layer epitaxial loayer 2b; 4.-5, in oxidation furnace, advance P type heavily doped region 9, advancing temperature is 1050 ℃, the propelling time is 60 minutes.
5. prepare polycrystalline resistor and polycrystalline electric capacity, the preparation process of polycrystalline resistor as shown in Figure 7, the preparation process of polycrystalline electric capacity as shown in Figure 8, detailed process is as follows:
5.-1, utilize mode deposit a layer thickness on the surface of top layer epitaxial loayer 2b of cryochemistry vapour deposition to be the polysilicon of 800nm, as ground floor polysilicon 6; 5.-2 be 3.2E14/cm to ground floor polysilicon 6 interior implantation dosages,
2And energy is that the boron ion of 80Kev carries out polysilicon doping; 5.-3, utilize lithographic mask layer to form the bottom crown of polycrystalline resistor and polycrystalline electric capacity; 5.-4, in oxidation furnace, carry out polysilicon oxidation, growth a layer thickness is the silicon dioxide of 700nm, as capacitor dielectric layer 14.
6. the active area and the polysilicon gate that prepare high pressure lateral DMOS pipe and conventional cmos pipe, as shown in Figure 9, its detailed process is as follows:
6.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open the active area of active device in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed active area; 6.-2, be the grid oxygen of 82nm in active area growth a layer thickness, growth temperature is 920 ℃; 6.-3, deposit a layer thickness is the polysilicon of 600nm on grid oxygen, as second layer polysilicon 5, forms top crown and the polygate electrodes of polycrystalline electric capacity.
7. prepare the P type lightly doped region of high pressure lateral DMOS pipe, as shown in figure 10, its detailed process is as follows:
7.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open P type lightly doped region 10 at photoresist mask layer, re-use the silicon dioxide that corrosive liquid is removed P type lightly doped region 10; 7.-2, be the silicon dioxide of 80nm in P type lightly doped region 10 growth a layer thickness, growth temperature is 900 ℃, growth time is 20 minutes; 7.-3 be 7.0E13/cm to P type lightly doped region implantation dosage,
2And energy is the boron ion of 80Kev; 7.-4 utilize plasma degumming machine to remove the lip-deep lithographic mask layer of top layer epitaxial loayer 2b after, injection finishes; 7.-5, isolation advances P type lightly doped region 10 in oxidation furnace, advancing temperature is 1175 ℃, and the propelling time is 45 minutes, and the square resistance of the P type lightly doped region 10 of formation is about 630 Ω/.
8. the source electrode and the drain electrode that prepare the conventional cmos pipe, as shown in figure 11, its detailed process is as follows:
8.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner on lithographic mask layer, to open respectively CMOS pipe N-type source/drain region and P type source/drain region, re-use the silicon dioxide that corrosive liquid is removed N-type source/drain region and P type source/drain region; 8.-2 be 5.0E15/cm to N-type source/drain region implantation dosage,
2And energy is the arsenic ion of 60Kev; 8.-3, in order to form N-type drain region light-dope structure, do not use mask plate, be 6.0E12/cm to the drain region implantation dosage of N-type source/drain region
2And energy is the phosphorus impurities of 120Kev, forms N-type drain region lightly doped region 16; 8.-4, the drain region implantation dosage to P type source/drain region is 7.0E14/cm
2And energy is the boron ion of 50Kev.
Embodiment three:
The present embodiment and embodiment one, embodiment two are basic identical, and the preparation process of the present embodiment is specific as follows:
1. selection: selecting the crystal orientation is that (100), resistivity are that the P type silicon chip of 50 Ω cm is as original material, select the N-type silicon chip of phosphorus doping as epitaxial material, make substrate layer 1 by original material, the double-deck N-type epitaxial loayer 2 that direct growth is made by epitaxial material on substrate layer, as shown in Figure 3, epitaxial loayer 2 comprises bottom epitaxial loayer 2a and top layer epitaxial loayer 2b, and substrate layer 1, bottom epitaxial loayer 2a and top layer epitaxial loayer 2b be successively growth from the bottom to top.
2. adopt high voltage junction isolation technology (HVJI) preparation P type area of isolation, as shown in Figure 4, its detailed process is as follows:
2.-1, be the silicon dioxide of 1000nm in top layer epitaxial loayer 2b growth a layer thickness, apply one deck lithographic mask layer at silicon dioxide; 2.-2, utilize mask aligner to open area of isolation for isolated high-voltage side drive control module and low-pressure side drive control module in lithographic mask layer, then use corrosive liquid to remove the silicon dioxide of area of isolation; 2.-3, use oxidation furnace in area of isolation growth a layer thickness as the silicon dioxide of 70nm as implant blocking layer, growth temperature is 900 ℃, growth time is 25 minutes; 2.-4 be 9.0E15/cm to area of isolation isolation implantation dosage,
2(namely 9.0 * 10
15/ cm
2) and energy be the boron ion B of 50Kev
11+; 2.-5, use corrosive liquid to remove thickness and be the silicon dioxide of 550nm; 2.-6, in oxidation furnace, advance area of isolation, advancing temperature is 1200 ℃, the propelling time is 110 minutes, then carries out 23 minutes wet-oxygen oxidation under 1050 ℃ of temperature, is the silicon dioxide of 250nm in area of isolation growth a layer thickness.By above step, just formed P type area of isolation 3.
3. prepare P well area and P type and reduce electric field region, as shown in Figure 5, its detailed process is as follows:
3.-1, in the surface of top layer epitaxial loayer 2b coating one deck lithographic mask layer, then utilize mask aligner to open P well area 11 and P type reduction electric field region 4 in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P well area 11 and P type reduction electric field region 4; 3.-2, to reduce a layer thickness of growing respectively on the electric field region 4 in P well area 11 and P type be the silicon dioxide of 85nm, growth temperature is 900 ℃, growth time is 30 minutes; 3.-3 be 6.6E12/cm to P well area 11 isolation implantation dosages,
2And energy is the boron ion of 80Kev; 3.-4, again in the surface of top layer epitaxial loayer 2b coating one deck lithographic mask layer, then utilize mask aligner to open the P type and reduce lithographic mask layer on the electric field region 4, reducing electric field region 4 implantation dosages to the P type again is 3.4E12/cm
2And energy is the boron ion of 80Kev; 3.-5, utilize removing of photoresist by plasma equipment to remove the lip-deep lithographic mask layer of top layer epitaxial loayer 2b; 3.-6, in oxidation furnace, advance P well area 11 and P type to reduce electric field region 4, advancing temperature is 1200 ℃, the propelling time is 680 minutes, then carry out 22 minutes wet-oxygen oxidation under 1050 ℃ of temperature, reducing electric field region 4 growth a layer thickness in P well area 11 and P type respectively is the silicon dioxide of 1100nm.
4. prepare the P type heavily doped region of high pressure lateral MOS pipe, as shown in Figure 6, its preparation process is similar to the preparation process of P well area, and its detailed process is as follows:
4.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open P type heavily doped region 9 in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P type heavily doped region 9; 4.-2, be the silicon dioxide of 70nm in P type heavily doped region 9 growth a layer thickness, growth temperature is 900 ℃, growth time is 20 minutes; 4.-3 be 3.0E14/cm to P type heavily doped region 9 implantation dosages,
2And energy is the boron ion of 80Kev; 4.-4, inject the lip-deep lithographic mask layer that finishes rear removal top layer epitaxial loayer 2b; 4.-5, in oxidation furnace, advance P type heavily doped region 9, advancing temperature is 1050 ℃, the propelling time is 55 minutes.
5. prepare polycrystalline resistor and polycrystalline electric capacity, the preparation process of polycrystalline resistor as shown in Figure 7, the preparation process of polycrystalline electric capacity as shown in Figure 8, detailed process is as follows:
5.-1, utilize mode deposit a layer thickness on the surface of top layer epitaxial loayer 2b of cryochemistry vapour deposition to be the polysilicon of 700nm, as ground floor polysilicon 6; 5.-2 be 3.2E14/cm to ground floor polysilicon 6 interior implantation dosages,
2And energy is that the boron ion of 80Kev carries out polysilicon doping; 5.-3, utilize lithographic mask layer to form the bottom crown of polycrystalline resistor and polycrystalline electric capacity; 5.-4, in oxidation furnace, carry out polysilicon oxidation, growth a layer thickness is the silicon dioxide of 650nm, as capacitor dielectric layer 14.
6. the active area and the polysilicon gate that prepare high pressure lateral DMOS pipe and conventional cmos pipe, as shown in Figure 9, its detailed process is as follows:
6.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open the active area of active device in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed active area; 6.-2, be the grid oxygen of 80nm in active area growth a layer thickness, growth temperature is 920 ℃; 6.-3, deposit a layer thickness is the polysilicon of 550nm on grid oxygen, as second layer polysilicon 5, forms top crown and the polygate electrodes of polycrystalline electric capacity.
7. prepare the P type lightly doped region of high pressure lateral DMOS pipe, as shown in figure 10, its detailed process is as follows:
7.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner to open P type lightly doped region 10 at photoresist mask layer, re-use the silicon dioxide that corrosive liquid is removed P type lightly doped region 10; 7.-2, be the silicon dioxide of 70nm in P type lightly doped region 10 growth a layer thickness, growth temperature is 900 ℃, growth time is 20 minutes; 7.-3 be 7.0E13/cm to P type lightly doped region implantation dosage,
2And energy is the boron ion of 80Kev; 7.-4 utilize plasma degumming machine to remove the lip-deep lithographic mask layer of top layer epitaxial loayer 2b after, injection finishes; 7.-5, isolation advances P type lightly doped region 10 in oxidation furnace, advancing temperature is 1175 ℃, and the propelling time is 45 minutes, and the square resistance of the P type lightly doped region 10 of formation is about 560 Ω/.
8. the source electrode and the drain electrode that prepare the conventional cmos pipe, as shown in figure 11, its detailed process is as follows:
8.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer 2b, then utilize mask aligner on lithographic mask layer, to open respectively CMOS pipe N-type source/drain region and P type source/drain region, re-use the silicon dioxide that corrosive liquid is removed N-type source/drain region and P type source/drain region; 8.-2 be 5.0E15/cm to N-type source/drain region implantation dosage,
2And energy is the arsenic ion of 60Kev; 8.-3, in order to form N-type drain region light-dope structure, do not use mask plate, be 6.0E12/cm to the drain region implantation dosage of N-type source/drain region
2And energy is the phosphorus impurities of 120Kev, forms N-type drain region lightly doped region 16; 8.-4, the drain region implantation dosage to P type source/drain region is 7.0E14/cm
2And energy is the boron ion of 50Kev.
Claims (8)
1. a high-voltage grid that is used for direct driving power device drives the preparation method of chip, it is characterized in that may further comprise the steps:
1. selection: select the crystal orientation be (100), resistivity be the P type silicon chip of 40～60 Ω cm as original material, the N-type silicon chip of selection phosphorus doping is as epitaxial material; Make substrate layer by original material, make double-deck epitaxial loayer by epitaxial material, epitaxial loayer comprises bottom epitaxial loayer and top layer epitaxial loayer, and substrate layer, bottom epitaxial loayer and top layer epitaxial loayer be successively growth from the bottom to top;
2. prepare P type area of isolation, detailed process is:
2.-1, be the silicon dioxide of 900～1100nm in top layer epitaxial loayer growth a layer thickness, then apply one deck lithographic mask layer at silicon dioxide; 2.-2, utilize mask aligner to open area of isolation for isolated high-voltage side drive control module and low-pressure side drive control module in lithographic mask layer, then use corrosive liquid to remove the silicon dioxide of area of isolation; 2.-3 be that the silicon dioxide of 60～80nm is as implant blocking layer in area of isolation growth a layer thickness; 2.-4 be 9.0E15/cm to area of isolation isolation implantation dosage,
2And energy is the boron ion of 50Kev; 2.-5, using corrosive liquid to remove thickness is the silicon dioxide of 500～600nm; 2.-6, in oxidation furnace, advance area of isolation, advancing temperature is 1200 ℃, the propelling time is 100～120 minutes, then carries out wet-oxygen oxidation, is the silicon dioxide of 250nm in area of isolation growth a layer thickness, forms P type area of isolation;
3. prepare P well area and P type and reduce electric field region, detailed process is:
3.-1, in the surface of top layer epitaxial loayer coating one deck lithographic mask layer, then utilize mask aligner to open the P well area and the P type reduces electric field region in lithographic mask layer, re-use corrosive liquid and remove the silicon dioxide that P well area and P type reduce electric field region; 3.-2, reducing a layer thickness of growing respectively on the electric field region in P well area and P type is the silicon dioxide of 80～90nm; 3.-3 be 6.6E12/cm to P well area isolation implantation dosage,
2And energy is the boron ion of 80Kev; 3.-4, again in the surface of top layer epitaxial loayer coating one deck lithographic mask layer, then utilize mask aligner to open the P type and reduce lithographic mask layer on the electric field region, reducing the electric field region implantation dosage to the P type again is 3.4E12/cm
2And energy is the boron ion of 80Kev; 3.-5, utilize removing of photoresist by plasma equipment to remove the lip-deep lithographic mask layer of top layer epitaxial loayer; 3.-6, in oxidation furnace, advance P well area and P type to reduce electric field region, advancing temperature is 1200 ℃, the propelling time is 600～720 minutes, then carries out wet-oxygen oxidation, is the silicon dioxide of 1000～1200nm at P well area and P type reduction electric field region growth a layer thickness respectively;
4. prepare the P type heavily doped region of high pressure lateral DMOS pipe, detailed process is:
4.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner to open P type heavily doped region in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed P type heavily doped region; 4.-2 be the silicon dioxide of 60～80nm in P type heavily doped region growth a layer thickness; 4.-3 be 3.0E14/cm to P type heavily doped region implantation dosage,
2And energy is the boron ion of 80Kev; 4.-4, inject the lip-deep lithographic mask layer that finishes rear removal top layer epitaxial loayer; 4.-5, in oxidation furnace, advance P type heavily doped region;
5. prepare polycrystalline resistor and polycrystalline electric capacity, detailed process is:
5.-1, to utilize mode deposit a layer thickness on the surface of top layer epitaxial loayer of cryochemistry vapour deposition be the polysilicon of 600～800nm, as the ground floor polysilicon; 5.-2, implantation dosage is 3.2E14/cm in the ground floor polysilicon
2And energy is that the boron ion of 80Kev carries out polysilicon doping; 5.-3, utilize lithographic mask layer to form the bottom crown of polycrystalline resistor and polycrystalline electric capacity; 5.-4, in oxidation furnace, carry out polysilicon oxidation, growth a layer thickness is the silicon dioxide of 600～700nm, as the capacitor dielectric layer;
6. prepare active area and the polysilicon gate of high pressure lateral DMOS pipe and conventional cmos pipe, detailed process is:
6.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner to open the active area of active device in lithographic mask layer, re-use the silicon dioxide that corrosive liquid is removed active area; 6.-2, at active area growth one deck grid oxygen; 6.-3, on grid oxygen deposit one deck polysilicon, as second layer polysilicon, form top crown and the polygate electrodes of polycrystalline electric capacity;
7. prepare the P type lightly doped region of high pressure lateral DMOS pipe, detailed process is:
7.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner to open P type lightly doped region at photoresist mask layer, re-use the silicon dioxide that corrosive liquid is removed P type lightly doped region; 7.-2 be the silicon dioxide of 60～80nm in P type lightly doped region growth a layer thickness; 7.-3 be 7.0E13/cm to P type lightly doped region implantation dosage,
2And energy is the boron ion of 80Kev; 7.-4 utilize plasma degumming machine to remove the lip-deep lithographic mask layer of top layer epitaxial loayer after, injection finishes; 7.-5, isolation advances P type lightly doped region in oxidation furnace;
8. prepare source electrode and the drain electrode of conventional cmos pipe, detailed process is:
8.-1, apply one deck lithographic mask layer on the surface of top layer epitaxial loayer, then utilize mask aligner on lithographic mask layer, to open respectively N-type source/drain region and the P type source/drain region of CMOS pipe, re-use the silicon dioxide that corrosive liquid is removed N-type source/drain region and P type source/drain region; 8.-2 be 5.0E15/cm to N-type source/drain region implantation dosage,
2And energy is the arsenic ion of 60Kev; 8.-3, the drain region implantation dosage to N-type source/drain region is 6.0E12/cm
2And energy is the phosphorus impurities of 120Kev, forms N-type drain region lightly doped region; 8.-4, the drain region implantation dosage to P type source/drain region is 7.0E14/cm
2And energy is the boron ion of 50Kev.
2. a kind of preparation method who drives chip for the direct high-voltage grid of driving power device according to claim 1, the thickness that it is characterized in that described bottom epitaxial loayer is 2.0～4.5 μ m, the resistivity of described bottom epitaxial loayer is 0.5～1.2 Ω cm, the thickness of described top layer epitaxial loayer is 5.0～10.0 μ m, and the resistivity of described top layer epitaxial loayer is 2.5～3.15 Ω cm.
3. a kind of preparation method who drives chip for the direct high-voltage grid of driving power device according to claim 1 and 2, it is characterized in that the growth temperature at area of isolation growth silicon dioxide was 900 ℃ during described step 2.-3, growth time is 20～30 minutes; Described step 2.-6 in the temperature of wet-oxygen oxidation be 1050 ℃, the time of wet-oxygen oxidation is 18～25 minutes.
4. a kind of preparation method who drives chip for the direct high-voltage grid of driving power device according to claim 3, the growth temperature that it is characterized in that during described step 3.-2 reducing in P well area and P type the silicon dioxide of growing respectively on the electric field region is 900 ℃, and growth time is 30 minutes; Described step 3.-6 in the temperature of wet-oxygen oxidation be 1050 ℃, the time of wet-oxygen oxidation is 18～25 minutes.
5. a kind of preparation method who drives chip for the direct high-voltage grid of driving power device according to claim 4, it is characterized in that the growth temperature at P type heavily doped region growth silicon dioxide was 900 ℃ during described step 4.-2, growth time is 20 minutes; Described step 4.-5 in isolation to advance the propelling temperature of P type heavily doped region be 1050 ℃, the propelling time is 50～60 minutes.
6. a kind of preparation method who drives chip for the direct high-voltage grid of driving power device according to claim 5 is characterized in that the thickness of the grid oxygen of growing at active area during described step 6.-2 is 78～82nm, and growth temperature is 920 ℃; Described step 6.-3 on grid oxygen the thickness of the polysilicon of deposit be 500～600nm.
7. a kind of preparation method who drives chip for the direct high-voltage grid of driving power device according to claim 6, it is characterized in that the growth temperature at P type lightly doped region growth silicon dioxide was 900 ℃ during described step 7.-2, growth time is 20 minutes; Described step 7.-5 in isolation to advance the propelling temperature of P type lightly doped region be 1175 ℃, the propelling time is 45 minutes.
8. a kind of preparation method who drives chip for the high-voltage grid of direct driving power device according to claim 1 and 2 is characterized in that the square resistance of the P type lightly doped region of formation during described step 7. is 450～630 Ω/.
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| CN102723304B (en) * | 2012-05-31 | 2014-07-16 | 日银Imp微电子有限公司 | Preparation method of N-trap high-voltage gate driving chip for directly driving power device |
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| CN104992966B (en) * | 2015-05-21 | 2017-10-24 | 中国电子科技集团公司第十三研究所 | A kind of preparation method of the low bipolar high frequency power transistor chip of heat budget |
| CN106298524B (en) * | 2015-05-27 | 2019-05-07 | 北大方正集团有限公司 | The horizontal double-diffused metal oxide semiconductor LDMOS of high frequency and manufacturing method |
| CN109444551B (en) * | 2018-09-10 | 2020-09-15 | 全球能源互联网研究院有限公司 | Method and circuit for testing square resistance of semiconductor |
| CN111326580B (en) * | 2018-12-13 | 2022-08-02 | 中芯集成电路（宁波）有限公司 | Gate drive integrated circuit and forming method thereof |
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Effective date of registration: 20161222 Address after: 315809 Beilun City, Ningbo Province, Wan Chai street, Wan Jing Road, No. G, block, floor three, 12-3, 213 Patentee after: Core integrated circuit (Ningbo) Co., Ltd. Address before: Ningbo city science and Technology Park in Zhejiang province 315040 lease Poplar Road No. 7 Lane 578 Patentee before: Daily Silver IMP Microelectronics Co., Ltd. |
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