CN102983070B - Preparation method for metamaterial and metamaterial - Google Patents
Preparation method for metamaterial and metamaterial Download PDFInfo
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- CN102983070B CN102983070B CN201110260989.6A CN201110260989A CN102983070B CN 102983070 B CN102983070 B CN 102983070B CN 201110260989 A CN201110260989 A CN 201110260989A CN 102983070 B CN102983070 B CN 102983070B
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Abstract
The embodiment of the present invention provides a preparation method for a metamaterial. the method comprises: forming a first insulating layer on a substrate; depositing a first intrinsic poly-silicon layer on the first insulating layer; doping the first intrinsic poly-silicon layer to obtain a first conductor layer; forming a default micro-structure array on the first conductor layer; depositing a second insulating layer on the first conductor layer having a micro-structure array; depositing a second intrinsic poly-silicon layer on the second insulating layer; doping the second intrinsic poly-silicon layer to obtain a second conductor layer; and forming the default micro-structure array on the second conductor layer. The embodiment of the present invention further provides the metamaterial prepared by using the method in the above-described embodiment. The metamaterial with micro-structure of relative better controllability and double-crystal silicon capacitive characteristics can be obtained.
Description
【Technical field】
The present invention relates to technical field of composite materials, more particularly, to a kind of preparation method of Meta Materials and Meta Materials.
【Background technology】
Meta Materials are the height intersection having merged the science such as electromagnetism, microwave, Terahertz, photon, advanced engineering design, communication
New field.As emerging interdisciplinary science technology, Meta Materials science and technology is repeatedly cited as the " world ten because of its prominent physical characteristic
Big Progress ＆ New Products ".As brand-new material science and technology Meta Materials significant development, space flight, aviation, electronics, communication, Internet of Things,
All there is substantial amounts of potential application in the fields such as biomedical devices, military affairs.The core theory of Meta Materials is description electromagnetic wave rail
Mark and the anamorphic optical of Meta Materials characteristic, a big core of this technology is to design thousands of mutually different artificial complexity
Micro structure simultaneously forms a Meta Materials device with specific functionality according to rational arrangement.
In prior art, CMOS technology is the technique enabling controlled minimum dimension in semiconductor technology, present 32nm
Processing procedure gradually ripe, smaller size of processing procedure is developed.Effectively utilize the various different material in CMOS technology, lead to
Cross the size Control means of CMOS technology, the micro structure of very small dimensions can be constructed.Dual poly (double Poly-silicon) electricity
Container has the advantages of capacity is big, and electrode property is controlled.Should with twin crystal silicon electric capacity by CMOS technology but also do not have in prior art
In Meta Materials preparation.
【Content of the invention】
The technical problem to be solved is to provide a kind of preparation method of Meta Materials and Meta Materials, can obtain micro-
Structure-controllable performance is higher, have the Meta Materials of twin crystal silicon capacitance characteristic.
For solving above-mentioned technical problem, the method that one embodiment of the invention provides Meta Materials preparation, this preparation method bag
Include：
First insulating barrier is formed on substrate；
First intrinsically polysilicon layer is deposited on the first insulating barrier；
Described first intrinsic polysilicon is doped, obtains the first conductor layer；
Described first conductor layer forms default micro structure array；
Second insulating barrier is formed on first conductor layer with micro structure array；
Deposit the second intrinsically polysilicon layer over the second dielectric；
Second intrinsically polysilicon layer is doped, obtains the second conductor layer；
Described default micro structure array is formed on the second conductor layer.
Another embodiment of the present invention additionally provides a kind of Meta Materials, including：
Backing material；The first insulating barrier on substrate；Have the first of micro structure array on the first insulating barrier
Conductor layer；The second insulating barrier in the first conductor layer；And on the second insulating barrier, there is described micro structure array
Second conductor layer.
Technique scheme compared with prior art, has advantages below：Capacity is had greatly based on dual poly electric capacity, electricity
The controlled advantage of polarity matter, is prepared using CMOS technology and has the first conductor layer of micro structure array, has micro structure array
The second conductor layer and be located at insulating barrier between the first conductor layer and the second conductor layer, thus obtain that there is twin crystal silicon electricity
Hold the Meta Materials of characteristic, and due to CMOS technology, the process control preparing micro structure array is high.
【Brief description】
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, will make to required in embodiment description below
Accompanying drawing be briefly described it should be apparent that, drawings in the following description are only some embodiments of the present invention, for
For those of ordinary skill in the art, without having to pay creative labor, it can also be obtained according to these accompanying drawings
Its accompanying drawing.
Fig. 1 is a kind of preparation method flow chart of Meta Materials that the present invention implements an offer；
Fig. 2 is a kind of preparation method flow chart of Meta Materials that the present invention implements two offers；
Fig. 3 is a kind of metamaterial structure schematic diagram that the embodiment of the present invention three provides；
Fig. 4 is a kind of metamaterial structure schematic diagram that the embodiment of the present invention four provides.
【Specific embodiment】
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation description is it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is all other that those of ordinary skill in the art are obtained under the premise of not making creative work
Embodiment, broadly falls into the scope of protection of the invention.
Embodiment one,
Referring to Fig. 1, it is a kind of preparation method flow chart of Meta Materials that the present invention implements an offer, this preparation method bag
Include：
S101：One layer insulating is formed on substrate.
Specifically, a layer insulating can be deposited on substrate；One layer insulating can also be generated on substrate, for example,
The method of dry oxidation or the method for wet oxidation is adopted to generate layer of silicon dioxide on a silicon substrate.
S102：First intrinsically polysilicon layer is deposited on the first insulating barrier.
Wherein, the thickness of deposit the first intrinsically polysilicon layer is configured according to specific requirement.
S103：First intrinsic polysilicon is doped, obtains the first conductor layer.
For example, p-type or N-type impurity are injected in the first intrinsically polysilicon layer.
S104：Default micro structure array is formed on the first conductor layer.
Specifically, one layer of photoresist is applied on the first conductor layer；Photoetching is carried out to photoresist, is formed pre- on a photoresist
If micro structure array；The micro structure array being formed after photoetching on photoresist is transferred in the first conductor layer.
Wherein, micro structure array is designed according to specific requirement.Each micro structure in micro structure array can be axle
To one-tenth figure, such as " work " font and its derivative shape；Can also be non-axis symmetry figure, such asFont, Yi Jiping
Row tetragon.
S105：Second insulating barrier is deposited on first conductor layer with micro structure array, and by this second insulating barrier
Appearance mirror polish.
Wherein, the material of the material of this second insulating barrier and the first insulating barrier can identical it is also possible to different.
S106：Deposit the second intrinsically polysilicon layer over the second dielectric.
Wherein, the thickness of deposit the second intrinsically polysilicon layer is configured according to specific requirement.
S107：Second intrinsically polysilicon layer is doped, obtains the second conductor layer.
For example, p-type or N-type impurity are injected in the second intrinsically polysilicon layer.
S108：Default micro structure array is formed on the second conductor layer.
Specifically, one layer of photoresist is applied on the second conductor layer；Photoetching is carried out to photoresist, is formed pre- on a photoresist
If micro structure array；The micro structure array being formed after photoetching on photoresist is transferred in the second conductor layer.
In the present embodiment, capacity is had greatly based on dual poly electric capacity, the controlled advantage of electrode property, using CMOS technology
Prepare and there is the first conductor layer of micro structure array, there is the second conductor layer of micro structure array and be located at the first conductor
Insulating barrier between layer and the second conductor layer, thus obtain the Meta Materials with twin crystal silicon capacitance characteristic, and due to CMOS work
The feature of skill, the process control preparing micro structure array is high.
Embodiment two,
Referring to Fig. 2, it is a kind of preparation method flow chart of Meta Materials that the present invention implements two offers, this preparation method bag
Include：
S201：Substrate is carried out.
S202：One layer insulating is formed on substrate.
Specifically, a layer insulating can be deposited on substrate；One layer insulating can also be generated on substrate, for example,
The method of dry oxidation or the method for wet oxidation is adopted to generate layer of silicon dioxide on a silicon substrate.
S203：First intrinsically polysilicon layer is deposited on the first insulating barrier.
Wherein, the thickness of deposit the first intrinsically polysilicon layer is configured according to specific requirement.
S204：First intrinsic polysilicon is doped, obtains the first conductor layer.
For example, p-type or N-type impurity are injected in the first intrinsically polysilicon layer.
S205：First conductor layer coats one layer of photoresist, according to default micro structure array, described photoresist is entered
Row photoetching, the micro structure array being formed after etching or etch photoetching on photoresist in the first conductor layer.
Wherein, micro structure array is designed according to specific requirement.Each micro structure in micro structure array can be axle
To one-tenth figure, such as " work " font and its derivative shape；Can also be non-axis symmetry figure, such asFont, Yi Jiping
Row tetragon.
S206：Second insulating barrier is deposited on first conductor layer with micro structure array, and by this second insulating barrier
Appearance mirror polish.
Wherein, the material of the material of this second insulating barrier and the first insulating barrier can identical it is also possible to different.
S207：Deposit the second intrinsically polysilicon layer over the second dielectric.
Wherein, the thickness of deposit the second intrinsically polysilicon layer is configured according to specific requirement.
S208：Second intrinsically polysilicon layer is doped, obtains the second conductor layer.
For example, p-type or N-type impurity are injected in the second intrinsically polysilicon layer.
S209：Second conductor layer coats one layer of photoresist, light is carried out to photoresist according to default micro structure array
Carve；The micro structure array being formed after etching or etch photoetching on photoresist in the second conductor layer.
Wherein, micro structure array is designed according to specific requirement.
S210：The second conductor layer have micro structure array deposits the 3rd insulating barrier, and by the 3rd insulating barrier
Appearance mirror polish.
Wherein, the material of the 3rd insulating barrier identical with the material of the material of the first insulating barrier and the second insulating barrier or
Different.
The present embodiment, with respect to embodiment one, has carried out cleaning it is ensured that preparing the degree of purity of Meta Materials to substrate；In addition exist
There is deposit the 3rd insulating barrier in the second conductor layer of micro structure array, the 3rd insulating barrier, as protective layer, enters to Meta Materials
Row protection.
Referring to Fig. 3, it is a kind of metamaterial structure schematic diagram that the embodiment of the present invention three provides, this Meta Materials includes：
Backing material 301；The first insulating barrier 302 on substrate 301；On the first insulating barrier 302, there is micro- knot
First conductor layer 303 of structure array；The second insulating barrier 304 in the first conductor layer 303；And it is located at the second insulating barrier
There is on 304 second conductor layer 305 of described micro structure array.
Wherein, micro structure array is designed according to specific requirement.Each micro structure in micro structure array can be axle
To one-tenth figure, such as " work " font and its derivative shape；Can also be non-axis symmetry figure, such asFont, and parallel
Tetragon.
Wherein, the material of the first insulating barrier 302 is identical with the material of the second insulating barrier 304, or different, according to specific
Demand is designed.
In the present embodiment, the first conductor layer 303 of Meta Materials, the second conductor layer 305 and be located at the first conductor layer 303
The second insulating barrier 304 and the second conductor layer 305 between, constitutes dual poly electric capacity, because dual poly electric capacity has appearance
The advantages of measure big, electrode property is controlled, therefore this material is also with twin crystal silicon capacitance characteristic.
Referring to Fig. 4, it is a kind of metamaterial structure schematic diagram that the embodiment of the present invention four provides, this Meta Materials includes：
This embodiment is implementing backing material 301 in three；The first insulating barrier 302 on substrate 301；Exhausted positioned at first
First conductor layer 303 of micro structure array is had on edge layer 302；The second insulating barrier 304 in the first conductor layer 303；With
And also include on the basis of being located at the second conductor layer 305 that described micro structure array is had on the second insulating barrier 304：
The 3rd insulating barrier 401 above the second conductor layer 305.
With respect to embodiment three, in the second conductor layer, 305 deposit the 3rd insulating barrier 401, the 3rd insulation to the present embodiment
Layer 401, as protective layer, is protected to Meta Materials.
Above the embodiment of the present invention is described in detail, specific case used herein to the principle of the present invention and
Embodiment is set forth, and the explanation of above example is only intended to help and understands the method for the present invention and its core concept；
Simultaneously for one of ordinary skill in the art, according to the thought of the present invention, all can in specific embodiments and applications
In place of having change, in sum, this specification content should not be construed as limitation of the present invention.
Claims (4)
1. a kind of method of Meta Materials preparation is it is characterised in that methods described includes：
First insulating barrier is formed on substrate；
First intrinsically polysilicon layer is deposited on the first insulating barrier；
Described first intrinsic polysilicon is doped, obtains the first conductor layer；
Described first conductor layer forms default micro structure array；
Second insulating barrier is deposited on first conductor layer with micro structure array；
Deposit the second intrinsically polysilicon layer over the second dielectric；
Second intrinsically polysilicon layer is doped, obtains the second conductor layer；
Described default micro structure array is formed on the second conductor layer,
Wherein, described micro structure array is zhou duicheng tuxing or non-axis symmetry figure, is formed pre- in described first conductor layer
If micro structure array, including：
Described first conductor layer coats one layer of photoresist, light is carried out to described photoresist according to default micro structure array
Carve；
The micro structure array being formed after etching or etch photoetching on photoresist in the first conductor layer；
Accordingly, described default micro structure array is formed on the second conductor layer, including：
Described second conductor layer coats one layer of photoresist, light is carried out to described photoresist according to default micro structure array
Carve；
The micro structure array being formed after etching or etch photoetching on photoresist in the second conductor layer；
Described first intrinsic polysilicon is doped, including：
P-type or N-type impurity are injected in described first intrinsically polysilicon layer；Accordingly,
Second intrinsically polysilicon layer is doped, including：
P-type or N-type impurity are injected in described second intrinsically polysilicon layer.
2. method according to claim 1 is it is characterised in that also include before forming the first insulating barrier on substrate：
Substrate is carried out.
3. method according to claim 1 is it is characterised in that form described default micro structure battle array in the second conductor layer
After row, also include：
3rd insulating barrier is formed on the second conductor layer have micro structure array.
4. method according to claim 1 is it is characterised in that form the first insulating barrier on substrate, including：
One layer insulating is generated on substrate；Or a layer insulating is deposited on substrate.
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| WO2018176267A1 (en) * | 2017-03-29 | 2018-10-04 | 香港中文大学（深圳） | Method for fabricating perfect absorber |
| CN108227244B (en) * | 2018-03-19 | 2020-01-03 | 中国科学技术大学 | Modulator for regulating terahertz wave amplitude and manufacturing method |
| CN110718763B (en) * | 2019-09-17 | 2020-08-04 | 北京航空航天大学 | Tunable metamaterial device based on CMOS (complementary Metal oxide semiconductor) process |
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| CN1431696A (en) * | 2002-01-09 | 2003-07-23 | 矽统科技股份有限公司 | Method for mfg. polisilicon/polisilicon capacitance |
| CN101197371A (en) * | 2006-12-06 | 2008-06-11 | 上海华虹Nec电子有限公司 | Coupling capacitance structure and manufacturing method thereof |
| CN101465384A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Polycrystalline silicon-insulator-polycrystalline silicon capacitance structure |
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| CN102130060B (en) * | 2010-12-24 | 2013-02-20 | 日银Imp微电子有限公司 | Method for producing high-voltage grid drive chip for directly driving power device |
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| CN1431696A (en) * | 2002-01-09 | 2003-07-23 | 矽统科技股份有限公司 | Method for mfg. polisilicon/polisilicon capacitance |
| CN101197371A (en) * | 2006-12-06 | 2008-06-11 | 上海华虹Nec电子有限公司 | Coupling capacitance structure and manufacturing method thereof |
| CN101465384A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Polycrystalline silicon-insulator-polycrystalline silicon capacitance structure |
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