CN109444551B - Method and circuit for testing square resistance of semiconductor - Google Patents
Method and circuit for testing square resistance of semiconductor Download PDFInfo
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- CN109444551B CN109444551B CN201811051617.0A CN201811051617A CN109444551B CN 109444551 B CN109444551 B CN 109444551B CN 201811051617 A CN201811051617 A CN 201811051617A CN 109444551 B CN109444551 B CN 109444551B
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Abstract
The invention discloses a method and a circuit of a semiconductor square resistor, wherein the method comprises the following steps: forming at least one first doped region in the doped region to be tested, wherein the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming a second doped region in the first doped region, wherein the second doped region is of the first conductivity type; at least two excitation electrodes are arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping area; sequentially arranging at least one isolation layer and control electrodes corresponding to the isolation layer on the surface of the semiconductor substrate, wherein the isolation layer and the control electrodes extend from the edge of one first doping region to the edge of a second doping region inside the first doping region; and applying excitation current through the two excitation electrodes, and testing the voltage between the to-be-tested doped regions positioned between the two excitation electrodes to obtain the square resistance value of the to-be-doped region. The square resistance test is carried out by the method, and the more accurate square resistance value can be measured.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a method and a circuit for testing a semiconductor square resistor.
Background
The square resistance is also called membrane resistance and surface resistance, and refers to the resistance between edges of a square thin film conductive material, and represents the compactness of a membrane layer. Fig. 1 shows a schematic diagram of a square type film, where a and b are the length and width of the square, respectively, a ═ b, and d is the thickness of the film. When the square type film is applied with exciting current I, and the current I flow direction is basically parallel to the film surface, the square resistance can be obtained as
It can be seen that the resistance of the square film is related only to the thickness and resistivity ρ of the square film, and is not related to the length and width of the square. Whereas for semiconductors the resistivity p is related to the doping concentration of the thin film conductive material, and the ion doping depth corresponds to the thickness of the thin film resistor, the semiconductor sheet resistance can be used to characterize the ion doping concentration and depth of the semiconductor surface during the manufacturing process. Therefore, during the manufacturing process of integrated circuits and devices, the square resistance of a specific doped layer can be tested to monitor the fluctuation of the process (ion implantation window size, ion implantation dosage or energy, diffusion temperature and time, etc.) of the doped layer on line, so as to ensure the normal electrical characteristics, parameter consistency and stability of the final devices and circuits, and the reliability of the devices and circuits.
Since the sheet resistance of semiconductors is usually small, typically in the milliohm range, kelvin connections with high measurement accuracy are usually used for testing.
Fig. 2 shows a schematic diagram of the principle of detection by kelvin connection, where Rt is the resistance to be detected, a point a and a point B are two ends of the resistance to be detected, and an excitation branch and a detection branch are connected in parallel at an end AB. On the excitation branch, the direct current source applies an excitation current I flowing from the end A to the end B to the resistor to be tested through a first excitation wire F1 and a second excitation wire F2; meanwhile, in the detection branch, the high-impedance voltmeter detects the resistance between the AB through the first detection line S1 and the second detection line S2, r1～r4Respectively representing contact resistance on corresponding line segmentsAnd the sum of the lead resistances (i.e., the parasitic resistance of the detection system), where contact resistance refers to the contact resistance between the probe and the test point. The voltmeter on the detection branch is high impedance, so that the current on the detection branch is almost zero, and the resistance r3、r4The pressure drop over is also almost zero; and because the excitation branch is connected with the detection branch in parallel, the resistor r on the excitation branch1、r2The voltage drop in the resistor does not affect the measurement result of the voltage between the detection branch and the AB, so that the influence of contact resistance and lead resistance (between the probe and the test point) can be eliminated by adopting Kelvin connection for detection, and the measurement result of the resistor Rt to be measured is more accurate and can be generally accurate to 0.1m omega.
Fig. 3A shows a schematic connection diagram of a prior art method for testing a semiconductor sheet resistance by using kelvin connection. The N-region is a to-be-detected lightly doped region, A is a first metal electrode, B is a second metal electrode, and the N + region is a heavily doped region and used for forming ohmic contact with the metal electrode. During detection, two ends of the excitation branch are respectively contacted with the first metal electrode A and the second metal electrode B, and two ends of the detection branch are also respectively contacted with the first metal electrode A and the second metal electrode B. It should be noted that the light doping and the heavy doping are used to indicate relative magnitudes of ion doping concentrations, and the ion doping concentrations are not limited.
However, the inventors found that: if the ion doping concentration of the N + region for forming ohmic contact in fig. 3A does not reach the concentration for forming good ohmic contact with the metal electrode, the fermi level of the metal electrode and the N + region in contact is greatly different, so that electrons in the semiconductor and in the region in contact with the metal electrode are gathered at the contact surface of the semiconductor and the metal, and holes are gathered at the region in the semiconductor and close to the contact surface of the metal, thereby forming a stable internal electric field, the direction of which is from the semiconductor to the metal electrode, and the formed stable electric field further hinders the movement of carriers (i.e. electrons or holes) and prevents the carriers from freely diffusing; a depletion layer is formed between the collected electrons and the collected holes, which is a microscopic manifestation of the schottky junction. Because the internal electric fields of the two Schottky junctions point to the metal electrode from the semiconductor, when the region to be tested is electrified with the excitation current I in any direction, one of the two Schottky junctions on the path of the excitation current I is always in a forward bias state, and the other is always in a reverse bias state. As shown in fig. 3A-3C, when the first metal electrode a is connected to a positive voltage and the second metal electrode B is connected to a negative voltage, the current on the semiconductor surface flows from the first metal electrode a to the second metal electrode B, and at this time, the schottky junction X at the position of the first metal electrode a is forward biased, and the schottky junction Y at the position of the second metal electrode B is reverse biased. For a positively biased schottky junction X, applying the excitation current I is equivalent to applying an external electric field across the schottky junction, which cancels the internal electric field, so that the carriers can diffuse freely as normal. For the reverse-biased Schottky junction Y, the direction of an external electric field formed by applying the excitation current I is consistent with that of an internal electric field, namely, the blocking effect on free diffusion of carriers is further enhanced; taking an N-type doped P-type semiconductor as an example, when the excitation current I is applied, the negative electrode of the power supply (i.e., the second metal electrode B) can make more electrons gather at the contact surface of the semiconductor and the metal electrode; accordingly, new holes attracted by the newly accumulated electrons are accumulated on the other side of the depletion region, and these "new holes" originate from the nearby resistance region to be measured, which results in a decrease in the hole (i.e., minority carrier) concentration of the resistance region to be measured, as shown in fig. 3D, wherein the direction of the arrow indicates the moving direction of the carriers. In addition, for the reverse biased schottky junction Y, even if the intensity of the external electric field is greater than the reverse breakdown voltage of the schottky junction Y, so that the schottky junction Y can be conducted reversely, and the electrons in the excitation current I can be recombined with the holes in the depletion region, the holes gathered from the resistance region to be measured are depleted, and the hole concentration of the resistance region to be measured is reduced, as shown in fig. 3E, the measured sheet resistance of the resistance region to be measured can still be affected, which is different from the measured sheet resistance in the state where the excitation current I is not applied. In summary, the sheet resistance measured by the above method may be affected by the depletion layer, resulting in inaccurate measurement results.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method and a circuit for testing a semiconductor sheet resistance, so as to solve the problem that the sheet resistance measured by the conventional testing method is affected by a depletion layer, so that the measurement result is inaccurate.
According to a first aspect, an embodiment of the present invention provides a method for testing a semiconductor sheet resistor, in which a doped region to be tested is located in a semiconductor substrate and has a first conductivity type. The method comprises the following steps: forming at least one first doped region in the doped region to be tested, wherein the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming a second doped region in the first doped region, wherein the second doped region is of the first conductivity type; at least two excitation electrodes are arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping area; sequentially arranging at least one isolation layer and control electrodes corresponding to the isolation layer on the surface of the semiconductor substrate, wherein the isolation layer and the control electrodes extend from the edge of one first doping region to the edge of a second doping region inside the first doping region; and applying excitation current through the two excitation electrodes, and simultaneously testing the square resistance value of the doping area to be tested positioned between the two excitation electrodes.
Optionally, the first conductivity type is N-type, and the second conductivity type is P-type; or the first conduction type is P type, and the second conduction type is N type.
Optionally, the step of testing the sheet resistance of the doped region to be tested located between the two excitation electrodes includes: at least one pair of probes is arranged between the two excitation electrodes, and the pair of probes comprises a first probe and a second probe; and measuring a distance between the first probe and the second probe; acquiring a value of the excitation current; testing the voltage value between the first probe and the second probe; calculating the square resistance value of the doping area to be measured according to the following formula:
wherein V is the voltage value between the first probe and the second probe, I is the value of the excitation current, and n is the distance between the first probe and the second probe.
Optionally, testing between two excitation electrodesThe step of measuring the square resistance of the doped region comprises the following steps: arranging at least one group of probes between the two excitation electrodes, wherein the group of probes comprises a first probe, a second probe and a third probe; measuring the distance between the second probe and the first probe and the distance between the second probe and the third probe; respectively testing the voltage value between the second probe and the first probe and the voltage value between the second probe and the third probe; acquiring a value of the excitation current; calculating the block resistance value of the region to be doped according to the following formula:
wherein R issqIs the square resistance value to be measured, V21Is the voltage value between the second probe and the first probe, V23Is the voltage value between the second probe and the third probe, n21Is the distance between the second probe and the first probe, n23Is the distance between the second probe and the third probe, and I is the value of the excitation current.
Optionally, the probe is disposed on a line connecting the two excitation electrodes.
Optionally, the voltage between the two locations is tested by a high impedance voltage testing device.
Optionally, before the step of applying an excitation current through two excitation electrodes and simultaneously testing the sheet resistance of the doped region to be tested located between the two excitation electrodes, the method further includes: arranging a bias electrode on the surface of the semiconductor substrate where the to-be-detected doped region is located, wherein the bias electrode is located outside the to-be-detected doped region; the bias electrode is connected to a negative voltage when the first conductivity type is N-type, or to a positive voltage when the first conductivity type is P-type.
According to a second aspect, an embodiment of the present invention provides a test circuit for a semiconductor sheet resistor, in which a doped region to be tested is located in a semiconductor substrate and has a first conductivity type; at least one first doped region is formed in the region to be doped, the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; a second doped region is formed in the first doped region, and the second doped region is of the first conductivity type; the test circuit includes: at least two excitation electrodes arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping region; a direct current power supply, the positive electrode and the negative electrode of which are respectively connected with the two excitation electrodes so as to apply excitation current; the isolation layer and the control electrode are sequentially arranged on the surface of the semiconductor substrate, and the isolation layer and the control electrode extend from the edge of one first doped region to the edge of the internal second doped region; at least two probes disposed between the two excitation electrodes; and two testing ends of the voltage measuring device are respectively connected with the two probes and used for measuring the square resistance of the doped region to be measured.
Optionally, the first conductivity type is N-type and the second conductivity type is P-type. Or the first conduction type is P type, and the second conduction type is N type.
Optionally, the wiring of the probe is parallel to the wiring of the excitation electrode.
Optionally, the probe is disposed on a line connecting the two excitation electrodes.
Optionally, the test circuit further comprises: and the processor is respectively connected with the direct current power supply and the voltage measuring device so as to respectively obtain the excitation current and the voltage between the probes during testing and calculate the square resistance of the doped region to be tested.
Optionally, the method further comprises: the bias electrode and the to-be-detected doped region are positioned on the same surface of the semiconductor substrate, and the bias electrode is positioned outside the to-be-detected doped region; and a bias power supply, wherein when the first conduction type is an N type, the negative pole of the bias power supply is connected with the bias electrode, or when the first conduction type is a P type, the positive pole of the bias power supply is connected with the bias electrode.
The embodiment of the invention provides a method and a circuit for testing a semiconductor square resistor, which have the following advantages:
1. the method for testing the square resistance of the semiconductor provided by the embodiment of the invention comprises the following steps: forming at least one first doped region in the doped region to be tested, wherein the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming a second doped region in the first doped region, wherein the second doped region is of the first conductivity type; at least two excitation electrodes are arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping area; sequentially arranging at least one isolation layer and control electrodes corresponding to the isolation layer on the surface of the semiconductor substrate, wherein the isolation layer and the control electrodes extend from the edge of one first doping region to the edge of a second doping region inside the first doping region; and applying excitation current through the two excitation electrodes, and simultaneously testing the square resistance value of the doping area to be tested positioned between the two excitation electrodes. By arranging the first doping area, the isolation layer and the control electrode, a reverse biased Schottky junction cannot be formed when the doping area to be tested is tested, and a depletion layer cannot be formed in the doping area to be tested to influence a resistance test result, so that the test circuit of the semiconductor square resistance can test a more accurate square resistance value.
2. According to the test circuit of the semiconductor square resistor, provided by the embodiment of the invention, the doped region to be tested is positioned in the semiconductor substrate and is of a first conductivity type; at least one first doped region is formed in the region to be doped, the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; a second doped region is formed in the first doped region, and the second doped region is of the first conductivity type; the test circuit includes: at least two excitation electrodes arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping region; a direct current power supply, the positive electrode and the negative electrode of which are respectively connected with the two excitation electrodes so as to apply excitation current; the isolation layer and the control electrode are sequentially arranged on the surface of the semiconductor substrate, and the isolation layer and the control electrode extend from the edge of one first doped region to the edge of the internal second doped region; at least two probes disposed between the two excitation electrodes; and two testing ends of the voltage measuring device are respectively connected with the two probes and used for measuring the square resistance of the doped region to be measured. The test circuit of the semiconductor square resistor is provided with the first doping area, the isolation layer and the control electrode, so that a reverse biased Schottky junction cannot be formed when the doping area to be tested is tested, and a depletion layer cannot be formed in the doping area to be tested to influence the test result of the resistor, so that the test circuit of the semiconductor square resistor can be used for measuring a more accurate square resistance value.
Drawings
The features and advantages of the invention will be more clearly understood by reference to the accompanying drawings, which are schematic and should not be understood as showing any limitation of the invention, in which:
FIG. 1 shows a schematic view of a block-type thin film;
FIG. 2 shows a schematic diagram of the detection using Kelvin connections;
FIG. 3A is a schematic diagram of a prior art method for testing semiconductor sheet resistance using Kelvin connections;
FIG. 3B shows a schematic diagram of a forward biased Schottky barrier;
FIG. 3C shows a schematic diagram of a reverse-biased Schottky barrier;
FIG. 3D shows the direction of movement of carriers when testing semiconductor sheet resistance using Kelvin connections;
FIG. 3E is a graph showing the results of carrier depletion when testing semiconductor sheet resistance using Kelvin connections;
FIG. 4A is a schematic diagram of a test circuit for a semiconductor sheet resistor according to an embodiment of the present invention;
FIG. 4B is a schematic diagram illustrating a local electron distribution of a circuit for testing a semiconductor sheet resistance according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another semiconductor sheet resistance test circuit according to an embodiment of the present invention;
FIGS. 6A and 6B are schematic diagrams of a test circuit for testing a semiconductor sheet resistor according to another embodiment of the present invention;
FIG. 7 is a flow chart of a method for testing a semiconductor sheet resistance according to an embodiment of the present invention;
FIG. 8 is a flow chart of a method for testing a semiconductor sheet resistance according to an embodiment of the present invention;
FIG. 9A is a flow chart illustrating a method for testing a semiconductor sheet resistance according to another embodiment of the present invention;
FIG. 9B shows a top view of the surface of the semiconductor substrate where the excitation electrodes and probes are located;
FIG. 10A is a flow chart of another method for testing a semiconductor sheet resistance according to an embodiment of the present invention;
FIG. 10B shows a top view of the surface of the semiconductor substrate where the excitation electrodes and probes are located;
FIGS. 11A and 11B are flow charts illustrating another method for testing the sheet resistance of a semiconductor device according to an embodiment of the present invention;
11-a region to be doped; 12-a semiconductor substrate; 13. 15-a first doped region; 14. 16-a second doped region; a 17-ohmic contact region; 21. 22-an excitation electrode; 23-a bias electrode; 30-a direct current power supply; 41. 42-an isolation layer; 51. 52-control electrode; 61. 62-a probe; 70-a voltage measuring device; 80-bias power supply.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the first conductivity type in this application is N-type, and correspondingly the second conductivity type is P-type; alternatively, the first conductivity type is P-type, and correspondingly the second conductivity type is N-type.
The principle of the present invention is described in the embodiments of the present application only by using the first conductive type as the N-type and the second conductive type as the P-type, and on the basis of the technical solutions and the technical principles disclosed in the present application, a person skilled in the art should be able to deduce the principle of the technical solutions when the first conductive type is the P-type and the second conductive type is the N-type.
Example one
FIG. 4A is a schematic diagram of a test circuit for a semiconductor sheet resistor according to an embodiment of the invention. As shown in fig. 4A, the doped region to be tested 11 is located in the semiconductor substrate 12 and is of the first conductivity type. At least one first doped region 13 is formed in the region to be doped 11, the first doped region 13 is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type. A second doped region 14 is formed in the first doped region 13, the second doped region being of the first conductivity type.
The test circuit comprises at least two excitation electrodes 21 and 22, a direct current source 30, at least one isolation layer 41 and a control electrode 51 corresponding thereto, at least two probes 61 and 62, a voltage measuring device 70.
The positive and negative electrodes of the dc power supply 30 are connected to the two excitation electrodes, respectively, to apply excitation current.
The isolation layer 41 and the control electrode 51 are sequentially disposed on the surface of the semiconductor substrate 12, and both extend from the edge of the first doped region 13 to the edge of the second doped region 14 inside the first doped region 13.
The excitation electrodes 21 and 22 are both disposed on the surface of the semiconductor substrate 12, and the excitation electrode 22 corresponds to the second doping region 14. The other excitation electrode 21 may be in direct contact with an ohmic contact region (shown as 15 in fig. 4A) in the doping region 11 to be measured, which is used for making the semiconductor and the excitation electrode 21 form a good ohmic contact, and has an ion doping concentration higher than that of the doping region to be measured and the same doping type), or may also be in other arrangements (for example, the arrangement described in the second embodiment), which is not limited in this application. When the other excitation electrode 21 directly contacts the ohmic contact region in the doped region 11 to be tested, during testing, attention needs to be paid to control the corresponding relationship between the positive electrode and the negative electrode of the dc power supply 30 and the excitation electrodes 21 and 22, and the corresponding relationship must make the schottky junction between the excitation electrode 21 and the ohmic contact region forward biased, that is, the test circuit shown in fig. 4A should control the excitation electrode 21 to be connected to the positive electrode of the dc power supply 30, and control the excitation electrode 22 to be connected to the negative electrode of the dc power supply 30.
Two probes 61 and 62 are disposed between the two excitation electrodes. Two testing ends of the voltage measuring device 70 are respectively connected with the two probes 61 and 62, and are used for measuring the square resistance of the doped region to be measured.
The working principle of the test circuit for testing the semiconductor sheet resistor is described below with the first conductivity type being N-type and the second conductivity type being P-type.
In the test circuit shown in fig. 4A, when the control electrode 51 is not energized, although the second doped region 14 is connected to the negative electrode of the dc power supply 30, and the second doped region 14 and the doped region 11 to be tested have the same conductivity type, since the first doped region 13 with the opposite doping type is spaced therebetween, electrons in the second doped region 14 cannot flow into the doped region 11 to be tested through the first doped region 13, so as to form an electron path. When the control electrode 51 is connected to the positive electrode of the control power supply (as shown by "+") as shown in fig. 4B, electrons (i.e. minority carriers of the P-type doped region) in the first doped region 13 are adsorbed on the surface of the semiconductor by the control electrode 51, and since the isolation layer 41 is disposed between the control electrode 51 and the surface of the semiconductor substrate 12, electrons always form an electron layer (the electron layer is shown by a black dot in fig. 4B) on the surface of the semiconductor substrate 12 and do not flow into the control electrode, so that a flow path (e.g. path Pe in fig. 4B) of electrons is formed on the surface of the first doped region 13, and thus electrons input from the negative electrode of the dc power supply 30 to the excitation electrode 22 can flow into the second doped region 14 and then flow into the doped region to be measured 11 through the electron layer on the surface of the first doped region 13, thereby forming an electron path. As can be seen from comparing fig. 3E and fig. 4B, the test circuit of the semiconductor sheet resistor is provided with the first doping region 13, the isolation layer and the control electrode, so that a reverse biased schottky junction is not formed when the doping region to be tested is tested, and a depletion layer is not formed in the doping region to be tested 11 to affect the test result of the sheet resistance value, so that the test circuit of the semiconductor sheet resistor can measure a more accurate sheet resistance value.
Optionally, the voltage measuring device 70 is high impedance, so that the current in the detecting branch "probe 61-voltage measuring device 70-probe 62" is small enough, so that the parasitic resistance (see background section) and the contact resistance (see background section) in the detecting branch are small enough (almost zero), thereby further improving the testing accuracy of the square resistance.
Example two
FIG. 5 shows a schematic diagram of another test circuit for a semiconductor sheet resistance according to an embodiment of the invention. As can be seen from comparing fig. 4A and 5, the testing circuit differs from the first embodiment in that the ohmic contact region 15 is replaced by a first doped region 15 and a second doped region 16, and further includes an isolation layer 42 and a control electrode 52.
The first doped region 15 is located in the doped region to be measured 11 and is of the second conductivity type; the second doped region 16 is located within the first doped region 15 and is of the first conductivity type. The excitation electrode 21 corresponds to the second doping region 16. The isolation layer 42 and the control electrode 52 are sequentially disposed on the surface of the semiconductor substrate 12, and both extend from the edge of the first doped region 15 to the edge of the second doped region 16 inside the first doped region 15.
According to the test circuit of the semiconductor square resistor, the first doping area, the second doping area, the isolation layer and the control electrode are arranged at the positions of the two excitation electrodes, so that the two excitation electrodes are completely symmetrical, the corresponding relation between the positive electrode and the negative electrode of the power direct-current power supply 30 and the excitation electrodes 21 and 22 does not need to be particularly noticed during testing, and the test method is simplified.
In addition, in the test circuit shown in fig. 5, when the control electrode 52 is not powered, although the second doping region 16 is connected to the positive electrode of the dc power supply 30, and the second doping region 16 and the doping region 11 to be tested have the same conductivity type, since the first doping region 15 with the opposite doping type is spaced therebetween, electrons in the doping region 11 to be tested cannot flow into the second doping region 16 through the first doping region 15, so that an electron path is formed. When the control electrode 52 is connected to the positive electrode of the control power supply (as shown by "+") and referring to the principle shown in fig. 4B, electrons (i.e. minority carriers in the P-type doped region) in the first doped region 15 are adsorbed on the surface of the semiconductor by the control electrode 52, and since the isolation layer 42 is disposed between the control electrode 52 and the surface of the semiconductor substrate 12, electrons always form an electron layer on the surface of the semiconductor substrate 12 and do not flow into the control electrode, so that a flow path of electrons is formed on the surface of the first doped region 15, and electrons in the to-be-measured doped region 11 can flow into the second doped region 16 through the electron layer on the surface of the first doped region 15 and then flow to the positive electrode of the dc power supply 30. Therefore, the test circuit of the semiconductor square resistor is provided with the first doping area 15, the isolation layer and the control electrode, so that a forward biased Schottky junction cannot be formed during testing the square resistor, and a depletion layer cannot be formed in the doping area 11 to be tested to influence the test result of the resistor, so that the test circuit of the semiconductor square resistor further improves the test precision of the square resistor.
The test circuit of the semiconductor square resistor also prevents a reverse-biased Schottky junction from being formed when the doped region to be tested is tested, and prevents a depletion layer from being formed in the doped region 11 to be tested to influence the test result of the square resistance value, so that the test circuit of the semiconductor square resistor can test the more accurate square resistance value. Please refer to embodiment one.
EXAMPLE III
The embodiment of the present invention provides another testing circuit for a semiconductor sheet resistance, which is different from the first or second embodiment in that the testing circuit further includes a processor, which is connected to the dc power supply 30 and the voltage measuring device respectively, to obtain the excitation current I during testing and the voltage between the probes 61 and 62, and calculate the sheet resistance of the doped region 11 to be tested.
Example four
The embodiment of the present invention provides another test circuit for a semiconductor sheet resistor, which is different from any one of the first to third embodiments in that the test circuit further includes a bias electrode 23 and a bias power supply 80.
The bias electrode 23 and the doping region 11 to be measured are located on the same surface of the semiconductor substrate 12, and the bias electrode is located outside the doping region 11 to be measured. When the first conductivity type is N-type, the cathode of the bias power supply 80 is connected to the bias electrode 23, or when the first conductivity type is P-type, the anode of the bias power supply 80 is connected to the bias electrode 23.
As shown in fig. 6A and 6B, the first conductivity type is N-type, the bias electrode 23 is connected to the negative electrode of the bias power supply 80, and holes in the semiconductor substrate 12 near the bias electrode 23 are recombined by electrons of the negative electrode of the bias power supply 80, so that holes remaining in the semiconductor substrate 12 near the bias electrode 23 are far away from the surface where the bias electrode 23 is located (i.e. away from the doped region 11 to be tested), and the potential gradually increases from the surface to the inner part on the surface of the semiconductor substrate 12 where the bias electrode 23 is located, so that electrons in the doped region 11 to be tested are collected on the surface under the influence of the potential, and do not escape to the outside of the doped region 11 to be tested and thus affect the accuracy of the test. Therefore, the bias electrode is arranged on the surface of the semiconductor substrate where the to-be-tested doped region is located, and the test accuracy can be improved.
It should be added that, on the basis of the above technical solutions, a person skilled in the art should be able to think of forming the ohmic contact region 17 (as shown by the "P +" region in fig. 6A and 6B) inside the semiconductor substrate 12 at a position in contact with the bias electrode 23 to form a good ohmic contact, and the description of this application is omitted here.
EXAMPLE five
FIG. 7 is a flow chart illustrating a method for testing a semiconductor sheet resistance according to an embodiment of the present invention. The testing method is used for testing the square resistance of the doped region to be tested in the semiconductor substrate and can be realized by adopting the testing circuit in any one of the first embodiment, the third embodiment or the fourth embodiment. As shown in fig. 7, the method includes the steps of:
s10: forming at least one first doped region in the doped region to be tested, wherein the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; and forming a second doped region in the first doped region, the second doped region being of the first conductivity type.
As shown in fig. 4A, the first conductivity type is N-type, the doped region to be tested 11 is N-type doped, and the semiconductor substrate 12 is P-type doped. A first doped region 13 doped P-type is formed in the doped region 11 to be tested, and a second doped region doped N-type is formed in the first doped region 13. The second doped region 14 may be heavily doped to form a good ohmic contact with the actuation electrode 22.
S20: at least two excitation electrodes are disposed on the surface of the semiconductor substrate, wherein at least one of the excitation electrodes corresponds to the second doped region.
As shown in fig. 4A, excitation electrodes 21 and 22 are provided on the surface of the semiconductor substrate 12, wherein the excitation electrode 22 corresponds to the second doping region 14.
S31: at least one isolation layer and control electrodes corresponding to the isolation layer are sequentially arranged on the surface of the semiconductor substrate, and the isolation layer and the control electrodes extend from the edge of one first doping region to the edge of the inner second doping region.
As shown in fig. 4A, an isolation layer 41 and a control electrode 51 corresponding to the isolation layer 41 are sequentially disposed on the surface of the semiconductor substrate 12, and the isolation layer 41 and the control electrode 51 extend from the edge of the first doped region 13 to the edge of the second doped region 14 inside the first doped region 13.
S40: and applying excitation current through the two excitation electrodes, and simultaneously testing the square resistance value of the doping area to be tested positioned between the two excitation electrodes.
As shown in fig. 4A, the positive and negative electrodes of the dc power supply 30 are connected to the excitation electrodes 21 and 22, respectively, so as to apply an excitation current. Meanwhile, the doped region to be measured between the excitation electrodes 21 and 22 is contacted by the probes 61 and 62, and the probes 61 and 62 are connected to both ends of the voltage measuring device 70, respectively, so as to test the voltage between the two probes after the excitation current is applied.
According to the testing method of the semiconductor square resistor, the first doping area, the isolation layer and the control electrode are arranged, so that a reverse biased Schottky junction cannot be formed when the doping area to be tested is tested, and a depletion layer cannot be formed in the doping area to be tested to influence the square resistor testing result, so that the testing circuit of the semiconductor square resistor can be used for testing a more accurate square resistor value. Please specifically refer to the first embodiment.
In addition, it should be noted that, during testing, it is necessary to control the corresponding relationship between the positive electrode and the negative electrode of the dc power supply 30 and the excitation electrodes 21 and 22, and the corresponding relationship must be such that the schottky junction between the excitation electrode 21 and the ohmic contact region is forward biased, that is, the test circuit shown in fig. 4A should control the excitation electrode 21 to be connected to the positive electrode of the dc power supply 30, and control the excitation electrode 22 to be connected to the negative electrode of the dc power supply 30.
EXAMPLE six
FIG. 8 is a flow chart illustrating a method for testing a semiconductor sheet resistance according to an embodiment of the present invention. The testing method is used for testing the square resistance of the doped region to be tested in the semiconductor substrate and can be realized by adopting the testing circuit in any one of the second embodiment, the third embodiment or the fourth embodiment. As shown in fig. 8, the method includes the steps of:
s10: forming at least one first doped region in the doped region to be tested, wherein the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; and forming a second doped region in the first doped region, the second doped region being of the first conductivity type.
As shown in fig. 5, the first conductivity type is N-type, the doped region to be measured 11 is N-type doped, and the semiconductor substrate 12 is P-type doped. Forming a first doping area 13 doped with P type in the doping area 11 to be tested, and forming a second doping area 14 doped with N type in the first doping area 13; a first doped region 15 of P-type doping is formed in the doped region 11 to be tested, and a second doped region 16 of N-type doping is formed in the first doped region 15. The second doped regions 14 and 16 may be heavily doped to form a good ohmic contact with the actuation electrode 22.
S20: at least two excitation electrodes are disposed on the surface of the semiconductor substrate, wherein at least one of the excitation electrodes corresponds to an edge of the second doped region.
As shown in fig. 5, excitation electrodes 21 and 22 are provided on the surface of the semiconductor substrate 12, wherein the excitation electrode 21 corresponds to the second doping region 16, and the excitation electrode 22 corresponds to the second doping region 14.
S32: at least two isolation layers and control electrodes respectively corresponding to the isolation layers are sequentially arranged on the surface of the semiconductor substrate, and the isolation layers and the control electrodes extend from the edge of one first doping region to the edge of the inner second doping region.
As shown in fig. 5, an isolation layer 41 and a control electrode 51 corresponding to the isolation layer 41 are sequentially disposed on the surface of the semiconductor substrate 12, and the isolation layer 41 and the control electrode 51 extend from the edge of the first doped region 13 to the edge of the second doped region 14 inside the first doped region 13. Further, an isolation layer 42 and a control electrode 52 corresponding to the isolation layer 42 are sequentially provided on the surface of the semiconductor substrate 12, and the isolation layer 42 and the control electrode 52 extend from the edge of the first doped region 15 to the edge of the second doped region 16 inside the first doped region 15.
S40: and applying excitation current through the two excitation electrodes, and simultaneously testing the square resistance value of the doping area to be tested positioned between the two excitation electrodes.
As shown in fig. 5, the positive and negative electrodes of the dc power supply 30 are connected to the excitation electrodes 21 and 22, respectively, so as to apply an excitation current. Meanwhile, the doped region to be measured between the excitation electrodes 21 and 22 is contacted by the probes 61 and 62, and the probes 61 and 62 are connected to both ends of the voltage measuring device 70, respectively, so as to test the voltage between the two probes after the excitation current is applied.
According to the testing method of the semiconductor square resistor, the first doping area, the isolation layer and the control electrode are arranged, so that a reverse biased Schottky junction cannot be formed when the doping area to be tested is tested, and a depletion layer cannot be formed in the doping area to be tested to influence the square resistor testing result, so that the testing circuit of the semiconductor square resistor can be used for testing a more accurate square resistor value. Please specifically refer to the first embodiment.
In addition, according to the testing method of the semiconductor square resistor, the first doping area, the second doping area, the isolation layer and the control electrode are arranged at the positions of the two excitation electrodes, so that the two excitation electrodes are completely symmetrical, the corresponding relation between the positive electrode and the negative electrode of the power supply direct-current power supply and the sum of the excitation electrodes does not need to be particularly noticed during testing, and the testing method is simplified. Please specifically refer to the second embodiment.
EXAMPLE seven
FIG. 9A is a flow chart illustrating a method for testing a semiconductor sheet resistance according to an embodiment of the present invention. The testing method is used for testing the square resistance of the doped region to be tested in the semiconductor substrate, and can be realized by adopting the testing circuit in any one of the first to the fourth embodiments. As shown in fig. 9A, the difference from the fifth embodiment or the sixth embodiment is that the step of "testing the sheet resistance of the doped region to be tested located between the two excitation electrodes" in step S40 includes the following steps S41, S42, S43, and S44:
s41: at least one pair of probes is arranged between the two excitation electrodes, and the pair of probes comprises a first probe and a second probe; and measuring a distance between the first probe and the second probe.
FIG. 9B is a top view of the surface of the semiconductor substrate where the excitation electrodes and probes are located, where M1 and N1 are a pair of probes and M2 and N2 are a pair of probes.
S42: and acquiring the value of the excitation current.
S43: and testing the voltage value between the first probe and the second probe.
S44: calculating the square resistance value of the doping area to be measured according to the following formula:
wherein V is a voltage value between the first probe and the second probe, I is a numerical value of the excitation current, and n is a distance between the first probe and the second probe.
In the above formula, the ratio of the Vvoltage to the excitation current I is the resistance between the first probe and the second probe. It should be added that, as an alternative to this embodiment, the resistance between the first probe and the second probe can also be measured directly by using an ohmmeter.
Since the resistance of the square type thin film is only related to the thickness and resistivity ρ of the square type thin film, and is not related to the length and width of the square, assuming that the unit of the distance d is cm, the size of the square can be considered to be 1cm × 1cm, that is, the side length of the square is 1 unit, and the square is a unit area, it can be understood that N squares are located between the first probe and the second probe (as shown in fig. 9B, 2 squares are located between the first probe M1 and the second probe N1, and 3 squares are located between the first probe M2 and the second probe N2), so that the square resistance value per unit area can be expressed as:
furthermore, on the basis of the above method, a plurality of pairs of probes can be arranged to measure a plurality of block resistance values, and the block resistance values are processed (for example, averaged) to obtain the final block resistance value.
As shown in FIG. 9B, the probe lines are parallel to the excitation electrode lines (e.g., probes M1, N1, or M2, N2). And, optionally, the probe is placed on the line connecting the two excitation electrodes (e.g., probes M1, N1).
Example eight
FIG. 10A is a flow chart illustrating a method for testing a semiconductor sheet resistance according to an embodiment of the present invention. The testing method is used for testing the square resistance of the doped region to be tested in the semiconductor substrate, and can be realized by adopting the testing circuit in any one of the first to the fourth embodiments. As shown in fig. 10A, the difference from the fifth embodiment or the sixth embodiment is that the step of "testing the sheet resistance of the doped region to be tested located between the two excitation electrodes" in step S40 includes the following steps S45, S46, S47, and S48:
s45: arranging at least one group of probes between the two excitation electrodes, wherein the group of probes comprises a first probe, a second probe and a third probe; and measuring a distance between the second probe and the first probe, and a distance between the second probe and the third probe.
S46: and respectively testing the voltage value between the second probe and the first probe and the voltage value between the second probe and the third probe.
S47: and acquiring the value of the excitation current.
For example, it can be read from the dc power supply 30 in the first embodiment.
S48: calculating the block resistance value of the region to be doped according to the following formula:
wherein R issqIs the square resistance to be measured, V21Is the voltage value between the second probe and the first probe, V23Is the voltage value between the second probe and the third probe, n21Is the distance between the second probe and the first probe, n23Is the distance between the second probe and the third probe, and I is the value of the excitation current.
Fig. 10B is a top view of the surface of the semiconductor substrate where the excitation electrodes and the probes are located, wherein L1, L2, and L3 are the first probe, the second probe, and the third probe, respectively, and the three probes are a set of probes. Since the resistance of a square film is dependent only on the thickness and resistivity ρ of the square film, and not on the length and width of the square, assume that the distance n21、n23When the unit of (A) is cm, the size of the square block is 1cm × 1cm, that is, the side length of the square block is 1 unit, and the square block is a unit area, it can be understood that n is between the second probe and the first probe21Each square (as shown in FIG. 10B, there are 3 squares between the second probe and the first probe), and n is between the second probe and the third probe23Each square (as shown in fig. 10B, there are 2 squares between the second probe and the first probe), so that the voltage between the second probe L2 and the first probe L1 and the voltage between the second probe L2 and the third probe L3 can be expressed as:
V21＝I*(Rsq*n21)，V23＝I*(Rsq*n23)
thus, V21-V21＝I*(Rsq*n21)-I*(Rsq*n23) After finishing, can obtain
The square resistance value RsqIs just a square block ofThe square resistance per unit area.
Optionally, the resistance value between the two positions is tested by a high-impedance voltage testing device, so that the testing accuracy of the square resistor can be improved, as shown in the first embodiment.
Furthermore, on the basis of the above method, several sets of probes can be arranged to measure several square resistance values, and the square resistance values are processed (e.g., averaged) to obtain the final square resistance value.
Alternatively, the wiring of one set of probes (e.g., L1, L2, L3 in fig. 10B) is parallel to the wiring of the excitation electrodes. And, optionally, the probe is disposed on a line connecting the two excitation electrodes.
Example nine
FIGS. 11A and 11B are flow charts illustrating a method for testing a sheet resistance of a semiconductor device according to another embodiment of the present invention. The test method is used for testing the square resistance of the doped region to be tested in the semiconductor substrate, and can be realized by adopting the test circuit described in the fourth embodiment. The testing method of any one of the fifth to eighth embodiments is different from the testing method of any one of the fifth to eighth embodiments in that the testing method further includes, before step S40, S51 and S52:
s51: and arranging a bias electrode on the surface of the semiconductor substrate where the to-be-detected doped region is located, wherein the bias electrode is positioned outside the to-be-detected doped region.
S52: the bias electrode is connected to a negative voltage when the first conductivity type is N-type, or to a positive voltage when the first conductivity type is P-type.
By arranging the bias electrode and connecting the bias electrode with the positive electrode or the negative electrode, the accuracy of the test can be improved. See example four for details.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (13)
1. A test method of semiconductor square resistance is disclosed, a doping area to be tested is positioned in a semiconductor substrate and is of a first conductivity type; characterized in that the method comprises:
forming at least one first doped region in the doped region to be tested, wherein the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; forming a second doped region in the first doped region, wherein the second doped region is of a first conductivity type;
at least two excitation electrodes are arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping area;
sequentially arranging at least one isolation layer and control electrodes corresponding to the isolation layer and the control electrodes on the surface of the semiconductor substrate, wherein the isolation layer and the control electrodes extend from the edge of one first doping region to the edge of the second doping region inside the first doping region;
and applying excitation current through the two excitation electrodes, and testing the voltage between the to-be-tested doped regions positioned between the two excitation electrodes to obtain the square resistance value of the to-be-tested doped region.
2. The method as claimed in claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type; alternatively, the first and second electrodes may be,
the first conductive type is a P type, and the second conductive type is an N type.
3. The method as claimed in claim 1, wherein the step of testing the sheet resistance of the doped region to be tested between the two excitation electrodes comprises:
disposing at least one pair of probes between the two excitation electrodes, the pair of probes comprising a first probe and a second probe; and measuring a distance between the first probe and the second probe;
acquiring a value of the excitation current;
testing a voltage value between the first probe and the second probe;
calculating the square resistance value of the doping area to be measured according to the following formula:
wherein V is a voltage value between the first probe and the second probe, I is a numerical value of the excitation current, and n is a distance between the first probe and the second probe.
4. The method as claimed in claim 1, wherein the step of testing the sheet resistance of the doped region to be tested between the two excitation electrodes comprises:
disposing at least one set of probes between the two excitation electrodes, the set of probes comprising a first probe, a second probe, and a third probe; and measuring a distance between the second probe and the first probe, and a distance between the second probe and the third probe;
respectively testing the voltage value between the second probe and the first probe and the voltage value between the second probe and the third probe;
acquiring a value of the excitation current;
calculating the square resistance value of the doping area to be measured according to the following formula:
wherein R issqIs the square resistance value to be measured, V21Is the value of the voltage, V, between the second probe and the first probe23Is the value of the voltage between the second probe and the third probe, n21Is the distance between the second probe and the first probe, n23Is the distance between the second probe and the third probe, and is the value of the excitation current.
5. The method as claimed in claim 3 or 4, wherein the probe is disposed on a connection line of the two excitation electrodes.
6. The method of claim 3, wherein the voltage between the two locations is tested by a high impedance voltage testing device.
7. The method of claim 1, wherein prior to the step of applying the excitation current through two excitation electrodes and simultaneously testing the sheet resistance of the doped region to be tested located between the two excitation electrodes, the method further comprises:
arranging a bias electrode on the surface of the semiconductor substrate where the to-be-detected doped region is located, wherein the bias electrode is located outside the to-be-detected doped region;
and connecting the bias electrode with a negative voltage when the first conduction type is an N type, or connecting the bias electrode with a positive voltage when the first conduction type is a P type.
8. A test circuit of a semiconductor square resistor is characterized in that a doping area to be tested is positioned in a semiconductor substrate and is of a first conductivity type; at least one first doped region is formed in the doped region to be tested, the first doped region is of a second conductivity type, and the second conductivity type is opposite to the first conductivity type; a second doped region is formed in the first doped region, and the second doped region is of a first conductivity type; the test circuit includes:
at least two excitation electrodes arranged on the surface of the semiconductor substrate, wherein at least one excitation electrode corresponds to the second doping region;
a direct current power supply, the positive electrode and the negative electrode of which are respectively connected with the two excitation electrodes so as to apply excitation current;
the isolation layer and the control electrode are sequentially arranged on the surface of the semiconductor substrate, and the isolation layer and the control electrode extend from the edge of one first doping region to the edge of the second doping region inside the semiconductor substrate;
at least two probes disposed between the two excitation electrodes;
and two testing ends of the voltage measuring device are respectively connected with the two probes and used for measuring the square resistance of the doped region to be measured.
9. The semiconductor square resistor testing circuit of claim 8, wherein the first conductivity type is N-type and the second conductivity type is P-type; alternatively, the first and second electrodes may be,
the first conductive type is a P type, and the second conductive type is an N type.
10. The semiconductor square resistor test circuit of claim 8, wherein the trace of the probe is parallel to the trace of the excitation electrode.
11. The semiconductor square resistor test circuit of claim 10, wherein the probe is disposed on a connection line of the two excitation electrodes.
12. The semiconductor square resistor test circuit of claim 8, wherein the test circuit further comprises:
and the processor is respectively connected with the direct current power supply and the voltage measuring device so as to respectively obtain the excitation current and the voltage between the probes during testing and calculate the square resistance of the doped region to be tested.
13. The circuit for testing a semiconductor square resistor of claim 8, further comprising:
the bias electrode and the to-be-detected doped region are positioned on the same surface of the semiconductor substrate, and the bias electrode is positioned outside the to-be-detected doped region;
and the cathode of the bias power supply is connected with the bias electrode when the first conduction type is the N type, or the anode of the bias power supply is connected with the bias electrode when the first conduction type is the P type.
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