CN104600103A - High-voltage semiconductor device, high-voltage semiconductor device terminal and manufacturing method thereof - Google Patents
High-voltage semiconductor device, high-voltage semiconductor device terminal and manufacturing method thereof Download PDFInfo
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- CN104600103A CN104600103A CN201310529071.6A CN201310529071A CN104600103A CN 104600103 A CN104600103 A CN 104600103A CN 201310529071 A CN201310529071 A CN 201310529071A CN 104600103 A CN104600103 A CN 104600103A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Abstract
The invention provides a high-voltage semiconductor device, a high-voltage semiconductor device terminal and a manufacturing method thereof. The high-voltage semiconductor device terminal comprises a substrate, a field limiting ring which is positioned on the substrate, surface reinforcing layers positioned at two sides of the field limiting ring, field oxidation layers positioned on the surface reinforcing layers, field plates positioned on the field limiting ring and the field oxidation layers, and passivation layers positioned on the field plates; the surface reinforcing layers have the same conductive type as the substrate, and the dosage concentration of the surface reinforcing areas is more than that of the substrate. According to the high-voltage conductor device terminal, the surface concentration of the field limiting ring is increased to reduce the influence of variable charge on the surface electric field of the high-voltage conductor device terminal as well as stabilizing the surface electric field of the high-voltage conductor device terminal, and therefore, the leakage current of the high-voltage conductor device terminal at high temperature can be decreased, and the pressure resisting reliability is improved; in addition, the manufacturing process is simple.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of high-voltage semi-conductor device, high-voltage semi-conductor device terminal and manufacture method thereof.
Background technology
In high-voltage semi-conductor device, the curvature effect of planar junction makes knot sweep and surface electric field increase, and limits the puncture voltage of device.Up to now, in order to realize the blocking ability of high-voltage semi-conductor device, develop multiple high-voltage semi-conductor device terminal technology, as skewed surface (Bevel Surface) technology, field limiting ring technology (field limiting rings, FLR), field plate (field plate, FP) technology, variety lateral doping (Variation of Lateral Doping, VLD) technology, semi-insulating polysilicon (semi insulatingpolycrystalline silicon, SIPOS) technology, weaken surface field (Reduced Surface Field, RESURF) technology and knot termination extension (Junction Termination, JTE) technology etc.
Above-mentioned high-voltage semi-conductor device terminal technology has the advantage compatible with planar technique, and cost reduces greatly, but also faces three identical problems.The first, design must consider the impact of many many factors such as junction depth, substrate concentration, ring width, ring spacing, surface concentration, surface charge, is difficult to obtain targeted breakdown voltage by analytic method, need be optimized design by simulation software.Second, the puncture voltage of device is subject to the impact introducing movable charge in semiconductor surface interface charge and normal process process, in order to stable puncture voltage, process means (as strengthened quality of oxide layer, carrying out hydrogen treat etc. to silicon face) need be utilized to eliminate the impact of unnecessary electric charge as far as possible.3rd, under the high temperature conditions, leakage current is bigger than normal even occurs that continuing increase can not stablize to device, and after recovering normal temperature, puncture voltage reduces the phenomenon even occurring short circuit, and device electric breakdown strength is higher, and required substrate doping is lower, and this phenomenon is more obvious.
Above-mentioned first kind problem generally can be solved by optimizing Terminal Design well.But second, third class problem and device layout, technique are prepared and encapsulates comparatively Important Relations, it is one of Major Difficulties of high-voltage semi-conductor device exploitation.It is generally acknowledged, rear two class problems are mainly caused by device inside and the outside movable charge introduced.In real work, movable charge moves under outside stress condition, will change originally stable surface field, thus withstand voltagely changing of making, even there is the problem that leakage current increases.
At present, solve the technical method of this problem mainly from two aspects: on the one hand, reduce the factor of chip manufacturing proces and encapsulation process introducing movable charge as far as possible.Such as adopt special surface passivation technique or adopt high reliability synthetic resin to encapsulate, to reduce the introducing that external charge and steam etc. stain.This has significant effect to device creepage under reduction high temperature.But the method requires very high to encapsulation technology and process costs is higher.On the other hand, adopt special design structure to strengthen the shielding action of chip to movable charge itself, thus improve the electric leakage performance of device under HTHP stress condition.Such as, adopt semi-insulating polysilicon structure, it utilizes semi-insulating film resistor one end to connect main knot, and one end connects cut-off ring.Under the reverse-biased condition of high pressure, semi-insulating resistance two ends will produce electric field, and this electric field can shield the impact of movable charge on terminal end surface electric field, thus improve device test under high-temperature and high-pressure conditions after puncture performance.Semi-insulating film is generally by carrying out oxygen-doped or nitrogen formation to polysilicon, resistivity requires 10
7~ 10
10between ohm meter.Therefore, adopt semi-insulating polysilicon structure, complex technical process, film resistor quality accurately must control according to design.This structure adopts semi-insulating resistance to be directly connected across between high pressure and ground, will produce the power consumption of can not ignore under normal running conditions; Meanwhile, film resistor has higher temperature coefficient, also there is certain stability problem.So although leakage current is large under above-mentioned two kinds of methods can improve high-voltage semi-conductor device terminal high temperature in mobile degree, the shortcoming that withstand voltage reliability is low, manufacturing process is complicated.
Summary of the invention
Based on this, be necessary to provide a kind of high-voltage semi-conductor device terminal, under it has high temperature, leakage current is little, the advantage that withstand voltage reliability is high, and manufacturing process is simple.
A kind of high-voltage semi-conductor device terminal, comprise substrate, the field limiting ring be positioned on substrate, the surface enhanced district being positioned at field limiting ring both sides, the field oxide be positioned in surface enhanced district, the passivation layer that is positioned at the field plate on field limiting ring and field oxide and is positioned on field plate, described surface enhanced district is identical with the conduction type of substrate, and the doping content in described surface enhanced district is greater than the doping content of substrate.
Wherein in an embodiment, described passivation layer comprises the first passivation layer and is positioned at the second passivation layer on the first passivation layer.
Wherein in an embodiment, the material of described second passivation layer is polyimides.
Wherein in an embodiment, described substrate is N-type substrate, and the impurity adulterated in described surface enhanced district is N-type impurity, and the square resistance in described surface enhanced district is 400 Ω/ ~ 6000 Ω/.
Wherein in an embodiment, the width in described surface enhanced district is greater than the distance between adjacent two field limiting rings.
A kind of high-voltage semi-conductor device, comprises above-mentioned high-voltage semi-conductor device terminal.
Wherein in an embodiment, described high-voltage semi-conductor device is double-diffusion metal-oxide-semiconductor field effect transistor or insulated gate bipolar transistor.
A kind of high-voltage semi-conductor device terminal manufacture method, comprises the following steps: provide substrate; Form field oxide, field limiting ring and surface enhanced district over the substrate, described surface enhanced district is positioned at field limiting ring both sides, and described surface enhanced district is identical with the conduction type of substrate, and the doping content in described surface enhanced district is greater than the doping content of substrate; Described field limiting ring and field oxide form field plate; Described field plate forms passivation layer.
Wherein in an embodiment, described substrate is N-type substrate, and the impurity adulterated in described surface enhanced district is N-type impurity, and the implantation dosage of described N-type impurity is 2e11 ~ 1e13cm
-2, Implantation Energy is 60keV ~ 120keV.
Wherein in an embodiment, described passivation layer comprises the first passivation layer and is positioned at the second passivation layer on the first passivation layer.
Above-mentioned high-voltage semi-conductor device terminal is by strengthening the surface concentration of field limiting ring, to reduce the impact of movable charge on high-voltage semi-conductor device terminal end surface electric field, the surface field of stable high voltage semiconductor device terminal, thus the leakage current reduced under high-voltage semi-conductor device terminal high temperature, strengthen its withstand voltage reliability.In addition, this high-voltage semi-conductor device terminal only increases the step of the surface concentration strengthening field limiting ring during fabrication, and manufacturing process is relatively simple.
Accompanying drawing explanation
Fig. 1 is conventional high-voltage semi-conductor device terminal structure situation schematic diagram corresponding to surface field;
Fig. 2 is the high-voltage semi-conductor device terminal structure schematic diagram of embodiment 1;
Structural representation when Fig. 3 is double-diffusion metal-oxide-semiconductor field effect transistor Application Example 1 mesohigh semiconductor device terminal;
Structural representation when Fig. 4 is insulated gate bipolar transistor Application Example 1 mesohigh semiconductor device terminal;
Fig. 5 is the manufacture method flow chart for the pressure semiconductor device terminal shown in Fig. 2;
Fig. 6 ~ 13 are the structural representation of pressure semiconductor device terminal corresponding in the pressure semiconductor device terminal manufacture method flow process shown in Fig. 5.
Embodiment
Embodiment 1
Please refer to Fig. 2, an embodiment of the invention provide a kind of high-voltage semi-conductor device terminal 200.This high-voltage semi-conductor device terminal 200 comprises substrate 210, the field limiting ring 220 be positioned on substrate 210, the surface enhanced district 230 being positioned at field limiting ring 220 both sides, the field oxide 250 be positioned in surface enhanced district 230, the field plate 240 be positioned on field limiting ring 220 and field oxide 250, be positioned at the passivation layer on field plate 240 and be positioned at the metal layer on back 280 at substrate 210 back side.Surface enhanced district 230 is identical with the conduction type of substrate 210, and the doping content in surface enhanced district 230 is greater than the doping content of substrate 210.
The field oxide 250 of this high-voltage semi-conductor device terminal 200 is also provided with one deck dielectric layer 251, and passivation layer is located on dielectric layer 251.In this embodiment, passivation layer comprises the first passivation layer 260 and the second passivation layer 270 be positioned on the first passivation layer 260.The material of the first passivation layer 260 is silicon nitride, and the material of the second passivation layer 270 is polyimides.The thickness of the second passivation layer 270 is 4 microns to 18 microns.Adopt the structure of passivation layers herein except can stopping the advantage that extraneous mobile ion, steam etc. stain, the movable charge effects on surface state that this structure can also introduce chip internal effectively in shielding process preparation process impacts.
The substrate 210 of this high-voltage semi-conductor device terminal 200 is N-type substrate, and field limiting ring 220 is the doping of P type, and the impurity adulterated in surface enhanced district 230 is N-type impurity.In surface enhanced district 230, the implantation dosage of N-type impurity is 2e11 ~ 1e13cm
-2, Implantation Energy is 60keV ~ 120keV.The square resistance in surface enhanced district 230 is 400 Ω/ ~ 6000 Ω/.The width in surface enhanced district 230 is greater than the distance between adjacent two field limiting rings 220, and the field limiting ring 220 that is surface enhanced district 230 is adjacent with two is connected.The square resistance of field limiting ring 220 is 10 Ω/ ~ 1200 Ω/.
Please also refer to Fig. 1 and Fig. 2, the high-voltage semi-conductor device terminal 100 in Fig. 1 comprises substrate 110, the field limiting ring 120 be positioned on substrate 110, the field oxide 150 be positioned on substrate 110 and field limiting ring 120, be positioned at the field plate 140 on field limiting ring 120 and field oxide 150 and be positioned at the first passivation layer 160 on field plate 140.As seen from Figure 1, under HTHP stress condition (circuit connecting mode as shown in Figure 1), cation shakes off the constraint of potential field around after obtaining certain energy, become free charge, moved to cold end by the hot end of high-voltage semi-conductor device terminal 100, the region clustering between field limiting ring 120, surface field is herein increased, leakage current increases and even can not stablize, and causes puncture voltage to reduce even short circuit further.So the withstand voltage poor reliability of this high-voltage semi-conductor device terminal 100.
The region of high-voltage semi-conductor device terminal 200 between field limiting ring 220 in this embodiment adds surface enhanced district 230, between such field limiting ring 220, the surface concentration in region is increased, and is the surface concentration being strengthened region between field limiting ring 220 by ion implantation technology herein.Under high-temperature and high-pressure conditions, movable charge has high potential to move to electronegative potential in passivation layer, and between field limiting ring 220, field plate 240 place in region assembles.By strengthening the surface concentration in region between field limiting ring 220, device surface equivalence electric charge increases, thus corresponding reduction movable charge is on the impact of high-voltage semi-conductor device terminal 200 surface field, improve high-voltage semi-conductor device terminal 200 withstand voltage, thus the leakage current under reduction higher device temperature, strengthen its withstand voltage reliability.So under this high-voltage semi-conductor device terminal 200 has high temperature, leakage current is little, the advantage that withstand voltage reliability is high.In addition, this high-voltage semi-conductor device terminal 200 only need increase the step of the surface concentration strengthening field limiting ring during fabrication, and manufacturing process is relatively simple.
Embodiment 2
Another embodiment of the invention provides a kind of high-voltage semi-conductor device.This high-voltage semi-conductor device can be double-diffusion metal-oxide-semiconductor field effect transistor, insulated gate bipolar transistor or other high-voltage semi-conductor device.This high-voltage semi-conductor device to have in embodiment 1 high-voltage semi-conductor device terminal 200 as shown in Figure 2.Please refer to Fig. 3 and Fig. 4, the double-diffusion metal-oxide-semiconductor field effect transistor in Fig. 3 has structure and high-voltage semi-conductor device terminal 200 structure of double-diffusion metal-oxide-semiconductor field effect transistor.Insulated gate bipolar transistor in Fig. 4 has structure and high-voltage semi-conductor device terminal 200 structure of insulated gate bipolar transistor.With conventional double-diffusion metal-oxide-semiconductor field effect transistor and insulated gate bipolar transistor structural similarity, difference, double-diffusion metal-oxide-semiconductor field effect transistor herein and the structure of insulated gate bipolar transistor are only that they have the structure of the high-voltage semi-conductor device terminal 200 in embodiment 1.Because leakage current is little under high-voltage semi-conductor device terminal 200 has high temperature, the advantage that withstand voltage reliability is high, therefore under this high-voltage semi-conductor device (double-diffusion metal-oxide-semiconductor field effect transistor and insulated gate bipolar transistor) also has high temperature, leakage current is little, the advantage that withstand voltage reliability is high, and manufacturing process is simple.
Embodiment 3
Another execution mode of the present invention provides a kind of high-voltage semi-conductor device terminal 200 manufacture method.This high-voltage semi-conductor device terminal 200 is high-voltage semi-conductor device terminal 200 as shown in Figure 2 in embodiment 1.Please refer to Fig. 5, this high-voltage semi-conductor device terminal 200 manufacture method comprises the following steps.
Step S110, provides substrate 210.Herein, this substrate 210 is N-type substrate 210.
Step S120, substrate 210 is formed field oxide 250, field limiting ring 220 and surface enhanced district 230, surface enhanced district 230 is positioned at field limiting ring 220 both sides, and surface enhanced district 230 is identical with the conduction type of substrate 210, and the doping content in surface enhanced district 230 is greater than the doping content of substrate 210.The growth step in oxide layer, field limiting ring 220 and surface enhanced district 230 will be introduced in detail below.
Please refer to Fig. 6, substrate 210 grows the field oxide 250 that a layer thickness is 1000 dust ~ 3000 dusts.Then, after the step such as gluing, exposure, hard baking, etching, ion implantation is carried out.Now ion implantation dosage is 2e11 ~ 1e13cm
-2, ion implantation energy is 60keV ~ 120keV, and ion during ion implantation is N-type impurity.
Please refer to Fig. 7, carry out after ion implantation removing photoresist, the step such as cleaning, the aerobic environment then carrying out 1100 DEG C ~ 1200 DEG C pushes away trap and forms surface enhanced district 230, grows the field oxide 250 of 6000 dust ~ 20000 dusts simultaneously.Field oxide 250 is carried out thickening and covering surfaces enhancement region 230 herein.
Please refer to Fig. 8, the step such as field oxide 250 carries out gluing, exposure, wet etching, remove photoresist, then carry out ion implantation.Now ion implantation dosage is 1e13 ~ 1e15cm
-2energy is 60keV ~ 120keV, and ion during ion implantation is p type impurity.
Please refer to Fig. 9, after ion implantation, carry out the steps such as cleaning, and in the nitrogen environment of 1100 DEG C ~ 1200 DEG C, push away trap formation field limiting ring 220.
Please refer to Figure 10, on field oxide 250, the boron-phosphorosilicate glass (boro-phospho-silicate-glass, BPSG) of deposit 8000 dust ~ 16000 dust, refluxes at 850 DEG C ~ 950 DEG C, forms dielectric layer 251.
Step S130, field limiting ring 220 and field oxide 250 form field plate 240.Please refer to Figure 11, after formation dielectric layer 251, carry out gluing, exposure, etch, the step such as to remove photoresist, then deposit front metal thus form field plate 240 on field limiting ring 220 and field oxide 250.
Step S140, field plate 240 forms passivation layer.Please refer to Figure 12, after formation field plate 240, carry out gluing, exposure, wet etching, the step such as to remove photoresist, then deposit first passivation layer 260.The material of the first passivation layer 260 is herein silicon nitride.Please refer to Figure 13, carry out gluing, expose, remove photoresist, after 380 DEG C ~ 450 DEG C steps such as annealing solidifications etc., deposit forms the second passivation layer 270.The material of the second passivation layer 270 is polyimides herein.
This high-voltage semi-conductor device terminal 200 manufacture method also comprises step S150, forms metal layer on back 280.As shown in Figure 2, metal layer on back 280 is formed in the back side deposit of substrate 210.
The manufacture of this high-voltage semi-conductor device terminal 200 is just completed through above-mentioned processing step.This high-voltage semi-conductor device terminal 200 manufacture method adopts the technology completely compatible with planar technique, and manufacturing process is simple.The surface concentration of field limiting ring 220 is strengthened by ion implantation, to reduce the impact of movable charge on high-voltage semi-conductor device terminal 200 surface field, the surface field of stable high voltage semiconductor device terminal 200, thus the leakage current reduced under high-voltage semi-conductor device terminal 200 high temperature, strengthen its withstand voltage reliability.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a high-voltage semi-conductor device terminal, it is characterized in that, comprise substrate, the field limiting ring be positioned on substrate, the surface enhanced district being positioned at field limiting ring both sides, the field oxide be positioned in surface enhanced district, the passivation layer that is positioned at the field plate on field limiting ring and field oxide and is positioned on field plate, described surface enhanced district is identical with the conduction type of substrate, and the doping content in described surface enhanced district is greater than the doping content of substrate.
2. high-voltage semi-conductor device terminal according to claim 1, is characterized in that, described passivation layer comprises the first passivation layer and is positioned at the second passivation layer on the first passivation layer.
3. high-voltage semi-conductor device terminal according to claim 2, is characterized in that, the material of described second passivation layer is polyimides.
4. high-voltage semi-conductor device terminal according to claim 1, is characterized in that, described substrate is N-type substrate, and the impurity adulterated in described surface enhanced district is N-type impurity, and the square resistance in described surface enhanced district is 400 Ω/ ~ 6000 Ω/.
5. high-voltage semi-conductor device terminal according to claim 1, is characterized in that, the width in described surface enhanced district is greater than the distance between adjacent two field limiting rings.
6. a high-voltage semi-conductor device, is characterized in that, comprises the high-voltage semi-conductor device terminal as described in claim 1 to 5.
7. high-voltage semi-conductor device according to claim 6, is characterized in that, described high-voltage semi-conductor device is double-diffusion metal-oxide-semiconductor field effect transistor or insulated gate bipolar transistor.
8. a high-voltage semi-conductor device terminal manufacture method, is characterized in that, comprises the following steps:
Substrate is provided;
Form field oxide, field limiting ring and surface enhanced district over the substrate, described surface enhanced district is positioned at field limiting ring both sides, and described surface enhanced district is identical with the conduction type of substrate, and the doping content in described surface enhanced district is greater than the doping content of substrate;
Described field limiting ring and field oxide form field plate;
Described field plate forms passivation layer.
9. high-voltage semi-conductor device terminal manufacture method according to claim 8, is characterized in that, described substrate is N-type substrate, and the impurity adulterated in described surface enhanced district is N-type impurity, and the implantation dosage of described N-type impurity is 2e11 ~ 1e13cm
-2, Implantation Energy is 60keV ~ 120keV.
10. high-voltage semi-conductor device terminal manufacture method according to claim 8, is characterized in that, described passivation layer comprises the first passivation layer and is positioned at the second passivation layer on the first passivation layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310529071.6A CN104600103A (en) | 2013-10-30 | 2013-10-30 | High-voltage semiconductor device, high-voltage semiconductor device terminal and manufacturing method thereof |
| PCT/CN2014/088609 WO2015062411A1 (en) | 2013-10-30 | 2014-10-15 | High voltage semiconductor device, high voltage semiconductor device terminal, and method of fabricating same |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310529071.6A CN104600103A (en) | 2013-10-30 | 2013-10-30 | High-voltage semiconductor device, high-voltage semiconductor device terminal and manufacturing method thereof |
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| CN104600103A true CN104600103A (en) | 2015-05-06 |
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| CN106783958A (en) * | 2016-12-29 | 2017-05-31 | 丽晶美能（北京）电子技术有限公司 | Pressure-resistant terminal ring structure and power device |
| CN106783959A (en) * | 2016-12-29 | 2017-05-31 | 丽晶美能（北京）电子技术有限公司 | Pressure-resistant terminal ring structure and power device |
| CN106847878A (en) * | 2016-12-29 | 2017-06-13 | 丽晶美能（北京）电子技术有限公司 | Pressure-resistant terminal ring structure and power device |
| CN107910356A (en) * | 2017-10-24 | 2018-04-13 | 全球能源互联网研究院 | A kind of efficient terminal structure of vertical-type high voltage power device and preparation method thereof |
| CN109444551A (en) * | 2018-09-10 | 2019-03-08 | 全球能源互联网研究院有限公司 | The test method and test circuit of semiconductor square resistance |
| WO2022067750A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | Terminal structure of power device, fabrication method therefor, and power device |
| CN114725188A (en) * | 2022-04-01 | 2022-07-08 | 无锡市谷峰半导体有限公司 | IGBT terminal capable of reducing field limiting ring width and preparation method thereof |
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| CN108922888B (en) * | 2018-08-31 | 2023-06-06 | 江苏丽隽功率半导体有限公司 | Terminal structure of power device and manufacturing method thereof |
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| WO2022067750A1 (en) * | 2020-09-30 | 2022-04-07 | 华为技术有限公司 | Terminal structure of power device, fabrication method therefor, and power device |
| CN114725188A (en) * | 2022-04-01 | 2022-07-08 | 无锡市谷峰半导体有限公司 | IGBT terminal capable of reducing field limiting ring width and preparation method thereof |
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|---|---|
| WO2015062411A1 (en) | 2015-05-07 |
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