CN103839978B - A kind of terminal structure of mesohigh slot type power device and preparation method thereof - Google Patents
A kind of terminal structure of mesohigh slot type power device and preparation method thereof Download PDFInfo
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- CN103839978B CN103839978B CN201310086262.XA CN201310086262A CN103839978B CN 103839978 B CN103839978 B CN 103839978B CN 201310086262 A CN201310086262 A CN 201310086262A CN 103839978 B CN103839978 B CN 103839978B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000002347 injection Methods 0.000 claims abstract description 30
- 239000007924 injection Substances 0.000 claims abstract description 30
- 239000000945 filler Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 41
- 238000002161 passivation Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000005520 cutting process Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
Abstract
The invention discloses a kind of terminal structure of mesohigh slot type power device and preparation method thereof, belong to semiconductor power device preparing technical field.At least one groove of the terminal area of the terminal structure, the both sides Jun You surfaces knot of groove, close to the side of active area for n-type injection knot, the side away from active area is p-type injection knot, has filler in groove.One aspect of the present invention while ensureing that device has high breakdown voltage, can reduce the area in terminal protection area, reduce chip manufacturing cost；On the other hand the influence of spurious charge can be reduced, improves the reliability of device.
Description
Technical field
The invention belongs to semiconductor power device preparing technical field, more particularly to a kind of mesohigh slot type power device
Terminal structure and preparation method thereof.
Background technology
Insulated gate bipolar transistor IGBT is new high power device, and it collects MOSFET grid voltages control characteristic and double
Bipolar transistor low on-resistance characteristic, improves the pressure-resistant situation about mutually being pind down with conducting resistance of device, has height
The advantages such as voltage, high current, high-frequency, power integration density are high, input impedance is big, conducting resistance is small, switching loss is low.Becoming
The numerous areas such as frequency household electrical appliances, Industry Control, electronic and hybrid vehicle, new energy, intelligent grid obtain a wide range of applications
Space.
One difficult point of high tension apparatus design is that rational Terminal Design is pressure-resistant to ensure.There are a variety of methods at present
For Terminal Design, such as field limiting ring structure FLR, field plate termination FP, FLR combination FP, knot terminal extended structure JTE etc..It is logical
Optimization is crossed, the design of terminal is pressure-resistant can be close to perfect condition value.But it is even well-designed, terminal area passivation layer and
The presence of interface charge still can greatly reduce the voltage endurance capability of device.For this problem, knot terminal extended structure JTE passes through
Increase concentration strengthens the ability that anti-positive charge influences, but this maximum pressure-resistant reducing of can causing that device can bear.Optimization
Field limiting ring structure FLR combination field plate termination FP technologies can improve anti-positive charge capability of influence, but can cause the increase of terminal area.
There is the method for surface covering resistive formation in addition, although this confrontation interface charge influence is effective, it is also relevant to add leakage current
The disconnected time.Moreover, the positive-negative polarity and magnitude of electric charge not can determine that, so the key of problem is to improve the robust of Terminal Design
Property.
Traditional field limiting ring structure is as shown in Figure 1：The cut-off protection ring of partial pressure protection zone 103 and outer ring including inner ring
107.When bias is added on colelctor electrode 101 and institute's biasing gradually increases, depletion layer is along main knot 104 to the first field limiting ring
105 Directional Extension.Before voltage increases to the avalanche breakdown voltage of main knot 104, the depletion region of main knot with first
The depletion region of limit ring 105 converges, the increase of depletion region curvature, is pass-through state between main knot and ring knot, it is curved thus to weaken main knot
Accumulation electric field at song, breakdown voltage are improved.Before avalanche breakdown occurs for the first field limiting ring 105, the second field limiting ring 106
Break-through, by that analogy.Dielectric layer in the top of field limiting ring for covering terminal.Following drawback be present in field limiting ring terminal structure：
Traditional field limiting ring structure relies on impurity and diffuses to form field limiting ring one by one in thermal process by implanted dopant.
In order to prevent two adjacent field limiting rings from diffusing into one another, the spacing of field limiting ring and field limiting ring must keep remote enough, and this causes field
It is larger to limit the area of ring, increases cost.
Field limiting ring terminal structure is easily influenceed by Rayleigh Taylor and oxide interface electric charge, and then influences device
Reliability under breakdown voltage and high pressure.In addition, the precision controlling of heavy doping is also a problem.
Prior art provides a kind of groove-shaped terminal structure, as shown in Fig. 2 real by way of in terminal area cutting
It is existing.In the semiconductor surface apart from main knot 0.5-100um, longitudinal depth is formed by wet etching, the methods of reactive ion etching
Spend 0.1-10um groove 14；Flute surfaces pass through the methods of chemical vapor deposition, deposit one layer of conductive layer 16, conductive layer 16 with
Electrode 17 is isolation, and the conductive layer can be the doping type semi-conducting material opposite with substrate, or Al or its
The metal of its type.This terminal structure, it may be such that the void that depletion layer stretches out when device bears pressure-resistant, is specifically shown in figure
Line.Compared to traditional field limiting ring structure, groove-shaped terminal structure greatly reduces area；Injected additionally, due to impurity is reduced,
Grooved size easily accurately controls, so improving precision controlling；Required thermal process is less, avoids doping concentration point after thermal process
The change of cloth, but the influence to surface charge is not solved or weakened, the device robustness of the terminal structure compares
It is weak.
The content of the invention
The technical problems to be solved by the invention be to provide a kind of mesohigh slot type power device terminal structure and its
Preparation method, solves the weaker technical problem of the device robustness of the terminal structure of power device of the prior art.
In order to solve the above technical problems, the invention provides a kind of terminal structure of mesohigh slot type power device,
At least one groove of the terminal area of power device, the both sides Jun You surfaces knot of the groove, the side close to active area is n
Type injection knot, the side away from active area are p-type injection knot, have filler in the groove.
Further, the concentration of the surface knot is all higher than the drift region concentration of the power device.
Further, the junction depth of the surface knot is less than the groove depth of the groove.
Further, the junction depth of the surface knot is 0.4-4um.
Further, the depth bounds of the groove is 2-15um, and the width range of the groove is 0.5-5um.
Further, the filler is passivation or conductive materials.
Further, the passivation is any one in silica, silicon nitride or silicon oxynitride.
Further, the conductive materials are polysilicon.
A kind of preparation method of the terminal structure of mesohigh slot type power device, comprises the following steps：
By mask plate, at least one ditch is formed by wet etching or reactive ion etching in the termination environment of n-type substrate
Groove, by mask plate, by the method for ion implanting or the method for diffusion in the trench close to the side shape of active area
Inject and tie into n-type, opposite side forms p-type injection knot in the trench；It is in the groove and described by the method for deposit
The upper surface covering passivation of n-type substrate.
Further, the preparation method can also be：The preparation method also includes：It is described covering passivation it
Before, first the upper surface with the n-type substrate in the groove deposits one layer of conductive materials, then passes through plasma etching
Method, the conductive materials are etched away, it is upper with the n-type substrate in the groove finally again by the method for deposit
Surface covers passivation.
Terminal structure of a kind of mesohigh slot type power device provided by the invention and preparation method thereof, on the one hand can be with
While ensureing that device has high breakdown voltage, the area in terminal protection area is reduced, reduces chip manufacturing cost；Separately
On the one hand the influence of spurious charge can be reduced, improves the reliability of device.
Brief description of the drawings
Fig. 1 is a kind of field limiting ring structure schematic diagram that prior art provides；
Fig. 2 is a kind of groove-shaped terminal structure schematic diagram that prior art provides；
Fig. 3 is IGBT grooves terminal structure schematic diagram provided in an embodiment of the present invention.
Reference：
101st, colelctor electrode, 102, N- bases, 103, partial pressure protection zone, 104, main knot, the 105, first field limiting ring, 106, second
Field limiting ring, 107, cut-off protection ring, 7, passivation layer, 14, groove, 16, conductive layer, 17, electrode, 15, p-type injection knot, 18, n-type
Injection knot.
Embodiment
Embodiment 1：
Referring to Fig. 3, the embodiments of the invention provide a kind of terminal structure of mesohigh slot type power device, in the present invention
In embodiment, the power device is IGBT structure, and colelctor electrode 101 is in the bottom of n-type substrate, and N- bases 102 are in colelctor electrode 101
On, at least one groove 14 of IGBT terminal area, the both sides Jun You surfaces of groove 14 are tied, close in both side surface knot to have
The side of source region is that n-type injects knot 18, and knot 15 is injected in the side away from active area for p-type in both side surface knot, has in groove 14
Filler, when negative electrical charge be present in passivation layer 7, hole inversion layer can be formed on surface, increase n-type injection knot 18 can prevent
The formation of hole inversion layer.When positive charge in passivation layer be present, surface field can be caused to gather, increase p-type injection knot 15 can
For weakening peak value electric field.The terminal structure is extended to the peak value electric field of terminal part from the surface of semiconductor using groove
The inside of semiconductor, weaken influence of the surface treatment to device.
Wherein, the concentration of surface knot is all higher than IGBT drift region concentration, in embodiments of the present invention, the junction depth of surface knot
For 0.4-4um, the depth bounds of groove is 2-15um, and the width range of groove is 0.5-5um, and still, the junction depth of surface knot should
When the groove depth less than groove.
Wherein, filler is passivation or conductive materials, and passivation can reduce the leakage current in device terminal region.This
Passivation in embodiment can be any one in silica, silicon nitride or silicon oxynitride；Conductive materials are polysilicon,
Electric Field Distribution can be made more uniform.
Embodiment 2：
The embodiments of the invention provide a kind of preparation method of mesohigh slot type power device, comprise the following steps：
Step 201：Select n-type substrate；
Step 202：Regional choice is carried out by the mask plate of routine, needs the region of cutting in the termination environment of n-type substrate
More than one groove is formed by wet etching, the depth of groove is 2um, and the width of groove is 0.5um；
Step 203：Regional choice is carried out by the mask plate of routine, then it is remote in groove by the method for ion implanting
The side of IGBT active area forms p-type injection knot, and the junction depth of p-type injection knot is 0.4um；
Step 204：Regional choice is carried out by the mask plate of routine, by the method for ion implanting in groove close to IGBT
Active area side formed n-type injection knot, n-type injection knot junction depth be 0.4um；
Step 205：In groove and n-type substrate upper surface deposits one layer of conductive materials using the method for evaporation, wherein, should
Conductive materials are polysilicon；
Step 26：The method of using plasma etching, the covering of n-type substrate upper surface is etched away；
Step 207：In embodiments of the present invention, the specific method of deposit is the method for evaporation, passes through the evaporation side of routine
Upper surface covering passivation of the method in groove with n-type substrate;Wherein, the passivation is silica.
Embodiment 3：
Step 301：Select n-type substrate；
Step 302：Regional choice is carried out by the mask plate of routine, needs the region of cutting in the termination environment of n-type substrate
More than one groove, the depth 15um of groove, the width 5um of groove are formed by reactive ion etching；
Step 303：Regional choice is carried out by the mask plate of routine, then by the method for diffusion in groove close to IGBT's
The side of active area forms n-type injection knot, wherein, the junction depth of n-type injection knot is 4um；
Step 304：By routine mask plate carry out regional choice, by the method for diffusion in groove having away from IGBT
The side of source region forms p-type injection knot, wherein, the junction depth of p-type injection knot is 4um；
Step 305：In groove and n-type substrate upper surface deposits one layer of conductive materials by conventional sputter method, wherein,
The conductive materials are polysilicon；
Step 306：The method of using plasma etching, the covering of n-type substrate upper surface is etched away；
Step 307：In embodiments of the present invention, the specific method of deposit is the method for sputtering, is existed by the method for sputtering
Upper surface in groove with n-type substrate covers passivation, wherein, the passivation is silicon nitride and silicon oxynitride.
Embodiment 4：
Step 401：Select n-type substrate；
Step 402：Regional choice is carried out by the mask plate of routine, needs the region of cutting to lead in the termination environment of n-type lining
Cross wet etching and form more than one groove, the depth of groove is 5um, and the width of groove is 3um；
Step 403：Regional choice is carried out by the mask plate of routine, by the method for ion implanting in having close to IGBT
The side of source region forms n-type injection knot, wherein, the junction depth of n-type injection knot is 2um；
Step 404：Regional choice is carried out by the mask plate of routine, by the method for ion implanting in having away from IGBT
The side of source region forms p-type injection knot, wherein, the junction depth of p-type injection knot is 2um；
Step 405：In embodiments of the present invention, the specific method of deposit is the method for physical vapor deposition (PVD), is passed through
The method of conventional physical vapor deposition (PVD), it is with the upper surface covering passivation of n-type substrate, the passivation in groove
Silica and silicon nitride.
Embodiment 5：
Step 501：Select n-type substrate；
Step 502：Regional choice is carried out by the mask plate of routine, needs the region of cutting in the termination environment of n-type substrate
More than one groove is formed by reactive ion etching, the depth of groove is 8um, and the width of groove is 2um；
Step 503：Regional choice is carried out by the mask plate of routine, by the method for diffusion in the active area close to IGBT
Side formed n-type injection knot, wherein, n-type injection knot junction depth be 4um；
Step 504：Regional choice is carried out by the mask plate of routine, by the method for diffusion in the active area away from IGBT
Side formed p-type injection knot, wherein, p-type injection knot junction depth be 4um；
Step 505：In embodiments of the present invention, the specific method of deposit is the method for oxidation, is specially：By in high temperature
Under be passed through the gas containing oxygen element, in groove and n-type substrate upper surface covering passivation, the passivation include silica,
Silicon nitride and silicon oxynitride.
Terminal structure provided in an embodiment of the present invention is not limited to IGBT, can be also used for other power devices such as VDMOS.
The terminal structure can reduce the influence of Oxide trapped charge and interface charge to device, the robustness of device be improved, so as to improve
The reliability of device.In addition, the preparation technology of terminal structure and the processing step of slot type power device active area are combined, subtract
Lack terminal step of preparation process, reduce production cost.Compared to traditional field limiting ring structure, the present invention is tied using groove and surface
With reference to mode, compared with the injection type terminal such as traditional FLR, JTE, the depth and doping concentration of surface knot are shallower, and groove profile
Size easily accurately controls, so improving precision controlling.
It should be noted last that above embodiment is merely illustrative of the technical solution of the present invention and unrestricted,
Although the present invention is described in detail with reference to example, it will be understood by those within the art that, can be to the present invention
Technical scheme modify or equivalent substitution, without departing from the spirit and scope of technical solution of the present invention, it all should cover
Among scope of the presently claimed invention.
Claims (10)
1. a kind of terminal structure of mesohigh slot type power device, it is characterised in that in the terminal area of power device at least
There is a groove, the both sides Jun You surfaces knot of the groove, be n-type injection knot close to the side of active area, away from active area
Side is p-type injection knot, has filler in the groove.
2. terminal structure according to claim 1, it is characterised in that the concentration of the surface knot is all higher than the power device
The drift region concentration of part.
3. terminal structure according to claim 1, it is characterised in that the junction depth of the surface knot is less than the groove of the groove
It is deep.
4. terminal structure according to claim 3, it is characterised in that the junction depth of the surface knot is 0.4-4um.
5. terminal structure according to claim 3, it is characterised in that the depth bounds of the groove is 2-15um, described
The width range of groove is 0.5-5um.
6. terminal structure according to claim 1, it is characterised in that the filler is passivation or conductive materials.
7. terminal structure according to claim 6, it is characterised in that the passivation is silica, silicon nitride or nitrogen
Any one in silica.
8. terminal structure according to claim 6, it is characterised in that the conductive materials are polysilicon.
9. a kind of preparation method of the terminal structure of mesohigh slot type power device, it is characterised in that comprise the following steps：
By mask plate, at least one groove is formed by wet etching or reactive ion etching in the termination environment of n-type substrate, led to
Mask plate is crossed, n-type is formed close to the side of active area by the method for ion implanting or the method for diffusion in the trench
Injection knot, in the trench opposite side formation p-type injection are tied；By the method for deposit, served as a contrast in the groove with the n-type
The upper surface covering passivation at bottom.
10. according to the method for claim 9, it is characterised in that the preparation method also includes：In the covering passivation
Before, the upper surface first with the n-type substrate in the groove deposits one layer of conductive materials, then passes through plasma etching
Method, the conductive materials of the n-type substrate upper surface are etched away, finally again by the method for deposit, in the groove
Passivation is covered with the upper surface of the n-type substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310086262.XA CN103839978B (en) | 2012-11-23 | 2013-03-18 | A kind of terminal structure of mesohigh slot type power device and preparation method thereof |
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| CN201210484761X | 2012-11-23 | ||
| CN201210484761 | 2012-11-23 | ||
| CN201210484761.X | 2012-11-23 | ||
| CN201310086262.XA CN103839978B (en) | 2012-11-23 | 2013-03-18 | A kind of terminal structure of mesohigh slot type power device and preparation method thereof |
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| CN103839978B true CN103839978B (en) | 2018-04-03 |
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| CN106611798A (en) * | 2015-10-26 | 2017-05-03 | 南京励盛半导体科技有限公司 | N type silicon carbide semiconductor Schottky diode structure |
| CN107369620B (en) * | 2016-05-12 | 2020-10-13 | 北大方正集团有限公司 | Junction terminal extension structure preparation method, junction terminal extension structure and VDMOS power device |
| CN106331541B (en) * | 2016-09-18 | 2019-06-21 | 首都师范大学 | Collect the imaging sensor of parasitism photogenerated charge |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291518A (en) * | 1992-04-09 | 1993-11-05 | Toshiba Corp | Semiconductor device and its manufacture |
| US5949124A (en) * | 1995-10-31 | 1999-09-07 | Motorola, Inc. | Edge termination structure |
| CN101764159A (en) * | 2008-12-23 | 2010-06-30 | 万国半导体有限公司 | Metallic oxide semiconductor field effect tube with reduced breakdown voltage |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0122122D0 (en) * | 2001-09-13 | 2001-10-31 | Koninkl Philips Electronics Nv | Trench-gate semiconductor devices and their manufacture |
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2013
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291518A (en) * | 1992-04-09 | 1993-11-05 | Toshiba Corp | Semiconductor device and its manufacture |
| US5949124A (en) * | 1995-10-31 | 1999-09-07 | Motorola, Inc. | Edge termination structure |
| CN101764159A (en) * | 2008-12-23 | 2010-06-30 | 万国半导体有限公司 | Metallic oxide semiconductor field effect tube with reduced breakdown voltage |
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