WO2015062411A1 - High voltage semiconductor device, high voltage semiconductor device terminal, and method of fabricating same - Google Patents

High voltage semiconductor device, high voltage semiconductor device terminal, and method of fabricating same Download PDF

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Publication number
WO2015062411A1
WO2015062411A1 PCT/CN2014/088609 CN2014088609W WO2015062411A1 WO 2015062411 A1 WO2015062411 A1 WO 2015062411A1 CN 2014088609 W CN2014088609 W CN 2014088609W WO 2015062411 A1 WO2015062411 A1 WO 2015062411A1
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Prior art keywords
semiconductor device
high voltage
voltage semiconductor
field
substrate
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PCT/CN2014/088609
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French (fr)
Chinese (zh)
Inventor
邓小社
钟圣荣
王根毅
周东飞
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无锡华润上华半导体有限公司
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Publication of WO2015062411A1 publication Critical patent/WO2015062411A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Definitions

  • the present invention relates to the field of semiconductor devices, and more particularly to a high voltage semiconductor device, a high voltage semiconductor device terminal, and a method of fabricating the same.
  • the curvature effect of the planar junction increases the electric field at the curved portion and surface of the junction, limiting the breakdown voltage of the device.
  • various high-voltage semiconductor device terminal technologies have been developed, such as beveled surfaces (Bevel Surface technology, field limiting rings (FLR), field plate (FP) technology, lateral doping (Variation) Of Lateral Doping, VLD) technology, semi insulating polycrystalline Silicon,SIPOS technology, Reduced Surface Field (RESURF) technology and junction termination (Junction Termination, JTE) technology, etc.
  • the above high-voltage semiconductor device terminal technology has the advantages of being compatible with the planar process, and the cost is greatly reduced, but it also faces three identical problems.
  • the design must consider the influence of various factors such as junction depth, substrate concentration, ring width, ring pitch, surface concentration, surface charge, etc. It is difficult to obtain the target breakdown voltage by analytical method, and optimization design is needed through simulation software.
  • the breakdown voltage of the device is susceptible to the interface charge on the surface of the semiconductor and the introduction of a movable charge in the normal process. In order to stabilize the breakdown voltage, it is necessary to utilize process means (such as enhancing the quality of the oxide layer, performing hydrogen treatment on the silicon surface, etc.) ) Try to eliminate the effects of unnecessary charges.
  • the leakage current is too large or even increases continuously, and the breakdown voltage is reduced or even short-circuited after returning to normal temperature.
  • the higher the breakdown voltage of the device the lower the doping concentration of the substrate required. The more obvious the phenomenon.
  • the above first type of problem can generally be solved well by optimizing the terminal design.
  • the second and third types of problems have a great relationship with device design, process fabrication and packaging, and are one of the main difficulties in the development of high voltage semiconductor devices. It is generally believed that the latter two types of problems are mainly caused by the movable charges introduced inside and outside the device. In actual work, the movable charge moves under external stress conditions, which will change the original stable surface electric field, so that the withstand voltage changes, and even the leakage current increases.
  • the high voltage semiconductor device terminal 100 of FIG. 1 includes a substrate 110, a field limiting ring 120 on the substrate 110, a field oxide layer 150 on the substrate 110 and the field limiting ring 120, and a field limiting ring. 120 and field plate 140 on field oxide layer 150 and first passivation layer 160 on field plate 140. It can be seen from Fig. 1 that under high temperature and high stress conditions (such as the circuit connection mode shown in Fig. 1), the positive ions get a certain energy and then break away from the binding of the surrounding potential field, becoming a free charge, which is high by the high voltage semiconductor device terminal 100.
  • high temperature and high stress conditions such as the circuit connection mode shown in Fig. 1
  • the high voltage semiconductor device terminal 100 has poor withstand voltage reliability.
  • the technical methods for solving this problem mainly come from two aspects: on the one hand, the factors that introduce the movable charge in the chip manufacturing process and the packaging process are minimized.
  • special surface passivation technology or high-reliability synthetic resin is used to reduce the introduction of external charges and moisture. This has a significant effect on reducing leakage current of the device at high temperatures.
  • this method requires high packaging technology and high process cost.
  • a special design structure is adopted to enhance the shielding effect of the chip itself on the movable charge, thereby improving the leakage performance of the device under high temperature and high stress conditions.
  • a semi-insulating polysilicon structure which uses a semi-insulating film resistor to connect the main junction at one end and a cut-off ring at one end.
  • a semi-insulating film resistor to connect the main junction at one end and a cut-off ring at one end.
  • the semi-insulating film is generally formed by doping oxygen or nitrogen to polysilicon, and the resistivity is required to be between 10 7 and 10 10 ohm meters. Therefore, the use of semi-insulating polysilicon structure, the process is complex, the film resistance quality must be precisely controlled according to the design.
  • the structure uses a semi-insulating resistor to directly bridge between the high voltage and the ground. Under normal operating conditions, non-negligible power consumption will occur. At the same time, the thin film resistor has a high temperature coefficient and a certain stability problem. Therefore, although the above two methods can improve the leakage current of the high-voltage semiconductor device terminal at a high temperature and the low reliability of the voltage at the high temperature, the manufacturing process is complicated.
  • a high voltage semiconductor device terminal comprising a substrate having a first surface, the high voltage semiconductor device terminal further comprising a field limiting ring on the first surface, a surface enhancement also located on the first surface and on both sides of the field limiting ring a field oxide layer on the first surface and covering the surface enhancement region, a field plate on the first surface partially covering the field limiting ring and the field oxide layer, and a passivation layer covering the field plate and the field oxide layer, the surface enhancement region and The conductivity type of the substrate is the same, and the doping concentration of the surface enhancement region is greater than the doping concentration of the substrate.
  • the passivation layer includes a first passivation layer and a second passivation layer overlying the first passivation layer.
  • the material of the second passivation layer is polyimide.
  • the substrate is an N-type substrate
  • the impurity doped in the surface enhancement region is an N-type impurity
  • the sheet resistance of the surface enhancement region is 400 ⁇ / ⁇ to 6000 ⁇ / ⁇ .
  • the width of the surface enhancement zone is greater than the distance between adjacent two field limiting rings.
  • a high voltage semiconductor device comprising the high voltage semiconductor device terminal of any of the above embodiments.
  • the high voltage semiconductor device is a double diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.
  • a high voltage semiconductor device terminal manufacturing method comprising the steps of: providing a substrate having a first surface; forming a field oxide layer, a field limiting ring and a surface enhancement region on a first surface of the substrate, wherein the surface enhancement region is located On both sides of the ring, the surface enhancement region and the substrate have the same conductivity type, and the doping concentration of the surface enhancement region is greater than the doping concentration of the substrate; the field plate is formed on the first surface, and the field plate partially covers the field ring and the field An oxide layer; forming a passivation layer that covers the field plate and the field oxide layer.
  • the substrate is an N-type substrate
  • the impurity doped in the surface enhancement region is an N-type impurity
  • the implantation dose of the N-type impurity is 2e11 to 1e13 cm -2
  • the implantation energy is 60 keV to 120 keV.
  • the passivation layer includes a first passivation layer and a second passivation layer overlying the first passivation layer.
  • the high-voltage semiconductor device terminal increases the surface concentration of the field limiting ring to reduce the influence of the movable charge on the surface electric field of the high-voltage semiconductor device terminal, stabilizes the surface electric field of the high-voltage semiconductor device terminal, and thereby reduces the leakage current at high temperature of the high-voltage semiconductor device terminal. Enhance its pressure reliability.
  • the high-voltage semiconductor device terminal only increases the step of enhancing the surface concentration of the field limiting ring at the time of manufacture, and the manufacturing process is relatively simple.
  • FIG. 1 is a schematic view showing a correspondence between a terminal structure and a surface electric field of a commonly used high voltage semiconductor device
  • FIG. 2 is a schematic structural view of a terminal of a high voltage semiconductor device of Embodiment 1;
  • FIG. 3 is a schematic structural view showing a case where a high-voltage semiconductor device terminal of Embodiment 1 is applied to a double-diffused metal oxide semiconductor field effect transistor;
  • FIG. 4 is a schematic structural view showing a case where an insulated gate bipolar transistor is applied to a terminal of a high voltage semiconductor device in Embodiment 1;
  • FIG. 5 is a flow chart showing a method of manufacturing the piezoelectric semiconductor device terminal shown in FIG. 2;
  • 6 to 13 are schematic diagrams showing the structure of a corresponding piezoelectric semiconductor device terminal in the flow of the method for manufacturing a piezoelectric semiconductor device terminal shown in FIG. 5.
  • an embodiment of the present invention provides a high voltage semiconductor device terminal 200.
  • the high voltage semiconductor device terminal 200 includes a substrate 210 having a first surface 211 and a second surface 212 opposite the first surface 211, the high voltage semiconductor device terminal further including a first surface 211 of the substrate 210
  • the field limiting ring 220, the surface enhancement region 230 also located on the first surface 211 and on both sides of the field limiting ring 220, the field oxide layer 250 on the first surface and covering the surface enhancement region 230, on the first surface and partially covering the field limit Field plate 240 of ring 220 and field oxide layer 250, a passivation layer overlying field plate 240 and field oxide layer 250, and a back metal layer 280 on second surface 212 of substrate 210.
  • the surface enhancement region 230 is of the same conductivity type as the substrate 210, and the doping concentration of the surface enhancement region 230 is greater than the doping concentration of the substrate 210.
  • the field oxide layer 250 of the high voltage semiconductor device terminal 200 is further provided with a dielectric layer 251 disposed between the field oxide layer 250 and the passivation layer.
  • the passivation layer includes a first passivation layer 260 and a second passivation layer 270 overlying the first passivation layer 260.
  • the material of the first passivation layer 260 is silicon nitride
  • the material of the second passivation layer 270 is polyimide.
  • the second passivation layer 270 has a thickness of 4 micrometers to 18 micrometers.
  • the substrate 210 of the high voltage semiconductor device terminal 200 is an N-type substrate, the field limiting ring 220 is P-type doped, and the impurity doped by the surface enhancement region 230 is an N-type impurity.
  • the implantation dose of the N-type impurity in the surface enhancement region 230 is 2e11 to 1e13 cm -2 , and the implantation energy is 60 keV to 120 keV.
  • the sheet resistance of the surface enhancement region 230 is 400 ⁇ / ⁇ to 6000 ⁇ / ⁇ .
  • the width of the surface enhancement zone 230 is greater than the distance between adjacent two field limiting rings 220, that is, the surface enhancement zone 230 is coupled to two adjacent field limiting rings 220.
  • the sheet resistance of the field limit ring 220 is 10 ⁇ / ⁇ to 1200 ⁇ / ⁇ .
  • the high voltage semiconductor device terminal 200 in this embodiment increases the surface enhancement region 230 in the region between the field limiting rings 220 such that the surface concentration of the region between the field limiting rings 220 is increased, here the field limiting ring is enhanced by the ion implantation process.
  • the movable charge Under high temperature and high pressure conditions, the movable charge has a high potential to a low potential in the passivation layer, and is concentrated at the field plate 240 in the region between the field limiting rings 220.
  • the high voltage semiconductor device terminal 200 By increasing the surface concentration of the region between the field limiting rings 220, the equivalent charge of the device surface is increased, thereby correspondingly reducing the influence of the movable charge on the surface electric field of the high voltage semiconductor device terminal 200, and improving the withstand voltage of the high voltage semiconductor device terminal 200, thereby reducing the device.
  • Leakage current at high temperature enhances its withstand voltage reliability. Therefore, the high voltage semiconductor device terminal 200 has an advantage that the leakage current at a high temperature is small and the withstand voltage reliability is high.
  • the high voltage semiconductor device terminal 200 only needs to increase the surface concentration of the field limiting ring at the time of manufacture, and the manufacturing process is relatively simple.
  • the present invention also provides a high voltage semiconductor device.
  • the high voltage semiconductor device can be a double diffused metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, or other high voltage semiconductor device.
  • This high voltage semiconductor device has the high voltage semiconductor device terminal 200 as shown in FIG. 2 in Embodiment 1.
  • the double-diffused metal oxide semiconductor field effect transistor of FIG. 3 has a structure of a double-diffused metal oxide semiconductor field effect transistor and a high-voltage semiconductor device terminal 200 structure.
  • the insulated gate bipolar transistor of FIG. 4 has a structure of an insulated gate bipolar transistor and a high voltage semiconductor device terminal 200 structure.
  • the structure of the double-diffused metal oxide semiconductor field effect transistor and the insulated gate bipolar transistor here is similar to that of the conventional double-diffused metal oxide semiconductor field effect transistor and the insulated gate bipolar transistor, except that they have the embodiment.
  • the present invention also provides a method of fabricating a high voltage semiconductor device terminal 200.
  • the high voltage semiconductor device terminal 200 is the high voltage semiconductor device terminal 200 shown in FIG. 2 in Embodiment 1.
  • the high voltage semiconductor device terminal 200 manufacturing method includes the following steps.
  • Step S110 providing a substrate 210 having a first surface 211 and a second surface 212 opposite the first surface 211.
  • the substrate 210 is an N-type substrate 210.
  • a field oxide layer 250, a field limiting ring 220 and a surface enhancement region 230 are formed on the first surface 211 of the substrate 210.
  • the surface enhancement region 230 is located on both sides of the field limiting ring 220, and the surface enhancement region 230 is electrically conductive with the substrate 210.
  • the types are the same, and the doping concentration of the surface enhancement region 230 is greater than the doping concentration of the substrate 210.
  • a field oxide layer 250 having a thickness of 1000 angstroms to 3,000 angstroms is grown on the first surface 211 of the substrate 210. Then, after the steps of coating, exposure, hard baking, etching, etc., ion implantation is performed. At this time, the ion implantation dose is 2e11 ⁇ 1e13 cm -2 , the ion implantation energy is 60 keV ⁇ 120 keV, and the ions during ion implantation are N-type impurities.
  • a step of removing glue, cleaning, etc. is performed, and then an aerobic environment of 1100 ° C to 1200 ° C is used to form a surface enhancement region 230, and a field oxide layer 250 of 6000 ⁇ to 20,000 ⁇ is grown.
  • the field oxide layer 250 is thickened and covers the surface enhancement region 230.
  • a step of coating, exposing, wet etching, degumming, etc. is performed on the field oxide layer 250, followed by ion implantation.
  • the ion implantation dose is 1e13 to 1e15 cm -2 and the energy is 60 keV to 120 keV, and the ions during ion implantation are P-type impurities.
  • steps such as de-cleaning are performed, and the well is formed in a nitrogen atmosphere at 1100 ° C to 1200 ° C to form a field limiting ring 220.
  • boro-phospho-silicate-glass (BPSG) of 8000 ⁇ to 16,000 ⁇ is deposited on the field oxide layer 250, and reflowed at 850 ° C to 950 ° C to form a dielectric layer 251.
  • a field plate 240 is formed, which partially covers the field limiting ring 220 and the field oxide layer 250.
  • a step of coating, exposing, etching, stripping, etc. is performed, and then a front metal is deposited to form a field plate 240 on the field limiting ring 220 and the field oxide layer 250.
  • a passivation layer is formed, which covers the field plate 240 and the field oxide layer 250.
  • a step of coating, exposing, wet etching, degumming, etc. is performed, and then the first passivation layer 260 is deposited.
  • the material of the first passivation layer 260 here is silicon nitride.
  • a second passivation layer 270 is deposited.
  • the material of the second passivation layer 270 is polyimide.
  • the high voltage semiconductor device terminal 200 manufacturing method further includes a step S150 of forming a back metal layer 280. As shown in FIG. 2, a back metal layer 280 is deposited on the second surface 212 of the substrate 210.
  • the fabrication of the high voltage semiconductor device terminal 200 is completed through the above process steps.
  • the manufacturing method of the high voltage semiconductor device terminal 200 employs a process technology that is completely compatible with a planar process, and the manufacturing process is simple.
  • the surface concentration of the field limiting ring 220 is enhanced by ion implantation to reduce the influence of the movable charge on the surface electric field of the high voltage semiconductor device terminal 200, and the surface electric field of the high voltage semiconductor device terminal 200 is stabilized, thereby reducing the leakage current at high temperature of the high voltage semiconductor device terminal 200. To enhance its pressure reliability.

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Abstract

A high voltage semiconductor device terminal comprises a substrate, the substrate having a first surface, and the high voltage semiconductor device terminal further comprises a field limiting ring located on the first surface, a surface enhanced region that is also located on the first surface and located on two sides of the field limiting ring, a field oxide layer located on the first surface and covering the surface enhanced region, a field plate located on the first surface and partially covering the field limiting ring and the field oxide layer, and a passivation layer covering the field plate and the field oxide layer, the surface enhanced region and the substrate having a same conductivity type, and a doping concentration of the surface enhanced region being greater than that of the substrate.

Description

高压半导体器件、高压半导体器件终端及其制造方法High voltage semiconductor device, high voltage semiconductor device terminal and method of manufacturing same
【技术领域】[Technical Field]
本发明涉及半导体器件领域，特别是涉及一种高压半导体器件、高压半导体器件终端及其制造方法。 The present invention relates to the field of semiconductor devices, and more particularly to a high voltage semiconductor device, a high voltage semiconductor device terminal, and a method of fabricating the same.
【背景技术】【Background technique】
在高压半导体器件中，平面结的曲率效应使得结弯曲部分和表面处电场增大，限制了器件的击穿电压。迄今为止，为了实现高压半导体器件的阻断能力，已经开发了多种高压半导体器件终端技术，如斜表面(Bevel Surface)技术、场限环技术（field limiting rings，FLR）、场板（field plate，FP）技术、横向变掺杂（Variation of Lateral Doping，VLD）技术、半绝缘多晶硅（semi insulating polycrystalline silicon，SIPOS）技术、弱化表面电场（Reduced Surface Field，RESURF）技术以及结终端扩展（Junction Termination，JTE）技术等。In high voltage semiconductor devices, the curvature effect of the planar junction increases the electric field at the curved portion and surface of the junction, limiting the breakdown voltage of the device. To date, in order to achieve the blocking capability of high-voltage semiconductor devices, various high-voltage semiconductor device terminal technologies have been developed, such as beveled surfaces (Bevel Surface technology, field limiting rings (FLR), field plate (FP) technology, lateral doping (Variation) Of Lateral Doping, VLD) technology, semi insulating polycrystalline Silicon,SIPOS technology, Reduced Surface Field (RESURF) technology and junction termination (Junction Termination, JTE) technology, etc.
上述高压半导体器件终端技术具有与平面工艺相互兼容的优点，成本大大降低，但是也面临三个相同的问题。第一，设计必须考虑结深、衬底浓度、环宽、环间距、表面浓度、表面电荷等众多种因素的影响，难以通过解析方法得到目标击穿电压，需通过仿真软件进行优化设计。第二，器件的击穿电压易受半导体表面界面电荷以及正常工艺过程中引入可动电荷的影响，为了稳定击穿电压，需利用工艺手段（如增强氧化层质量、对硅表面进行氢气处理等）尽量消除不必要的电荷的影响。第三，器件在高温条件下，漏电流偏大甚至出现持续增大不能稳定，恢复常温后击穿电压降低甚至出现短路的现象，器件击穿电压越高，所需衬底掺杂浓度越低，该现象越明显。The above high-voltage semiconductor device terminal technology has the advantages of being compatible with the planar process, and the cost is greatly reduced, but it also faces three identical problems. First, the design must consider the influence of various factors such as junction depth, substrate concentration, ring width, ring pitch, surface concentration, surface charge, etc. It is difficult to obtain the target breakdown voltage by analytical method, and optimization design is needed through simulation software. Second, the breakdown voltage of the device is susceptible to the interface charge on the surface of the semiconductor and the introduction of a movable charge in the normal process. In order to stabilize the breakdown voltage, it is necessary to utilize process means (such as enhancing the quality of the oxide layer, performing hydrogen treatment on the silicon surface, etc.) ) Try to eliminate the effects of unnecessary charges. Third, under high temperature conditions, the leakage current is too large or even increases continuously, and the breakdown voltage is reduced or even short-circuited after returning to normal temperature. The higher the breakdown voltage of the device, the lower the doping concentration of the substrate required. The more obvious the phenomenon.
上述第一类问题一般可以通过优化终端设计得以良好地解决。但是，第二、第三类问题与器件设计、工艺制备以及封装都有较大关系，是高压半导体器件开发的主要难点之一。一般认为，后两类问题主要是由器件内部和外部引入的可动电荷引起的。实际工作中，可动电荷在外部应力条件下移动，将会改变原来稳定的表面电场，从而使的耐压发生改变，甚至出现漏电流增大的问题。The above first type of problem can generally be solved well by optimizing the terminal design. However, the second and third types of problems have a great relationship with device design, process fabrication and packaging, and are one of the main difficulties in the development of high voltage semiconductor devices. It is generally believed that the latter two types of problems are mainly caused by the movable charges introduced inside and outside the device. In actual work, the movable charge moves under external stress conditions, which will change the original stable surface electric field, so that the withstand voltage changes, and even the leakage current increases.
请参考图1，图1中的高压半导体器件终端100包括衬底110、位于衬底110上的场限环120、位于衬底110和场限环120上的场氧化层150、位于场限环120和场氧化层150上的场板140及位于场板140上的第一钝化层160。从图1可以看到，在高温高压应力条件下（如图1所示的电路连接方式），正离子获得一定能量后挣脱周围势场的束缚，成为自由电荷，由高压半导体器件终端100的高电位端向低电位端移动，在场限环120之间的区域聚集，使得此处表面电场增大，漏电流增大甚至不能稳定，进一步导致击穿电压降低甚至短路。所以该高压半导体器件终端100的耐压可靠性差。Referring to FIG. 1, the high voltage semiconductor device terminal 100 of FIG. 1 includes a substrate 110, a field limiting ring 120 on the substrate 110, a field oxide layer 150 on the substrate 110 and the field limiting ring 120, and a field limiting ring. 120 and field plate 140 on field oxide layer 150 and first passivation layer 160 on field plate 140. It can be seen from Fig. 1 that under high temperature and high stress conditions (such as the circuit connection mode shown in Fig. 1), the positive ions get a certain energy and then break away from the binding of the surrounding potential field, becoming a free charge, which is high by the high voltage semiconductor device terminal 100. The potential end moves toward the low potential end, and the region between the field limiting rings 120 gathers, so that the surface electric field increases here, the leakage current increases or even becomes unstable, and further causes the breakdown voltage to decrease or even short circuit. Therefore, the high voltage semiconductor device terminal 100 has poor withstand voltage reliability.
目前，解决该问题的技术方法主要从两个方面出发：一方面，尽量减少芯片制造过程和封装过程引入可动电荷的因素。比如采用特殊的表面钝化技术或采用高可靠性合成树脂进行封装，以降低外部电荷及水汽等沾污的引入。这对降低高温下器件漏电流具有显著的效果。但是该方法对封装技术要求很高且工艺成本较高。另一方面，采用特殊设计结构以加强芯片本身对可动电荷的屏蔽作用，从而改善器件在高温高压应力条件下的漏电表现。比如，采用半绝缘多晶硅结构，它是利用半绝缘薄膜电阻一端连接主结，一端连接截止环。在高压反偏条件下，半绝缘电阻两端将会产生电场，该电场能够屏蔽可动电荷对终端表面电场的影响，从而改善器件在高温高压条件下测试后的击穿表现。半绝缘薄膜一般是通过对多晶硅进行掺氧或氮形成的，电阻率要求在107~1010欧姆米之间。因此，采用半绝缘多晶硅结构，工艺过程复杂，薄膜电阻质量必须根据设计精确控制。该结构采用半绝缘电阻直接跨接在高压和地之间，正常工作条件下将会产生不可忽略的功耗；同时，薄膜电阻具有较高的温度系数，也存在一定的稳定性问题。所以，上述两种方法虽然能够在移动程度上改善高压半导体器件终端高温下漏电流大，耐压可靠性低的缺点，但是制造工艺复杂。At present, the technical methods for solving this problem mainly come from two aspects: on the one hand, the factors that introduce the movable charge in the chip manufacturing process and the packaging process are minimized. For example, special surface passivation technology or high-reliability synthetic resin is used to reduce the introduction of external charges and moisture. This has a significant effect on reducing leakage current of the device at high temperatures. However, this method requires high packaging technology and high process cost. On the other hand, a special design structure is adopted to enhance the shielding effect of the chip itself on the movable charge, thereby improving the leakage performance of the device under high temperature and high stress conditions. For example, a semi-insulating polysilicon structure is used, which uses a semi-insulating film resistor to connect the main junction at one end and a cut-off ring at one end. Under the condition of high voltage reverse bias, an electric field will be generated at both ends of the semi-insulating resistor, which can shield the influence of the movable charge on the electric field on the terminal surface, thereby improving the breakdown performance of the device after testing under high temperature and high pressure conditions. The semi-insulating film is generally formed by doping oxygen or nitrogen to polysilicon, and the resistivity is required to be between 10 7 and 10 10 ohm meters. Therefore, the use of semi-insulating polysilicon structure, the process is complex, the film resistance quality must be precisely controlled according to the design. The structure uses a semi-insulating resistor to directly bridge between the high voltage and the ground. Under normal operating conditions, non-negligible power consumption will occur. At the same time, the thin film resistor has a high temperature coefficient and a certain stability problem. Therefore, although the above two methods can improve the leakage current of the high-voltage semiconductor device terminal at a high temperature and the low reliability of the voltage at the high temperature, the manufacturing process is complicated.
【发明内容】 [Summary of the Invention]
基于此，有必要提供一种高压半导体器件终端，其具有高温下漏电流小，耐压可靠性高的优点，且制造工艺简单。Based on this, it is necessary to provide a high-voltage semiconductor device terminal which has the advantages of low leakage current at high temperature and high withstand voltage reliability, and the manufacturing process is simple.
一种高压半导体器件终端，包括衬底，该衬底具有第一表面，该高压半导体器件终端还包括位于第一表面的场限环、同样位于第一表面且位于场限环两侧的表面增强区、位于第一表面且覆盖表面增强区的场氧化层、位于第一表面且部分覆盖场限环和场氧化层的场板及覆盖场板和场氧化层的钝化层，表面增强区与衬底的导电类型相同，且表面增强区的掺杂浓度大于衬底的掺杂浓度。A high voltage semiconductor device terminal comprising a substrate having a first surface, the high voltage semiconductor device terminal further comprising a field limiting ring on the first surface, a surface enhancement also located on the first surface and on both sides of the field limiting ring a field oxide layer on the first surface and covering the surface enhancement region, a field plate on the first surface partially covering the field limiting ring and the field oxide layer, and a passivation layer covering the field plate and the field oxide layer, the surface enhancement region and The conductivity type of the substrate is the same, and the doping concentration of the surface enhancement region is greater than the doping concentration of the substrate.
在其中一个实施例中，钝化层包括第一钝化层和覆盖第一钝化层的第二钝化层。In one of the embodiments, the passivation layer includes a first passivation layer and a second passivation layer overlying the first passivation layer.
在其中一个实施例中，第二钝化层的材质为聚酰亚胺。In one embodiment, the material of the second passivation layer is polyimide.
在其中一个实施例中，衬底为N型衬底，表面增强区所掺杂的杂质为N型杂质，表面增强区的方块电阻为400Ω/□~6000Ω/□。In one embodiment, the substrate is an N-type substrate, the impurity doped in the surface enhancement region is an N-type impurity, and the sheet resistance of the surface enhancement region is 400 Ω/□ to 6000 Ω/□.
在其中一个实施例中，表面增强区的宽度大于相邻两个场限环之间的距离。In one of the embodiments, the width of the surface enhancement zone is greater than the distance between adjacent two field limiting rings.
一种高压半导体器件，包括上述任一实施例中的高压半导体器件终端。A high voltage semiconductor device comprising the high voltage semiconductor device terminal of any of the above embodiments.
在其中一个实施例中，高压半导体器件为双扩散金属氧化物半导体场效应管或绝缘栅双极型晶体管。In one of the embodiments, the high voltage semiconductor device is a double diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.
一种高压半导体器件终端制造方法，包括以下步骤：提供衬底，该衬底具有第一表面；在衬底的第一表面形成场氧化层、场限环和表面增强区，表面增强区位于场限环两侧，表面增强区与衬底的导电类型相同，且表面增强区的掺杂浓度大于衬底的掺杂浓度；在第一表面形成场板，该场板部分覆盖场限环和场氧化层；形成钝化层，该钝化层覆盖场板和场氧化层。A high voltage semiconductor device terminal manufacturing method comprising the steps of: providing a substrate having a first surface; forming a field oxide layer, a field limiting ring and a surface enhancement region on a first surface of the substrate, wherein the surface enhancement region is located On both sides of the ring, the surface enhancement region and the substrate have the same conductivity type, and the doping concentration of the surface enhancement region is greater than the doping concentration of the substrate; the field plate is formed on the first surface, and the field plate partially covers the field ring and the field An oxide layer; forming a passivation layer that covers the field plate and the field oxide layer.
在其中一个实施例中，衬底为N型衬底，表面增强区所掺杂的杂质为N型杂质，N型杂质的注入剂量为2e11~1e13cm-2，注入能量为60keV~120keV。In one embodiment, the substrate is an N-type substrate, the impurity doped in the surface enhancement region is an N-type impurity, the implantation dose of the N-type impurity is 2e11 to 1e13 cm -2 , and the implantation energy is 60 keV to 120 keV.
在其中一个实施例中，钝化层包括第一钝化层和覆盖第一钝化层的第二钝化层。In one of the embodiments, the passivation layer includes a first passivation layer and a second passivation layer overlying the first passivation layer.
上述高压半导体器件终端通过增强场限环的表面浓度，以降低可动电荷对高压半导体器件终端表面电场的影响，稳定高压半导体器件终端的表面电场，从而降低高压半导体器件终端高温下的漏电流，增强其耐压可靠性。另外，该高压半导体器件终端在制造时只是增加了增强场限环的表面浓度的步骤，制造工艺相对简单。The high-voltage semiconductor device terminal increases the surface concentration of the field limiting ring to reduce the influence of the movable charge on the surface electric field of the high-voltage semiconductor device terminal, stabilizes the surface electric field of the high-voltage semiconductor device terminal, and thereby reduces the leakage current at high temperature of the high-voltage semiconductor device terminal. Enhance its pressure reliability. In addition, the high-voltage semiconductor device terminal only increases the step of enhancing the surface concentration of the field limiting ring at the time of manufacture, and the manufacturing process is relatively simple.
【附图说明】[Description of the Drawings]
图1为常用的高压半导体器件终端结构与表面电场对应情况示意图；1 is a schematic view showing a correspondence between a terminal structure and a surface electric field of a commonly used high voltage semiconductor device;
图2为实施例1的高压半导体器件终端结构示意图；2 is a schematic structural view of a terminal of a high voltage semiconductor device of Embodiment 1;
图3为双扩散金属氧化物半导体场效应管应用实施例1中高压半导体器件终端时的结构示意图；3 is a schematic structural view showing a case where a high-voltage semiconductor device terminal of Embodiment 1 is applied to a double-diffused metal oxide semiconductor field effect transistor;
图4为绝缘栅双极型晶体管应用实施例1中高压半导体器件终端时的结构示意图；4 is a schematic structural view showing a case where an insulated gate bipolar transistor is applied to a terminal of a high voltage semiconductor device in Embodiment 1;
图5为为图2所示的压半导体器件终端的制造方法流程图；5 is a flow chart showing a method of manufacturing the piezoelectric semiconductor device terminal shown in FIG. 2;
图6~13为图5所示的压半导体器件终端制造方法流程中对应的压半导体器件终端的结构示意图。6 to 13 are schematic diagrams showing the structure of a corresponding piezoelectric semiconductor device terminal in the flow of the method for manufacturing a piezoelectric semiconductor device terminal shown in FIG. 5.
【具体实施方式】 【detailed description】
请参考图2，本发明的一个实施方式提供一种高压半导体器件终端200。该高压半导体器件终端200包括衬底210，该衬底210具有第一表面211和与第一表面211相对的第二表面212，该高压半导体器件终端还包括位于衬底210的第一表面211的场限环220、同样位于第一表面211且位于场限环220两侧的表面增强区230、位于第一表面且覆盖表面增强区230的场氧化层250、位于第一表面且部分覆盖场限环220和场氧化层250的场板240、覆盖场板240和场氧化层250的钝化层及位于衬底210的第二表面212的背面金属层280。表面增强区230与衬底210的导电类型相同，且表面增强区230的掺杂浓度大于衬底210的掺杂浓度。Referring to FIG. 2, an embodiment of the present invention provides a high voltage semiconductor device terminal 200. The high voltage semiconductor device terminal 200 includes a substrate 210 having a first surface 211 and a second surface 212 opposite the first surface 211, the high voltage semiconductor device terminal further including a first surface 211 of the substrate 210 The field limiting ring 220, the surface enhancement region 230 also located on the first surface 211 and on both sides of the field limiting ring 220, the field oxide layer 250 on the first surface and covering the surface enhancement region 230, on the first surface and partially covering the field limit Field plate 240 of ring 220 and field oxide layer 250, a passivation layer overlying field plate 240 and field oxide layer 250, and a back metal layer 280 on second surface 212 of substrate 210. The surface enhancement region 230 is of the same conductivity type as the substrate 210, and the doping concentration of the surface enhancement region 230 is greater than the doping concentration of the substrate 210.
该高压半导体器件终端200的场氧化层250上还设有一层介质层251，该介质层251设于场氧化层250和钝化层之间。在该实施例中，钝化层包括第一钝化层260和覆盖第一钝化层260的第二钝化层270。第一钝化层260的材质为氮化硅，第二钝化层270的材质为聚酰亚胺。第二钝化层270的厚度为4微米到18微米。此处采用两层钝化层的结构除了可以阻挡外界可动离子、水汽等沾污的优点外，该结构还可以有效地屏蔽工艺制备过程中引入芯片内部的可动电荷对表面态造成影响。The field oxide layer 250 of the high voltage semiconductor device terminal 200 is further provided with a dielectric layer 251 disposed between the field oxide layer 250 and the passivation layer. In this embodiment, the passivation layer includes a first passivation layer 260 and a second passivation layer 270 overlying the first passivation layer 260. The material of the first passivation layer 260 is silicon nitride, and the material of the second passivation layer 270 is polyimide. The second passivation layer 270 has a thickness of 4 micrometers to 18 micrometers. The structure using two passivation layers here can not only block the advantages of external movable ions, water vapor and the like, but also can effectively shield the surface charge induced by the movable charge introduced into the chip during the preparation process.
该高压半导体器件终端200的衬底210为N型衬底，场限环220是P型掺杂，表面增强区230所掺杂的杂质为N型杂质。表面增强区230中N型杂质的注入剂量为2e11~1e13cm-2，注入能量为60keV~120keV。表面增强区230的方块电阻为400Ω/□~6000Ω/□。表面增强区230的宽度大于相邻两个场限环220之间的距离，也就是说表面增强区230与两个相邻的场限环220相连接。场限环220的方块电阻为10Ω/□~1200Ω/□。The substrate 210 of the high voltage semiconductor device terminal 200 is an N-type substrate, the field limiting ring 220 is P-type doped, and the impurity doped by the surface enhancement region 230 is an N-type impurity. The implantation dose of the N-type impurity in the surface enhancement region 230 is 2e11 to 1e13 cm -2 , and the implantation energy is 60 keV to 120 keV. The sheet resistance of the surface enhancement region 230 is 400 Ω/□ to 6000 Ω/□. The width of the surface enhancement zone 230 is greater than the distance between adjacent two field limiting rings 220, that is, the surface enhancement zone 230 is coupled to two adjacent field limiting rings 220. The sheet resistance of the field limit ring 220 is 10 Ω/□ to 1200 Ω/□.
该实施例中的高压半导体器件终端200在场限环220之间的区域增加了表面增强区230，这样场限环220之间区域的表面浓度得到增加，此处是通过离子注入工艺增强场限环220之间区域的表面浓度。在高温高压条件下，可动电荷在钝化层内有高电位向低电位迁移，在场限环220之间区域的场板240处聚集。通过增强场限环220之间区域的表面浓度，器件表面等效电荷增大，从而相应降低可动电荷对高压半导体器件终端200表面电场的影响，提高高压半导体器件终端200耐压，从而降低器件高温下的漏电流，增强其耐压可靠性。所以，该高压半导体器件终端200具有高温下漏电流小，耐压可靠性高的优点。另外，该高压半导体器件终端200在制造时只需增加增强场限环的表面浓度的步骤，制造工艺相对简单。The high voltage semiconductor device terminal 200 in this embodiment increases the surface enhancement region 230 in the region between the field limiting rings 220 such that the surface concentration of the region between the field limiting rings 220 is increased, here the field limiting ring is enhanced by the ion implantation process. The surface concentration of the area between 220. Under high temperature and high pressure conditions, the movable charge has a high potential to a low potential in the passivation layer, and is concentrated at the field plate 240 in the region between the field limiting rings 220. By increasing the surface concentration of the region between the field limiting rings 220, the equivalent charge of the device surface is increased, thereby correspondingly reducing the influence of the movable charge on the surface electric field of the high voltage semiconductor device terminal 200, and improving the withstand voltage of the high voltage semiconductor device terminal 200, thereby reducing the device. Leakage current at high temperature enhances its withstand voltage reliability. Therefore, the high voltage semiconductor device terminal 200 has an advantage that the leakage current at a high temperature is small and the withstand voltage reliability is high. In addition, the high voltage semiconductor device terminal 200 only needs to increase the surface concentration of the field limiting ring at the time of manufacture, and the manufacturing process is relatively simple.
本发明的还提供一种高压半导体器件。该高压半导体器件可以为双扩散金属氧化物半导体场效应管、绝缘栅双极型晶体管或其它高压半导体器件。该高压半导体器件具有实施例1中如图2所示的高压半导体器件终端200。请参考图3与图4，图3中的双扩散金属氧化物半导体场效应管具有双扩散金属氧化物半导体场效应管的结构和高压半导体器件终端200结构。图4中的绝缘栅双极型晶体管具有绝缘栅双极型晶体管的结构和高压半导体器件终端200结构。此处的双扩散金属氧化物半导体场效应管和绝缘栅双极型晶体管的结构与常用的双扩散金属氧化物半导体场效应管和绝缘栅双极型晶体管结构相似，区别仅在于它们具有实施例1中的高压半导体器件终端200的结构。因为高压半导体器件终端200具有高温下漏电流小，耐压可靠性高的优点，因此该高压半导体器件（双扩散金属氧化物半导体场效应管和绝缘栅双极型晶体管）也具有高温下漏电流小，耐压可靠性高的优点，并且制造工艺简单。The present invention also provides a high voltage semiconductor device. The high voltage semiconductor device can be a double diffused metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, or other high voltage semiconductor device. This high voltage semiconductor device has the high voltage semiconductor device terminal 200 as shown in FIG. 2 in Embodiment 1. Referring to FIG. 3 and FIG. 4, the double-diffused metal oxide semiconductor field effect transistor of FIG. 3 has a structure of a double-diffused metal oxide semiconductor field effect transistor and a high-voltage semiconductor device terminal 200 structure. The insulated gate bipolar transistor of FIG. 4 has a structure of an insulated gate bipolar transistor and a high voltage semiconductor device terminal 200 structure. The structure of the double-diffused metal oxide semiconductor field effect transistor and the insulated gate bipolar transistor here is similar to that of the conventional double-diffused metal oxide semiconductor field effect transistor and the insulated gate bipolar transistor, except that they have the embodiment. The structure of the high voltage semiconductor device terminal 200 in 1. Since the high-voltage semiconductor device terminal 200 has the advantages of low leakage current at high temperature and high withstand voltage reliability, the high-voltage semiconductor device (double-diffused metal oxide semiconductor field effect transistor and insulated gate bipolar transistor) also has a leakage current at a high temperature. Small, high pressure reliability, and simple manufacturing process.
本发明的还提供一种高压半导体器件终端200制造方法。该高压半导体器件终端200为实施例1中如图2所示的高压半导体器件终端200。请参考图5，该高压半导体器件终端200制造方法包括以下步骤。The present invention also provides a method of fabricating a high voltage semiconductor device terminal 200. The high voltage semiconductor device terminal 200 is the high voltage semiconductor device terminal 200 shown in FIG. 2 in Embodiment 1. Referring to FIG. 5, the high voltage semiconductor device terminal 200 manufacturing method includes the following steps.
步骤S110，提供衬底210，该衬底210具有第一表面211和与第一表面211相对的第二表面212。此处，该衬底210为N型衬底210。Step S110, providing a substrate 210 having a first surface 211 and a second surface 212 opposite the first surface 211. Here, the substrate 210 is an N-type substrate 210.
步骤S120，在衬底210的第一表面211形成场氧化层250、场限环220和表面增强区230，表面增强区230位于场限环220两侧，表面增强区230与衬底210的导电类型相同，且表面增强区230的掺杂浓度大于衬底210的掺杂浓度。下面将详细介绍一下场氧化层250、场限环220和表面增强区230的生长步骤。In step S120, a field oxide layer 250, a field limiting ring 220 and a surface enhancement region 230 are formed on the first surface 211 of the substrate 210. The surface enhancement region 230 is located on both sides of the field limiting ring 220, and the surface enhancement region 230 is electrically conductive with the substrate 210. The types are the same, and the doping concentration of the surface enhancement region 230 is greater than the doping concentration of the substrate 210. The growth steps of the field oxide layer 250, the field limiting ring 220, and the surface enhancement region 230 will be described in detail below.
请参考图6，在衬底210的第一表面211生长一层厚度为1000埃~3000埃的场氧化层250。然后，经过涂胶、曝光、硬烘、刻蚀等步骤后，进行离子注入。此时离子注入剂量为2e11~1e13 cm-2，离子注入能量为60keV~120keV，离子注入时的离子为N型杂质。Referring to FIG. 6, a field oxide layer 250 having a thickness of 1000 angstroms to 3,000 angstroms is grown on the first surface 211 of the substrate 210. Then, after the steps of coating, exposure, hard baking, etching, etc., ion implantation is performed. At this time, the ion implantation dose is 2e11~1e13 cm -2 , the ion implantation energy is 60 keV~120 keV, and the ions during ion implantation are N-type impurities.
请参考图7，离子注入后进行去胶、清洗等步骤，然后进行1100℃~1200℃的有氧环境推阱形成表面增强区230，同时生长6000埃~20000埃的场氧化层250。此处是将场氧化层250进行加厚并覆盖表面增强区230。Referring to FIG. 7, after ion implantation, a step of removing glue, cleaning, etc. is performed, and then an aerobic environment of 1100 ° C to 1200 ° C is used to form a surface enhancement region 230, and a field oxide layer 250 of 6000 Å to 20,000 Å is grown. Here, the field oxide layer 250 is thickened and covers the surface enhancement region 230.
请参考图8，在场氧化层250上进行涂胶、曝光、湿法腐蚀、去胶等步骤，然后进行离子注入。此时离子注入剂量为1e13~1e15cm-2能量为60keV~120keV，离子注入时的离子为P型杂质。Referring to FIG. 8, a step of coating, exposing, wet etching, degumming, etc. is performed on the field oxide layer 250, followed by ion implantation. At this time, the ion implantation dose is 1e13 to 1e15 cm -2 and the energy is 60 keV to 120 keV, and the ions during ion implantation are P-type impurities.
请参考图9，离子注入后进行去清洗等步骤，并在1100℃~1200℃的氮气环境中推阱形成场限环220。Referring to FIG. 9, after ion implantation, steps such as de-cleaning are performed, and the well is formed in a nitrogen atmosphere at 1100 ° C to 1200 ° C to form a field limiting ring 220.
请参考图10，在场氧化层250上淀积8000埃~16000埃的硼磷硅玻璃（boro-phospho-silicate-glass，BPSG），在850℃~950℃进行回流，形成介质层251。Referring to FIG. 10, boro-phospho-silicate-glass (BPSG) of 8000 Å to 16,000 Å is deposited on the field oxide layer 250, and reflowed at 850 ° C to 950 ° C to form a dielectric layer 251.
步骤S130，形成场板240，该场板240部分覆盖场限环220和场氧化层250。请参考图11，在形成介质层251后进行涂胶、曝光、刻蚀、去胶等步骤，然后淀积正面金属从而在场限环220和场氧化层250上形成场板240。In step S130, a field plate 240 is formed, which partially covers the field limiting ring 220 and the field oxide layer 250. Referring to FIG. 11, after the dielectric layer 251 is formed, a step of coating, exposing, etching, stripping, etc. is performed, and then a front metal is deposited to form a field plate 240 on the field limiting ring 220 and the field oxide layer 250.
步骤S140，形成钝化层，该钝化层覆盖场板240和场氧化层250。请参考图12，在形成场板240后进行涂胶、曝光、湿法腐蚀、去胶等步骤，然后淀积第一钝化层260。此处的第一钝化层260的材质为氮化硅。请参考图13，进行涂胶、曝光、去胶、380℃~450℃退火固化等步骤后，淀积形成第二钝化层270。此处第二钝化层270的材质为聚酰亚胺。In step S140, a passivation layer is formed, which covers the field plate 240 and the field oxide layer 250. Referring to FIG. 12, after the field plate 240 is formed, a step of coating, exposing, wet etching, degumming, etc. is performed, and then the first passivation layer 260 is deposited. The material of the first passivation layer 260 here is silicon nitride. Referring to FIG. 13, after the steps of coating, exposing, degumming, annealing and curing at 380 ° C to 450 ° C, a second passivation layer 270 is deposited. Here, the material of the second passivation layer 270 is polyimide.
该高压半导体器件终端200制造方法还包括步骤S150，形成背面金属层280。如图2所示，在衬底210的第二表面212淀积形成背面金属层280。The high voltage semiconductor device terminal 200 manufacturing method further includes a step S150 of forming a back metal layer 280. As shown in FIG. 2, a back metal layer 280 is deposited on the second surface 212 of the substrate 210.
经过上述工艺步骤就完成了该高压半导体器件终端200的制造。该高压半导体器件终端200制造方法采用与平面工艺完全兼容的工艺技术，制造工艺简单。通过离子注入增强场限环220的表面浓度，以降低可动电荷对高压半导体器件终端200表面电场的影响，稳定高压半导体器件终端200的表面电场，从而降低高压半导体器件终端200高温下的漏电流，增强其耐压可靠性。The fabrication of the high voltage semiconductor device terminal 200 is completed through the above process steps. The manufacturing method of the high voltage semiconductor device terminal 200 employs a process technology that is completely compatible with a planar process, and the manufacturing process is simple. The surface concentration of the field limiting ring 220 is enhanced by ion implantation to reduce the influence of the movable charge on the surface electric field of the high voltage semiconductor device terminal 200, and the surface electric field of the high voltage semiconductor device terminal 200 is stabilized, thereby reducing the leakage current at high temperature of the high voltage semiconductor device terminal 200. To enhance its pressure reliability.
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。The above-mentioned embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims (10)

  1. 一种高压半导体器件终端，其特征在于，包括衬底，所述衬底具有第一表面，所述高压半导体器件终端还包括位于所述第一表面的场限环、同样位于所述第一表面且位于所述场限环两侧的表面增强区、位于所述第一表面且覆盖所述表面增强区的场氧化层、位于所述第一表面且部分覆盖所述场限环和所述场氧化层的场板及覆盖所述场板和所述场氧化层的钝化层，所述表面增强区与所述衬底的导电类型相同，且所述表面增强区的掺杂浓度大于所述衬底的掺杂浓度。A high voltage semiconductor device terminal, comprising: a substrate having a first surface, the high voltage semiconductor device terminal further comprising a field limiting ring on the first surface, also located on the first surface And a surface enhancement region on both sides of the field limiting ring, a field oxide layer on the first surface and covering the surface enhancement region, on the first surface and partially covering the field limiting ring and the field a field plate of the oxide layer and a passivation layer covering the field plate and the field oxide layer, the surface enhancement region is of the same conductivity type as the substrate, and the doping concentration of the surface enhancement region is greater than The doping concentration of the substrate.
  2. 根据权利要求1所述的高压半导体器件终端，其特征在于，所述钝化层包括第一钝化层和覆盖所述第一钝化层的第二钝化层。The high voltage semiconductor device terminal according to claim 1, wherein the passivation layer comprises a first passivation layer and a second passivation layer covering the first passivation layer.
  3. 根据权利要求2所述的高压半导体器件终端，其特征在于，所述第二钝化层的材质为聚酰亚胺。The high voltage semiconductor device terminal according to claim 2, wherein the material of the second passivation layer is polyimide.
  4. 根据权利要求1所述的高压半导体器件终端，其特征在于，所述衬底为N型衬底，所述表面增强区所掺杂的杂质为N型杂质，所述表面增强区的方块电阻为400Ω/□~6000Ω/□。The high voltage semiconductor device terminal according to claim 1, wherein said substrate is an N-type substrate, said surface enhancement region is doped with an impurity of an N-type impurity, and said surface enhancement region has a sheet resistance of 400Ω/□~6000Ω/□.
  5. 根据权利要求1所述的高压半导体器件终端，其特征在于，所述表面增强区的宽度大于相邻两个场限环之间的距离。The high voltage semiconductor device terminal according to claim 1, wherein a width of said surface enhancement region is greater than a distance between adjacent two field limiting rings.
  6. 一种高压半导体器件，其特征在于，包括如权利要求1至5中任意一项所述的高压半导体器件终端。A high voltage semiconductor device comprising the high voltage semiconductor device terminal according to any one of claims 1 to 5.
  7. 根据权利要求6所述的高压半导体器件，其特征在于，所述高压半导体器件为双扩散金属氧化物半导体场效应管或绝缘栅双极型晶体管。The high voltage semiconductor device according to claim 6, wherein said high voltage semiconductor device is a double diffused metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.
  8. 一种高压半导体器件终端制造方法，其特征在于，包括以下步骤：A method for manufacturing a high voltage semiconductor device terminal, comprising the steps of:
    提供衬底，所述衬底具有第一表面；Providing a substrate having a first surface;
    在所述衬底的第一表面形成场氧化层、场限环和表面增强区，所述表面增强区位于所述场限环两侧，所述表面增强区与所述衬底的导电类型相同，且所述表面增强区的掺杂浓度大于所述衬底的掺杂浓度；Forming a field oxide layer, a field limiting ring, and a surface enhancement region on a first surface of the substrate, the surface enhancement region being located on both sides of the field limiting ring, the surface enhancement region being of the same conductivity type as the substrate And a doping concentration of the surface enhancement region is greater than a doping concentration of the substrate;
    在所述第一表面形成场板，所述场板部分覆盖所述场限环和所述场氧化层；Forming a field plate on the first surface, the field plate partially covering the field limiting ring and the field oxide layer;
    形成钝化层，所述钝化层覆盖所述场板和所述场氧化层。A passivation layer is formed, the passivation layer covering the field plate and the field oxide layer.
  9. 根据权利要求8所述的高压半导体器件终端制造方法，其特征在于，所述衬底为N型衬底，所述表面增强区所掺杂的杂质为N型杂质，所述N型杂质的注入剂量为2e11~1e13cm-2，注入能量为60keV~120keV。The method of manufacturing a high voltage semiconductor device terminal according to claim 8, wherein the substrate is an N-type substrate, and impurities doped in the surface enhancement region are N-type impurities, and the N-type impurity is implanted. The dose is 2e11~1e13cm -2 and the implantation energy is 60keV~120keV.
  10. 根据权利要求8所述的高压半导体器件终端制造方法，其特征在于，所述钝化层包括第一钝化层和覆盖所述第一钝化层的第二钝化层。The method of manufacturing a high voltage semiconductor device terminal according to claim 8, wherein the passivation layer comprises a first passivation layer and a second passivation layer covering the first passivation layer.
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CN108922888B (en) * 2018-08-31 2023-06-06 江苏丽隽功率半导体有限公司 Terminal structure of power device and manufacturing method thereof
CN115472495A (en) * 2022-07-21 2022-12-13 上海林众电子科技有限公司 Preparation method of power chip termination area and preparation method of power chip
CN115472495B (en) * 2022-07-21 2024-05-31 上海林众电子科技有限公司 Preparation method of power chip termination region and preparation method of power chip

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