CN115566007B - Semiconductor structure, preparation method thereof and preparation method of semiconductor device - Google Patents
Semiconductor structure, preparation method thereof and preparation method of semiconductor device Download PDFInfo
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
The application relates to a semiconductor structure, a preparation method of the semiconductor structure and a preparation method of a semiconductor device. The semiconductor structure includes: the epitaxial transmission layer comprises device areas and test areas which are arranged in an alternating mode; the structure to be tested is at least partially positioned in the device area; the test structure is at least partially positioned in the test area, and a space is formed between the test structure and the structure to be tested; the source electrode of the structure to be tested is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the second excitation signal is transmitted to the source electrode of the structure to be tested by the test structure through the epitaxial transmission layer to form a test loop, wherein the test loop is formed; the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; and the voltage difference between the second voltage signal and the first voltage signal is used for detecting the on-resistance of the structure to be detected.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure, a method for manufacturing the same, and a method for manufacturing a semiconductor device.
Background
The on-resistance (Rdson) of a semiconductor device is one of the more critical parameters of the device, and therefore the detection of the on-resistance is one of the key points of wafer level testing. Due to the progress of technology and the update of products, the on-resistance of devices is getting smaller and smaller, and at present, the on-resistance reaches the milliohm level, and in order to accurately measure the on-resistance, the kelvin connection method is usually adopted for measurement so as to reduce errors.
For TMOS (short for TMOSFET, trench Metal-Oxide Semiconductor Field Effect Transistor), its Source (Source) and Gate (Gate) are on the front side of the wafer, while the Drain (Drain) is on the back side of the wafer. When the wafer test detects the on-resistance, the wafer is adsorbed on a sucker (Chuck) of a probe station, a drain electrode is shielded by the sucker and cannot be directly connected, kelvin double lines can only be connected to the edge of the sucker, and the back surface is thinned and plated with gold in the process of TMOS (TMOS), so that the back surface is uneven.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor structure, a method for manufacturing the same, and a method for manufacturing a semiconductor device.
To achieve the above object, in one aspect, the present application provides a semiconductor structure comprising:
the epitaxial transmission layer comprises device areas and test areas which are arranged alternately;
the structure to be tested is at least partially positioned in the device area;
the test structure is at least partially positioned in the test area, and a space is formed between the test structure and the structure to be tested; wherein,
the source electrode of the structure to be tested is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the test structure transmits the second excitation signal to a source electrode of the structure to be tested through the epitaxial transmission layer to form a test loop; wherein,
the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; and detecting the on-resistance of the structure to be detected by using the voltage difference between the second voltage signal and the first voltage signal.
In the semiconductor structure, a first excitation signal and a first detection signal are received through a source electrode, a second excitation signal and a second detection signal are received through a test electrode, and a Kelvin connection method is formed; the second excitation signal is transmitted to a source electrode of the structure to be tested through the epitaxial transmission layer through the test structure to form a test loop, the source electrode outputs a first voltage signal, the test electrode outputs a second voltage signal, and the on-resistance of the test loop can be obtained based on the voltage difference between the second voltage signal and the first voltage signal and the second excitation signal.
In one embodiment, the structure under test includes:
the first injection layer is positioned in the epitaxial transmission layer;
the first isolation laminated layer is positioned on the surface, away from the epitaxial transmission layer, of the first injection layer;
a first contact structure penetrating the first isolation stack and the first injection layer in a thickness direction;
the first electrode layer is positioned on the surfaces, far away from the first injection layer, of the first isolation laminated layer and the first contact structure;
the test structure includes:
the second injection layer is positioned in the epitaxial transmission layer;
the second isolation laminated layer is positioned on the surface, away from the epitaxial transmission layer, of the second injection layer;
a second contact structure penetrating the second isolation stack and the second injection layer in a thickness direction;
and the second electrode layer is positioned on the surfaces of the second isolation laminated layer and the second contact structure, which are far away from the second injection layer.
In one embodiment, the structure to be tested further includes:
the body region is positioned in the epitaxial transmission layer, positioned on the surface, away from the first isolation laminated layer, of the first injection layer and contacted with the first contact structure;
and the groove structure is positioned in the epitaxial transmission layer, penetrates through the body region and the first injection layer and is in contact with the first isolation lamination.
In one embodiment, the structure under test further includes:
the reflecting layer is positioned on the surface of the first electrode layer far away from the first isolation laminated layer;
the first passivation layer is positioned on the surface of the reflecting layer, which is far away from the first electrode layer;
the second passivation layer is positioned on the surface, far away from the reflecting layer, of the first passivation layer;
and the source electrode opening penetrates through the reflecting layer, the first passivation layer and the second passivation layer and exposes part of the first electrode layer.
In one embodiment, the first and second driving signals are current signals, respectively.
In one embodiment, the number of the structures to be tested is multiple, and the multiple structures to be tested are respectively arranged at intervals with the test structure; and at least two structures to be tested share the same test structure when being tested.
In one embodiment, the width of the test zone is 60-80 μm; the width of the test structure is 45-55 μm, and the length of the test structure is 65-75 μm.
The present application further provides a method for manufacturing a semiconductor structure, comprising:
forming an epitaxial transmission layer, wherein the epitaxial transmission layer comprises device areas and test areas which are alternately arranged;
forming a structure to be tested and a test structure, wherein at least part of the structure to be tested is positioned in the device area, at least part of the test structure is positioned in the test area, and a gap is formed between the test structure and the structure to be tested; wherein,
the source electrode of the structure to be tested is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the test structure transmits the second excitation signal to a source electrode of the structure to be tested through the epitaxial transmission layer to form a test loop, wherein the first excitation signal and the second excitation signal are different in frequency;
the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; and detecting the on-resistance of the structure to be detected by using the voltage difference between the second voltage signal and the first voltage signal.
According to the preparation method of the semiconductor structure, in the prepared semiconductor structure, the source electrode receives the first excitation signal and the first detection signal, and the test electrode receives the second excitation signal and the second detection signal, so that a Kelvin connection method is formed; the second excitation signal is transmitted to a source electrode of the structure to be tested through the epitaxial transmission layer through the test structure to form a test loop, the source electrode outputs a first voltage signal, the test electrode outputs a second voltage signal, and the on-resistance of the test loop can be obtained based on the voltage difference between the second voltage signal and the first voltage signal and the second excitation signal.
In one embodiment, the forming the structure to be tested and the test structure includes:
forming a first injection layer and a second injection layer in the epitaxial transport layer, wherein the first injection layer and the second injection layer have a gap;
forming a first isolation lamination on the surface of the first injection layer, and forming a second isolation lamination on the surface of the second injection layer;
sequentially etching the first isolation lamination layer and the first injection layer along the thickness direction to form a first contact hole, and sequentially etching the second isolation lamination layer and the second injection layer along the thickness direction to form a second contact hole;
filling a first contact medium lamination and a first contact conducting layer in the first contact hole to form a first contact structure, and filling a second contact medium lamination and a second contact conducting layer in the second contact hole to form a second contact structure;
forming a first electrode layer on the surfaces of the first contact structure and the first isolation lamination layer, which are far away from the first injection layer, and forming a second electrode layer on the surfaces of the second contact structure and the second isolation lamination layer, which are far away from the second injection layer;
wherein the structure to be tested comprises the first injection layer, the first isolation stack, the first contact structure and the first electrode layer; the test structure includes the second injection layer, the second isolation stack, the second contact structure, and the second electrode layer.
The present application also provides a method for manufacturing a semiconductor device, including:
the semiconductor structure is prepared by adopting the preparation method of the semiconductor structure according to any scheme of the application;
after testing the semiconductor structure is completed, the device region is separated from the test region.
According to the preparation method of the semiconductor device, the semiconductor structure is prepared by adopting the preparation method of the semiconductor structure, in the semiconductor structure, a first excitation signal and a first detection signal are received through a source electrode, a second excitation signal and a second detection signal are received through a test electrode, and a Kelvin connection method is formed; the second excitation signal is transmitted to a source electrode of the structure to be tested through the epitaxial transmission layer through the test structure to form a test loop, the source electrode outputs a first voltage signal, the test electrode outputs a second voltage signal, and the on-resistance of the test loop can be obtained based on the voltage difference between the second voltage signal and the first voltage signal and the second excitation signal; after the test is finished, the device area is separated from the test area to obtain the semiconductor device, and the device area of the semiconductor device cannot be damaged.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a cross-sectional schematic view of a semiconductor structure provided in one embodiment;
FIG. 2 is a schematic diagram illustrating a top view of a semiconductor structure provided in one embodiment;
FIG. 3 is a schematic diagram of the connections between the analog circuitry and the structure for measuring the on-resistance of a semiconductor structure using Kelvin connections provided in one embodiment;
FIG. 4 is a flow chart of a method of fabricating a semiconductor structure provided in one embodiment;
fig. 5 is a schematic cross-sectional structure diagram of a structure obtained in step S101 in the method for manufacturing a semiconductor structure provided in one embodiment;
FIG. 6 is a flowchart illustrating a step S102 of a method for fabricating a semiconductor structure according to an exemplary embodiment;
fig. 7 is a schematic cross-sectional structure view of the structure obtained in step S1022 in the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 8 is a schematic cross-sectional structure diagram of a structure obtained in step S1023 in the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 9 is a schematic cross-sectional structure view of a structure obtained in step S1024 in the method for manufacturing a semiconductor structure provided in one embodiment;
fig. 10 is a schematic cross-sectional structure diagram illustrating the structure obtained in step S1025 in the method for fabricating a semiconductor structure according to an embodiment;
fig. 11 is a flowchart of a method of manufacturing a semiconductor device provided in an embodiment;
fig. 12 is a schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment.
Description of reference numerals:
1-a substrate; 2-an epitaxial transport layer; 201-a device region; 202-a test zone; 3-a structure to be tested; 30-a body region; 301-heavily doped region; 31-a first implanted layer; 32-a trench structure; 321-a trench oxide layer; 322-a shielding grid; 323-control gate; 33-a first barrier stack; 331-a first isolation layer; 332-a second barrier layer; 333-a third barrier layer; 34-a first contact structure; 341-first contact hole; 342-a first contact dielectric layer; 343-a second contact dielectric layer; 344 — first contact conductive layer; 35-a first electrode layer; 36 a reflective layer; 37-a first passivation layer; 38-a second passivation layer; 39-source opening; 4-testing the structure; 40-a second implanted layer; 41-a second barrier stack; 411-a fourth separation layer; 412-a fifth spacer layer; 413-a sixth separation layer; 42-a second contact structure; 421-second contact hole; 422-a third contact dielectric layer; 423-fourth contact medium layer; 424-second contact conductive layer; 43-a second electrode layer; 5-a drain layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
The on-resistance of a semiconductor device is one of the more critical parameters of the device, and therefore the detection of the on-resistance is one of the key points of wafer level testing. Due to the progress of technology and the update of products, the on-resistance of devices is getting smaller and smaller, and at present, the on-resistance reaches the milliohm level, and in order to accurately measure the on-resistance, the kelvin connection method is usually adopted for measurement so as to reduce errors.
For TMOS, its source and gate are on the front side of the wafer and its drain is on the back side of the wafer. When detecting the on-resistance in the wafer level test, the wafer is adsorbed on the sucking disc of probe platform, the drain electrode is sheltered from unable lug connection by the sucking disc, can only be with kelvin double-line connection to the edge of sucking disc, because TMOS can carry out attenuate and gilding to the back in the processing procedure, cause the unevenness at the back, when the wafer test, the wafer back only has partial area contact with the test sucking disc, make chip back contact resistance great, simultaneously because the contact is random variation, lead to test result unstable, test error is great, can't realize real kelvin and connect the method.
At present, the traditional solution is to use the adjacent chip for assistance, test the chip to be tested and simultaneously pressurize the grid of the adjacent chip to conduct the adjacent chip, and equivalently realize the kelvin connection method, but the method has more defects: if the adjacent chips are abnormal (open circuit or grid source short circuit), the chip to be detected is misdetected; because the chips in the row at the outermost edge of the wafer are not provided with adjacent chips for auxiliary test, the on-resistance of the chips cannot be tested; the method needs repeated needle insertion, and the chip is easy to damage.
In view of the above, it is necessary to provide a semiconductor structure, a method for manufacturing the same, and a method for manufacturing a semiconductor device.
As shown in fig. 1 and 2, the present application provides a semiconductor structure comprising: the device comprises an epitaxial transmission layer 2, a structure to be tested 3 and a test structure 4; the epitaxial transmission layer 2 comprises device regions 201 and test regions 202 which are arranged alternately; the structure to be tested 3 is at least partially positioned in the device region 201; the test structure 4 is at least partially located in the test area 202, and a space is formed between the test structure 4 and the structure 3 to be tested; the source electrode of the structure to be tested 3 is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure 4 is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the test structure 4 transmits the second excitation signal to the source electrode of the structure to be tested 3 through the epitaxial transmission layer 2 to form a test loop, wherein the test loop is formed; the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; the voltage difference between the second voltage signal and the first voltage signal is used for detecting the on-resistance of the structure to be detected 3.
Wherein, the epitaxial transmission layer 2 may include, but is not limited to, a homo-epitaxial layer or a hetero-epitaxial layer; illustratively, the epitaxial transport layer 2 may be a lightly doped epitaxial transport layer, and the embodiment is not limited herein.
The first excitation signal and the second excitation signal respectively comprise current signals; the first detection signal and the second detection signal respectively comprise voltage signals; the current value of the first excitation signal may be the same as the current value of the second excitation signal, and the voltage value of the first detection signal may be smaller than the voltage value of the second detection signal. The structure to be tested 3 may include, but is not limited to, die (bare chip) and the like; the test electrode of the test structure 4 can be used as a drain electrode, a test loop is formed between the test structure 4 and the structure 3 to be tested, the second excitation signal is the test current of the test loop, and according to the test current, the voltage difference between the second voltage signal and the first voltage signal and the ohm law, the conduction resistance is equal to the voltage difference between the second voltage signal and the first voltage signal divided by the test current, so that the conduction resistance of the test loop can be obtained, and the conduction resistance between the source electrode and the drain electrode can be obtained.
As shown in fig. 3, which is a schematic diagram of connection between an analog circuit and a structure for measuring on-resistance of a semiconductor structure of the present application by using a kelvin connection method, in conjunction with fig. 2, two opposite sides of a structure to be measured 3 are provided with test structures 4, and the number of the test structures 4 on each side is at least one, where HF represents applying a second excitation signal to a test electrode of the test structure 4 on one side of the structure to be measured 3 through a probe card; HS represents applying a second detection signal to the test electrode of the test structure 4 on the other side of the structure to be tested 3 by a probe card, and the second excitation signal is a current signal, that is, a test current after conduction between the test structure 4 and the structure to be tested 3; LF represents that a first excitation signal is applied to the source electrode of the structure to be tested 3 through the probe card; LS represents that a first detection signal is applied to the source electrode of the structure to be detected 3 through the probe card; r1 is the sum of the resistance between the probe card and the test electrode at the HF needle inserting position and the resistance of all structures passing through the test structure 4 to the structure to be tested 3; r2 is the sum of the resistance between the probe card and the test electrode at the HS puncture position and the resistance of all structures passing through the test structure 4 to the structure to be tested 3; r3 is the resistance between the probe card and the source electrode at the LF puncture position; r4 is the resistance between the probe card and the source at the LS pin. Therefore, the source-drain voltage difference is calculated according to the measured output voltage of the source electrode and the output voltage of the testing electrode, and the on-resistance is equal to the current value of the second excitation signal divided by the source-drain voltage difference.
Referring to fig. 2, the number of the test structures 4 is at least one, and it can be understood that the number of the test structures 4 between adjacent structures to be tested 3 may be one or more than 1, and the number is set according to the requirement, which is not limited in this embodiment.
In the semiconductor structure in the above embodiment, the first excitation signal and the first detection signal are received by the source electrode, and the second excitation signal and the second detection signal are received by the test electrode, so that the kelvin connection method is formed; the second excitation signal is transmitted to the source electrode of the structure to be tested 3 through the epitaxial transmission layer 2 through the test structure 4 to form a test loop, the source electrode outputs a first voltage signal, the test electrode outputs a second voltage signal, and the on-resistance of the test loop can be obtained based on the voltage difference between the second voltage signal and the first voltage signal and the second excitation signal.
In one embodiment, still referring to fig. 2, the number of structures to be tested 3 may be plural, and the number of test structures 4 may be plural; the structures to be tested 3 are respectively arranged at intervals with the test structure 4; when being tested, at least two structures to be tested 3 share the same test structure 4.
The device area 201 may be a plurality of, the test area 202 may be a plurality of, and each test area 202 may have a plurality of test structures 4, that is, the number of test structures 4 may be set according to requirements, which is not limited in this embodiment.
It can be understood that the test structures 4 are disposed between adjacent structures to be tested 3, and each test structure 4 can serve as a drain equivalent test structure for a plurality of structures to be tested 3, so as to implement the kelvin connection method for testing the on-resistance.
In one embodiment, the width of the test area 202 is 60 μm to 80 μm; the width of the test structure 4 is 45 μm to 55 μm, and the length of the test structure 4 is 65 μm to 75 μm.
The test area 202 can be an area between adjacent structures to be tested 3, the area between adjacent structures to be tested 3 can also be called a cutting street, and the width of the cutting street is 60-80 μm; the width of the scribe line is, for example, 60 μm, 65 μm, 70 μm, 75 μm or 80 μm, and other widths between 60 μm and 80 μm are also possible, without limitation. The width of the test structure 4 may be 45 μm, 50 μm or 55 μm, or may be other widths between 45 μm and 55 μm, without limitation. The length of the test structure 4 may be 65 μm, 70 μm or 75 μm, or may be other widths between 65 μm and 75 μm, without limitation.
In one embodiment, referring to fig. 1, the semiconductor structure further comprises a substrate 1; wherein, the epitaxial transmission layer 2 is formed on the surface of the substrate 1.
Illustratively, the substrate 1 may be a doped substrate of a first conductivity type; the epitaxial transport layer 2 may be a doped epitaxial layer of the first conductivity type.
In one embodiment, still referring to fig. 1, the structure under test 3 includes: a first injection layer 31, a first isolation stack 33, a first contact structure 34 and a first electrode layer 35; the first implantation layer 31 is located within the epitaxial transport layer 2; the first isolation stack 33 is located on the surface of the first implantation layer 31 away from the epitaxial transport layer 2; the first contact structure 34 penetrates the first isolation stack 33 and the first implant layer 31 in the thickness direction; the first electrode layer 35 is located on the surface of the first isolation stack 33 and the first contact structure 34 away from the first injection layer 31; the test structure 4 includes: a second injection layer 40, a second isolation stack 41, a second contact structure 42, and a second electrode layer 43; the second injection layer 40 is positioned in the epitaxial transport layer 2; a second isolation stack 41 located on the surface of the second implantation layer 40 away from the epitaxial transport layer 2; the second contact structure 42 penetrates the second isolation stack 41 and the second injection layer 40 along the thickness direction; the second electrode layer 43 is located on the surface of the second isolation stack 41 and the second contact structure 42 away from the second injection layer 40.
Still referring to fig. 1, the structure to be tested 3 further includes: a body region 30, a heavily doped region 301 and a trench structure 32; the body region 30 is located within the epitaxial transport layer 2 and at the surface of the first implantation layer 31 remote from the first isolation stack 33 and in contact with the first contact structure 34; the heavily doped region 301 is located in the body region 30 and below the first contact structure 34, and contacts the first contact structure 34; the trench structure 32 is located within the epitaxial transport layer 2 and penetrates the body region 30 and the first implant layer 31 and is in contact with the first isolation stack 33.
The first injection layer 31 and the second injection layer 40 are both injection layers of a first conductivity type, the body region 30 is a body region of a second conductivity type, and the heavily doped region 301 is a heavily doped region of the second conductivity type; the doping concentration of the heavily doped region 301 is higher than that of the body region 30; the first conductive type may be an N-type, and the second conductive type may be a P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type. The trench structure 32 includes a trench oxide 321, a shield gate 322 and a control gate 323; the trench oxide 321 is in contact with the body 30, the first implant layer 31 and the first isolation stack 33, and the shield gate 322 and the control gate 323 are located in the trench oxide 321. Both the shield gate 322 and the control gate 323 may comprise a polysilicon layer.
The first electrode layer 35 and the second electrode layer 43 each include a metal layer. When a second excitation signal and a second detection signal are applied to the test electrode, and a first excitation signal and a first detection signal are applied to the source, the test current flows through the second electrode layer 43 to the second contact structure 42 and the second injection layer 40 in sequence, flows from the second injection layer 40 to the epitaxial transport layer 2, then flows through the epitaxial transport layer 2 to the body region 30, the first injection layer 31 and the first contact structure 34 in sequence, and finally flows to the first electrode layer 35 of the structure to be tested, a test loop is formed between the test structure 4 and the structure to be tested 3, the test structure 4 is equivalent to the test structure of the drain, and the test electrode is equivalent to the drain electrode, so that the drain and the source in the semiconductor structure are equivalent to be located on the same plane of the semiconductor structure, and conduction is performed between the source and the drain, and the conduction resistance can be measured by a true kelvin connection method.
Illustratively, still referring to fig. 1, the first isolation stack 33 may include: first isolation layer 331, second isolation layer 332, and third isolation layer 333; the first isolation layer 331 is located on the surface of the first injection layer 31; the second isolation layer 332 is located on the surface of the first isolation layer 331 away from the first injection layer 31; the third isolation layer 333 is located on the surface of the second isolation layer 332 away from the first isolation layer 331. The first separation layer 331 may include, but is not limited to, a TEOS (tetraethyl orthosilicate) layer; the second isolation layer 332 may include, but is not limited to, a BPSG (Boro-phosphate Glass) layer; the third spacer 333 may include, but is not limited to, a TEOS layer.
The second barrier stack 41 may include: a fourth separator 411, a fifth separator 412, and a sixth separator 413; the fourth isolation layer 411 is located on the surface of the second injection layer 40; the fifth isolation layer 412 is located on the surface of the fourth isolation layer 411 away from the second implanted layer 40; the sixth spacer 413 is positioned on the surface of the fifth spacer 412 away from the fourth spacer 411. The fourth isolation layer 411 may include, but is not limited to, a TEOS layer; the fifth isolation layer 412 may include, but is not limited to, a BPSG layer; the sixth isolation layer 413 may include, but is not limited to, a TEOS layer.
In one embodiment, referring to fig. 1 and 9, the first contact structure 34 includes: a first contact dielectric stack and a first contact conductive layer 344; the first contact dielectric stack includes a first contact dielectric layer 342 and a second contact dielectric layer 343; the first contact dielectric layer 342 is located on the sidewall and the bottom of the first contact hole 341; the second contact dielectric layer 343 is located on the surface of the first contact dielectric layer 342; the first contact conductive layer 344 is located on the surface of the second contact dielectric layer 343 away from the first contact dielectric layer 342. Illustratively, the first contact dielectric layer 342 may include, but is not limited to, a titanium layer; the second contact dielectric layer 343 may include, but is not limited to, a titanium nitride layer; the first contact conductive layer 344 may include, but is not limited to, a tungsten layer.
The second contact structure 42 includes a second contact dielectric stack and a second contact conductive layer 424; the second gate oxide stack layer comprises a third contact dielectric layer 422 and a fourth contact dielectric layer 423; the third contact dielectric layer 422 is located on the sidewall and the bottom of the second contact hole 421; the fourth contact dielectric layer 423 is positioned on the surface of the third contact dielectric layer 422; the second contact conductive layer 424 is located on the surface of the fourth contact dielectric layer 423 away from the third contact dielectric layer 422. Illustratively, the third contact dielectric layer 422 may include, but is not limited to, a titanium layer; the fourth contact dielectric layer 423 may include, but is not limited to, a titanium nitride layer; the second contact conductive layer 424 may include, but is not limited to, a tungsten layer.
In one embodiment, still referring to fig. 1, the semiconductor structure further comprises: a drain layer 5; the drain layer 5 is located at the surface of the epitaxial transport layer 2 remote from the first isolation stack 33.
In one embodiment, still referring to fig. 1, the structure under test 3 further includes: a reflective layer 36, a first passivation layer 37, a second passivation layer 38, and a source opening 39; the reflective layer 36 is located at the surface of the first electrode layer 35 remote from the first isolation stack 33; the first passivation layer 37 is located on the surface of the reflective layer 36 away from the first electrode layer 35; a second passivation layer 38 is located on the surface of the first passivation layer 37 remote from the reflective layer 36; the source opening 39 penetrates the reflective layer 36, the first passivation layer 37, and the second passivation layer 38, and exposes a portion of the first electrode layer 35.
Wherein the first passivation layer 37 may include, but is not limited to, an oxide layer; the second passivation layer 38 may include, but is not limited to, a nitride layer; at the time of testing, the probe tester pricks the first electrode layer 35 through the source opening 39.
As shown in fig. 4, the present application provides a method for manufacturing a semiconductor structure, comprising the steps of:
s101: forming an epitaxial transmission layer 2, wherein the epitaxial transmission layer 2 comprises device areas 201 and test areas 202 which are alternately arranged;
s102: forming a structure to be tested 3 and a test structure 4, wherein at least part of the structure to be tested 3 is positioned in the device area 201, at least part of the test structure 4 is positioned in the test area 202, and a gap is formed between the test structure 4 and the structure to be tested 3; the source electrode of the structure to be tested 3 is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure 4 is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the test structure 4 transmits the second excitation signal to the source electrode of the structure to be tested 3 through the epitaxial transmission layer 2 to form a test loop, wherein the test loop is formed; the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; the voltage difference between the second voltage signal and the first voltage signal is used for detecting the on-resistance of the structure to be detected 3.
The semiconductor structure obtained after steps S101-S102 can be referred to in fig. 1 and 2. Of course, fig. 1 and fig. 2 are an example of a semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to the present invention, and other suitable examples of the semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to the present invention are not limited herein.
Wherein, the epitaxial transmission layer 2 may include, but is not limited to, a homo-epitaxial layer or a hetero-epitaxial layer; illustratively, the epitaxial transport layer 2 may be a lightly doped epitaxial transport layer, and the embodiment is not limited herein.
The first excitation signal and the second excitation signal respectively comprise current signals; the first detection signal and the second detection signal respectively comprise voltage signals; the current value of the first excitation signal may be the same as the current value of the second excitation signal, and the voltage value of the first detection signal may be smaller than the voltage value of the second detection signal. The structure to be tested 3 may include, but is not limited to, die (bare chip) and the like; the test electrode of the test structure 4 can be used as a drain electrode, a test loop is formed between the test structure 4 and the structure 3 to be tested, the second excitation signal is the test current of the test loop, and according to the test current, the voltage difference between the second voltage signal and the first voltage signal and the ohm law, the conduction resistance is equal to the voltage difference between the second voltage signal and the first voltage signal divided by the test current, so that the conduction resistance of the test loop can be obtained, and the conduction resistance between the source electrode and the drain electrode can be obtained.
In the method for manufacturing a semiconductor structure in the above embodiment, the first excitation signal and the first detection signal may be received through the source electrode, and the second excitation signal and the second detection signal may be received through the test electrode, so that the kelvin connection method is formed; the second excitation signal is transmitted to the source electrode of the structure to be tested 3 through the epitaxial transmission layer 2 through the test structure 4 to form a test loop, the source electrode 39 outputs a first voltage signal, the test electrode outputs a second voltage signal, and the on-resistance of the test loop can be obtained based on the voltage difference between the second voltage signal and the first voltage signal and the second excitation signal.
In step S101, an epitaxial transport layer 2 may be formed, referring to fig. 5.
In one embodiment, an epitaxial transport layer 2 is formed on the surface of the substrate 1, and the resulting structure is shown in fig. 5.
The material of the substrate 1 may be any suitable material, and may be at least one of the following materials, for example: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III/V compound semiconductors, and may be a multilayer structure formed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be Double-Side Polished silicon Wafers (DSP), and the like, and the present embodiment is not limited thereto.
Illustratively, the substrate 1 may be a doped substrate of a first conductivity type; the epitaxial transport layer 2 may be a doped epitaxial layer of the first conductivity type.
In one embodiment, as shown in fig. 6, forming the structure to be tested 3 and the test structure 4 may include the following steps:
s1021: forming a first injection layer 31 and a second injection layer 40 in the epitaxial transport layer 2, wherein the first injection layer 31 and the second injection layer 40 have a gap;
s1022: forming a first isolation stack 33 on the surface of the first implant layer 31, and forming a second isolation stack 41 on the surface of the second implant layer 40;
s1023: sequentially etching the first isolation stack 33 and the first injection layer 31 in the thickness direction to form a first contact hole 341, and sequentially etching the second isolation stack 41 and the second injection layer 40 in the thickness direction to form a second contact hole 421;
s1024: filling the first contact hole 341 with a first contact dielectric stack and a first contact conductive layer 344 to form a first contact structure 34, and filling the second contact hole 421 with a second gate oxide stack and a second contact conductive layer 424 to form a second contact structure 42;
s1025: forming a first electrode layer 35 on the surfaces of the first contact structure 34 and the first isolation stack 33 away from the first injection layer 31, and forming a second electrode layer 43 on the surfaces of the second contact structure 42 and the second isolation stack 41 away from the second injection layer 40; the structure 3 to be tested comprises a first injection layer 31, a first isolation lamination 33, a first contact structure 34 and a first electrode layer 35; the test structure 4 comprises a second injection layer 40, a second isolation stack 41, a second contact structure 42 and a second electrode layer 43.
In one embodiment, before forming the first injection layer 31 and the second injection layer 40 in the epitaxial transport layer 2, the method further includes: a step of forming a body region 30 in the epitaxial transport layer 2, the body region 30 being in contact with the first contact structure 34; therein, a first implanted layer 31 is formed on the body region 30, see fig. 7.
The first injection layer 31 and the second injection layer 40 are both injection layers of a first conductivity type, and the body region 30 is a body region of a second conductivity type; the first conductive type may be an N-type, and the second conductive type may be a P-type; in other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.
In one embodiment, still referring to fig. 7, before forming the body region 30 in the epitaxial transport layer 2, the method for fabricating the semiconductor structure further includes: forming a trench structure 32 in the epitaxial transport layer 2, wherein the trench structure 32 penetrates through the body region 30 and the first injection layer 31 and extends into the epitaxial transport layer 2 outside the body region 30; wherein the trench structure 32 is in contact with the first isolation stack 33.
The trench structure 32 includes a trench oxide layer 321, a shield gate 322, and a control gate 323; the trench oxide 321 contacts the body 30, the first implant layer 31 and the first isolation stack 33, and the shield gate 322 and the control gate 323 are located in the trench oxide 321. Both the shield gate 322 and the control gate 323 may comprise a polysilicon layer.
In step S1021, please refer to fig. 7, a first injection layer 31 and a second injection layer 40 are formed in the epitaxial transport layer 2, and the first injection layer 31 and the second injection layer 40 have a gap therebetween.
Wherein the first and second implantation layers 31 and 40 may be formed by an ion implantation process; the first implantation layer 31 and the second implantation layer 40 may be formed simultaneously, and a patterned barrier layer may be formed on the surface of the epitaxial transport layer 2, where the patterned barrier layer exposes the surface of the epitaxial transport layer 2 that needs to be ion implanted, and the barrier layer helps to control the ion implantation area, so that ion implantation may be performed on different areas simultaneously.
In some examples, a first ion implantation may be performed on the epitaxial transport layer 2 to form a first implantation layer 31 and a second implantation layer 40 within the epitaxial transport layer 2; a second ion implantation is performed on the epitaxial transport layer 2 to form a body region 30 within the epitaxial transport layer 2.
Specifically, if the first ions are N-type ions, the second ions are P-type ions; if the first ion is a P-type ion, the second ion is an N-type ion; the N-type ions may include at least one of phosphorus ions, arsenic ions, or antimony ions; the P-type ions may include at least one of boron ions, indium ions, or gallium ions.
The ion implantation may be performed using other element ions, and is not limited to the above-described examples.
In S1022, referring to fig. 7, a first isolation stack 33 is formed on the surface of the first implant layer 31, and a second isolation stack 41 is formed on the surface of the second implant layer 40.
Wherein the simultaneous formation of the first isolation stack 33 and the second isolation stack 41 may be achieved by patterning a mask layer.
Further, still referring to fig. 7, the first isolation stack 33 may include: first isolation layer 331, second isolation layer 332, and third isolation layer 333; the first isolation layer 331 is located on the surface of the first injection layer 31; the second isolation layer 332 is located on the surface of the first isolation layer 331 away from the first injection layer 31; the third isolation layer 333 is located on the surface of the second isolation layer 332 away from the first isolation layer 331. The first separation layer 331 may include, but is not limited to, a TEOS (tetraethyl orthosilicate) layer; the second isolation layer 332 may include, but is not limited to, a BPSG (Boro-phosphate Glass) layer; the third spacer 333 may include, but is not limited to, a TEOS layer.
Still referring to fig. 7, the second isolation stack 41 may include: a fourth insulating layer 411, a fifth insulating layer 412, and a sixth insulating layer 413; the fourth isolation layer 411 is located on the surface of the second injection layer 40; the fifth isolation layer 412 is located on the surface of the fourth isolation layer 411 away from the second implanted layer 40; the sixth spacer 413 is positioned on the surface of the fifth spacer 412 away from the fourth spacer 411. The fourth isolation layer 411 may include, but is not limited to, a TEOS layer; the fifth isolation layer 412 may include, but is not limited to, a BPSG layer; the sixth isolation layer 413 may include, but is not limited to, a TEOS layer.
In S1023, referring to fig. 8, the first isolation stack 33 and the first injection layer 31 are sequentially etched in the thickness direction to form a first contact hole 341, and the second isolation stack 41 and the second injection layer 40 are sequentially etched in the thickness direction to form a second contact hole 421.
Wherein, a dry etching process or a wet etching process may be used to form the first contact hole 341 and the second contact hole 421; the first contact hole 341 and the second contact hole 421 may be formed simultaneously.
In S1024, referring to fig. 9, the first contact hole 341 is filled with the first contact dielectric stack and the first contact conductive layer 344 to form the first contact structure 34, and the second contact hole 421 is filled with the second contact dielectric stack and the second contact conductive layer 424 to form the second contact structure 42.
Still referring to fig. 8 and 9, the first contact dielectric stack includes a first contact dielectric layer 342 and a second contact dielectric layer 343; the first contact dielectric layer 342 is located on the sidewall and the bottom of the first contact hole 341; the second contact dielectric layer 343 is located on the surface of the first contact dielectric layer 342; the first contact conductive layer 344 is located on the surface of the second contact dielectric layer 343 away from the first contact dielectric layer 342.
Illustratively, the first contact dielectric layer 342 may include, but is not limited to, a titanium layer; the second contact dielectric layer 343 may include, but is not limited to, a titanium nitride layer; the first contact conductive layer 344 may include, but is not limited to, a tungsten layer.
Still referring to fig. 9, the second contact dielectric stack includes a third contact dielectric layer 422 and a fourth contact dielectric layer 423; the third contact dielectric layer 422 is located on the sidewall and the bottom of the second contact hole 421; the fourth contact dielectric layer 423 is positioned on the surface of the third contact dielectric layer 422; the second contact conductive layer 424 is located on the surface of the fourth contact dielectric layer 423 away from the third contact dielectric layer 422.
Illustratively, the third contact dielectric layer 422 may include, but is not limited to, a titanium layer; the fourth contact dielectric layer 423 may include, but is not limited to, a titanium nitride layer; the second contact conductive layer 424 may include, but is not limited to, a tungsten layer.
For example, still referring to fig. 9, after forming the first contact structure 34 and the second contact structure 42, the method for fabricating a semiconductor structure further includes: forming a heavily doped region 301 in the body region 30; wherein, the heavily doped region 301 is located below the first contact structure 34 and contacts the first contact structure 34.
Wherein the heavily doped region 301 may be a heavily doped region of the second conductivity type; the heavily doped region 301 has a doping concentration higher than that of the body region 30.
In S1025, referring to fig. 10, a first electrode layer 35 is formed on the surfaces of the first contact structure 34 and the first isolation stack 33 away from the first injection layer 31, and a second electrode layer 43 is formed on the surfaces of the second contact structure 42 and the second isolation stack 41 away from the second injection layer 40; with reference to fig. 10 and fig. 11, the structure to be tested 3 includes a first injection layer 31, a first isolation stack 33, a first contact structure 34, and a first electrode layer 35; the test structure 4 comprises a second injection layer 40, a second isolation stack 41, a second contact structure 42 and a second electrode layer 43.
The first electrode layer 35 and the second electrode layer 43 each include a metal layer.
In one embodiment, after forming the first electrode layer 35 and the second electrode layer 43, the method for manufacturing the semiconductor structure further includes the following steps: forming a reflective layer 36 on the surface of the first electrode layer 35 away from the first isolation stack 33; forming a first passivation layer 37 on the surface of the reflective layer 36 away from the first electrode layer 35; forming a second passivation layer 38 on the surface of the first passivation layer 37 away from the reflective layer 36; sequentially etching the reflective layer 36, the first passivation layer 37 and the second passivation layer 38 along the thickness direction to form a source opening 39; forming a drain layer 5 on the surface of the substrate 1 away from the epitaxial transport layer 2; the structure obtained through the above steps is shown in fig. 1.
The first passivation layer 37 may include, but is not limited to, an oxide layer; the second passivation layer 38 may include, but is not limited to, a nitride layer.
When a second excitation signal and a second detection signal are applied to the test electrode, and a first excitation signal and a first detection signal are applied to the source, the second electrode layer 43 may be used as a test electrode of the test structure 4, when a test current flows through the second electrode layer 43 to the second contact structure 42 and the second injection layer 40 in sequence, and flows from the second injection layer 40 to the epitaxial transport layer 2, then flows through the epitaxial transport layer 2 to the body region 30, the first injection layer 31 and the first contact structure 34 in sequence, and finally flows to the first electrode layer 35 of the test structure 3, a test loop is formed between the test structure 4 and the test structure 3, the test structure 4 is equivalent to a test structure of a drain, and the test electrode is equivalent to a drain electrode, so that the drain and the source in the semiconductor structure are equivalent to be located on the same plane of the semiconductor structure, and conduction is conducted between the source and the drain, and a true kelvin connection method can be realized to measure conduction resistance.
The present application also provides a method for manufacturing a semiconductor device, as shown in fig. 11, the method for manufacturing a semiconductor device includes:
s1101: the semiconductor structure is prepared by adopting the preparation method of the semiconductor structure of any scheme of the application;
s1102: after testing of the semiconductor structure is completed, the device region 201 is separated from the test region 202.
The semiconductor structure and the method for fabricating the semiconductor structure can be described with reference to the embodiments of fig. 1 to 10, and are not repeated herein.
As shown in fig. 1, the semiconductor structure further includes a substrate 1 and a drain layer 5, the substrate 1 is located on the surface of the epitaxial transport layer 2 away from the test structure 4, and the drain layer 5 is located on the surface of the substrate 1 away from the epitaxial transport layer 2; separating the device region 201 from the test region 202 includes: the epitaxial transport layer 2, the substrate 1 and the drain layer 5 are cut or etched in sequence in the thickness direction to separate the device region 201 from the test region 202, and the resulting semiconductor device is shown in fig. 12.
It should be noted that, when the device region 201 is separated from the test region 202, the test structure 4 is also separated from the structure under test 3.
In the manufacturing method of the semiconductor device in the above embodiment, the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure of the present application, wherein the first excitation signal and the first detection signal are received by the source electrode of the semiconductor structure, and the second excitation signal and the second detection signal are received by the test electrode, so that the kelvin connection method is formed; the second excitation signal is transmitted to the source electrode of the structure to be tested 3 through the epitaxial transmission layer 2 through the test structure 4 to form a test loop, the source electrode 39 outputs a first voltage signal, the test electrode outputs a second voltage signal, and the on-resistance of the test loop can be obtained based on the voltage difference between the second voltage signal and the first voltage signal and the second excitation signal; after the test is completed, the device region 201 is separated from the test region 202 to obtain the semiconductor device, and the device region 201 of the semiconductor device is not damaged.
It should be understood that, although the steps in the flowcharts of the embodiments are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the embodiments may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in other steps.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A semiconductor structure, comprising:
the epitaxial transmission layer comprises device areas and test areas which are arranged in an alternating mode;
the structure to be tested is at least partially positioned in the device area;
the test structure is at least partially positioned in the test area, and a space is formed between the test structure and the structure to be tested; wherein,
the source electrode of the structure to be tested is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the test structure transmits the second excitation signal to a source electrode of the structure to be tested through the epitaxial transmission layer to form a test loop; wherein,
the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; the voltage difference between the second voltage signal and the first voltage signal is used for detecting the on-resistance of the structure to be detected;
wherein, the structure to be measured includes:
the first injection layer is positioned in the epitaxial transmission layer;
the first isolation laminated layer is positioned on the surface, away from the epitaxial transmission layer, of the first injection layer;
a first contact structure penetrating the first isolation stack and the first injection layer in a thickness direction;
the first electrode layer is positioned on the surfaces, far away from the first injection layer, of the first isolation laminated layer and the first contact structure;
the test structure includes:
the second injection layer is positioned in the epitaxial transmission layer;
the second isolation laminated layer is positioned on the surface, away from the epitaxial transmission layer, of the second injection layer;
a second contact structure penetrating the second isolation stack and the second injection layer in a thickness direction;
and the second electrode layer is positioned on the surfaces of the second isolation laminated layer and the second contact structure, which are far away from the second injection layer.
2. The semiconductor structure of claim 1, wherein the first detection signal and the second detection signal are voltage signals, respectively.
3. The semiconductor structure of claim 1, wherein the structure under test further comprises:
the body region is positioned in the epitaxial transmission layer, positioned on the surface, away from the first isolation laminated layer, of the first injection layer and contacted with the first contact structure;
and the groove structure is positioned in the epitaxial transmission layer, penetrates through the body region and the first injection layer and is in contact with the first isolation lamination.
4. The semiconductor structure of claim 1, wherein the structure under test further comprises:
the reflecting layer is positioned on the surface of the first electrode layer far away from the first isolation laminated layer;
the first passivation layer is positioned on the surface of the reflecting layer far away from the first electrode layer;
the second passivation layer is positioned on the surface, far away from the reflecting layer, of the first passivation layer;
and the source electrode opening penetrates through the reflecting layer, the first passivation layer and the second passivation layer and exposes part of the first electrode layer.
5. The semiconductor structure of claim 1, wherein the first driving signal and the second driving signal are current signals, respectively.
6. The semiconductor structure of claim 1, wherein the number of the structures to be tested is plural, and the plural structures to be tested are respectively spaced from the test structures; and at least two structures to be tested share the same test structure when being tested.
7. The semiconductor structure of claim 1, wherein the width of the test region is 60 μm to 80 μm; the width of the test structure is 45-55 μm, and the length of the test structure is 65-75 μm.
8. A method of fabricating a semiconductor structure, comprising:
forming an epitaxial transmission layer, wherein the epitaxial transmission layer comprises device areas and test areas which are alternately arranged;
forming a first injection layer and a second injection layer in the epitaxial transport layer, wherein the first injection layer and the second injection layer have a gap;
forming a first isolation lamination on the surface of the first injection layer, and forming a second isolation lamination on the surface of the second injection layer;
sequentially etching the first isolation lamination layer and the first injection layer along the thickness direction to form a first contact hole, and sequentially etching the second isolation lamination layer and the second injection layer along the thickness direction to form a second contact hole;
filling a first contact medium lamination and a first contact conducting layer in the first contact hole to form a first contact structure, and filling a second contact medium lamination and a second contact conducting layer in the second contact hole to form a second contact structure;
forming a first electrode layer on the surfaces of the first contact structure and the first isolation lamination layer, which are far away from the first injection layer, and forming a second electrode layer on the surfaces of the second contact structure and the second isolation lamination layer, which are far away from the second injection layer;
the structure to be tested comprises the first injection layer, the first isolation lamination, the first contact structure and the first electrode layer; the test structure comprises the second injection layer, the second isolation lamination layer, the second contact structure and the second electrode layer; the structure to be tested is at least partially positioned in the device area, the test structure is at least partially positioned in the test area, and a gap is formed between the test structure and the structure to be tested; wherein,
the source electrode of the structure to be tested is used for receiving a first excitation signal and a first detection signal, and the test electrode of the test structure is used for receiving a second excitation signal and a second detection signal; under the action of the first excitation signal and the second excitation signal, the test structure transmits the second excitation signal to a source electrode of the structure to be tested through the epitaxial transmission layer to form a test loop, wherein the first excitation signal and the second excitation signal are different in frequency;
the source electrode is used as a first end of the test loop and used for outputting a first voltage signal; the test pole is used as a second end of the test loop and used for outputting a second voltage signal; and detecting the on-resistance of the structure to be detected by using the voltage difference between the second voltage signal and the first voltage signal.
9. The method of claim 8, wherein prior to forming the first and second implanted layers in the epitaxial transport layer, further comprising: forming a body region in the epitaxial transmission layer; the body region is in contact with the first contact structure, and the first implant layer is formed on the body region.
10. A method of manufacturing a semiconductor device, comprising:
preparing the semiconductor structure by using the preparation method of the semiconductor structure according to claim 8 or 9;
after testing the semiconductor structure is completed, the device region is separated from the test region.
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